Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/mips/loongson/loongson64-2k1000.dtsi
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1 // SPDX-License-Identifier: GPL-2.0 2 3 /dts-v1/; 4 5 #include <dt-bindings/interrupt-controller/irq.h> 6 7 / { 8 compatible = "loongson,loongson2k1000"; 9 10 #address-cells = <2>; 11 #size-cells = <2>; 12 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu0: cpu@0 { 18 device_type = "cpu"; 19 compatible = "loongson,gs264"; 20 reg = <0x0>; 21 #clock-cells = <1>; 22 clocks = <&cpu_clk>; 23 }; 24 }; 25 26 memory@200000 { 27 compatible = "memory"; 28 device_type = "memory"; 29 reg = <0x00000000 0x00200000 0x00000000 0x0ee00000>, /* 238 MB at 2 MB */ 30 <0x00000000 0x20000000 0x00000000 0x1f000000>, /* 496 MB at 512 MB */ 31 <0x00000001 0x10000000 0x00000001 0xb0000000>; /* 6912 MB at 4352MB */ 32 }; 33 34 cpu_clk: cpu_clk { 35 #clock-cells = <0>; 36 compatible = "fixed-clock"; 37 clock-frequency = <800000000>; 38 }; 39 40 cpuintc: interrupt-controller { 41 #address-cells = <0>; 42 #interrupt-cells = <1>; 43 interrupt-controller; 44 compatible = "mti,cpu-interrupt-controller"; 45 }; 46 47 package0: bus@10000000 { 48 compatible = "simple-bus"; 49 #address-cells = <2>; 50 #size-cells = <2>; 51 ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* ioports */ 52 0 0x40000000 0 0x40000000 0 0x40000000 53 0xfe 0x00000000 0xfe 0x00000000 0 0x40000000>; 54 55 pm: reset-controller@1fe07000 { 56 compatible = "loongson,ls2k-pm"; 57 reg = <0 0x1fe07000 0 0x422>; 58 }; 59 60 liointc0: interrupt-controller@1fe11400 { 61 compatible = "loongson,liointc-2.0"; 62 reg = <0 0x1fe11400 0 0x40>, 63 <0 0x1fe11040 0 0x8>, 64 <0 0x1fe11140 0 0x8>; 65 reg-names = "main", "isr0", "isr1"; 66 67 interrupt-controller; 68 #interrupt-cells = <2>; 69 70 interrupt-parent = <&cpuintc>; 71 interrupts = <2>; 72 interrupt-names = "int0"; 73 74 loongson,parent_int_map = <0xffffffff>, /* int0 */ 75 <0x00000000>, /* int1 */ 76 <0x00000000>, /* int2 */ 77 <0x00000000>; /* int3 */ 78 }; 79 80 liointc1: interrupt-controller@1fe11440 { 81 compatible = "loongson,liointc-2.0"; 82 reg = <0 0x1fe11440 0 0x40>, 83 <0 0x1fe11048 0 0x8>, 84 <0 0x1fe11148 0 0x8>; 85 reg-names = "main", "isr0", "isr1"; 86 87 interrupt-controller; 88 #interrupt-cells = <2>; 89 90 interrupt-parent = <&cpuintc>; 91 interrupts = <3>; 92 interrupt-names = "int1"; 93 94 loongson,parent_int_map = <0x00000000>, /* int0 */ 95 <0xffffffff>, /* int1 */ 96 <0x00000000>, /* int2 */ 97 <0x00000000>; /* int3 */ 98 }; 99 100 uart0: serial@1fe00000 { 101 compatible = "ns16550a"; 102 reg = <0 0x1fe00000 0 0x8>; 103 clock-frequency = <125000000>; 104 interrupt-parent = <&liointc0>; 105 interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 106 no-loopback-test; 107 }; 108 109 pci@1a000000 { 110 compatible = "loongson,ls2k-pci"; 111 device_type = "pci"; 112 #address-cells = <3>; 113 #size-cells = <2>; 114 #interrupt-cells = <2>; 115 116 reg = <0 0x1a000000 0 0x02000000>, 117 <0xfe 0x00000000 0 0x20000000>; 118 119 ranges = <0x01000000 0x0 0x00000000 0x0 0x18000000 0x0 0x00010000>, 120 <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>; 121 122 gmac@3,0 { 123 compatible = "pci0014,7a03.0", 124 "pci0014,7a03", 125 "pciclass0c0320", 126 "pciclass0c03", 127 "loongson, pci-gmac"; 128 129 reg = <0x1800 0x0 0x0 0x0 0x0>; 130 interrupts = <12 IRQ_TYPE_LEVEL_LOW>, 131 <13 IRQ_TYPE_LEVEL_LOW>; 132 interrupt-names = "macirq", "eth_lpi"; 133 interrupt-parent = <&liointc0>; 134 phy-mode = "rgmii"; 135 mdio { 136 #address-cells = <1>; 137 #size-cells = <0>; 138 compatible = "snps,dwmac-mdio"; 139 phy0: ethernet-phy@0 { 140 reg = <0>; 141 }; 142 }; 143 }; 144 145 gmac@3,1 { 146 compatible = "pci0014,7a03.0", 147 "pci0014,7a03", 148 "pciclass0c0320", 149 "pciclass0c03", 150 "loongson, pci-gmac"; 151 152 reg = <0x1900 0x0 0x0 0x0 0x0>; 153 interrupts = <14 IRQ_TYPE_LEVEL_LOW>, 154 <15 IRQ_TYPE_LEVEL_LOW>; 155 interrupt-names = "macirq", "eth_lpi"; 156 interrupt-parent = <&liointc0>; 157 phy-mode = "rgmii"; 158 mdio { 159 #address-cells = <1>; 160 #size-cells = <0>; 161 compatible = "snps,dwmac-mdio"; 162 phy1: ethernet-phy@1 { 163 reg = <0>; 164 }; 165 }; 166 }; 167 168 ehci@4,1 { 169 compatible = "pci0014,7a14.0", 170 "pci0014,7a14", 171 "pciclass0c0320", 172 "pciclass0c03"; 173 174 reg = <0x2100 0x0 0x0 0x0 0x0>; 175 interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 176 interrupt-parent = <&liointc1>; 177 }; 178 179 ohci@4,2 { 180 compatible = "pci0014,7a24.0", 181 "pci0014,7a24", 182 "pciclass0c0310", 183 "pciclass0c03"; 184 185 reg = <0x2200 0x0 0x0 0x0 0x0>; 186 interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 187 interrupt-parent = <&liointc1>; 188 }; 189 190 sata@8,0 { 191 compatible = "pci0014,7a08.0", 192 "pci0014,7a08", 193 "pciclass010601", 194 "pciclass0106"; 195 196 reg = <0x4000 0x0 0x0 0x0 0x0>; 197 interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 198 interrupt-parent = <&liointc0>; 199 }; 200 201 pci_bridge@9,0 { 202 compatible = "pci0014,7a19.0", 203 "pci0014,7a19", 204 "pciclass060400", 205 "pciclass0604"; 206 207 reg = <0x4800 0x0 0x0 0x0 0x0>; 208 #interrupt-cells = <1>; 209 interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 210 interrupt-parent = <&liointc1>; 211 interrupt-map-mask = <0 0 0 0>; 212 interrupt-map = <0 0 0 0 &liointc1 0 IRQ_TYPE_LEVEL_LOW>; 213 external-facing; 214 }; 215 216 pci_bridge@a,0 { 217 compatible = "pci0014,7a09.0", 218 "pci0014,7a09", 219 "pciclass060400", 220 "pciclass0604"; 221 222 reg = <0x5000 0x0 0x0 0x0 0x0>; 223 #interrupt-cells = <1>; 224 interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 225 interrupt-parent = <&liointc1>; 226 interrupt-map-mask = <0 0 0 0>; 227 interrupt-map = <0 0 0 0 &liointc1 1 IRQ_TYPE_LEVEL_LOW>; 228 external-facing; 229 }; 230 231 pci_bridge@b,0 { 232 compatible = "pci0014,7a09.0", 233 "pci0014,7a09", 234 "pciclass060400", 235 "pciclass0604"; 236 237 reg = <0x5800 0x0 0x0 0x0 0x0>; 238 #interrupt-cells = <1>; 239 interrupts = <2 IRQ_TYPE_LEVEL_LOW>; 240 interrupt-parent = <&liointc1>; 241 interrupt-map-mask = <0 0 0 0>; 242 interrupt-map = <0 0 0 0 &liointc1 2 IRQ_TYPE_LEVEL_LOW>; 243 external-facing; 244 }; 245 246 pci_bridge@c,0 { 247 compatible = "pci0014,7a09.0", 248 "pci0014,7a09", 249 "pciclass060400", 250 "pciclass0604"; 251 252 reg = <0x6000 0x0 0x0 0x0 0x0>; 253 #interrupt-cells = <1>; 254 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 255 interrupt-parent = <&liointc1>; 256 interrupt-map-mask = <0 0 0 0>; 257 interrupt-map = <0 0 0 0 &liointc1 3 IRQ_TYPE_LEVEL_LOW>; 258 external-facing; 259 }; 260 261 pci_bridge@d,0 { 262 compatible = "pci0014,7a19.0", 263 "pci0014,7a19", 264 "pciclass060400", 265 "pciclass0604"; 266 267 reg = <0x6800 0x0 0x0 0x0 0x0>; 268 #interrupt-cells = <1>; 269 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 270 interrupt-parent = <&liointc1>; 271 interrupt-map-mask = <0 0 0 0>; 272 interrupt-map = <0 0 0 0 &liointc1 4 IRQ_TYPE_LEVEL_LOW>; 273 external-facing; 274 }; 275 276 pci_bridge@e,0 { 277 compatible = "pci0014,7a09.0", 278 "pci0014,7a09", 279 "pciclass060400", 280 "pciclass0604"; 281 282 reg = <0x7000 0x0 0x0 0x0 0x0>; 283 #interrupt-cells = <1>; 284 interrupts = <5 IRQ_TYPE_LEVEL_LOW>; 285 interrupt-parent = <&liointc1>; 286 interrupt-map-mask = <0 0 0 0>; 287 interrupt-map = <0 0 0 0 &liointc1 5 IRQ_TYPE_LEVEL_LOW>; 288 external-facing; 289 }; 290 291 }; 292 }; 293 }; 294
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