3c120_devboard.dts

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    1 // SPDX-License-Identifier: GPL-2.0-or-later
    2 /*
    3  *  Copyright (C) 2013 Altera Corporation
    4  *
    5  * This file is generated by sopc2dts.
    6  */
    7 
    8 /dts-v1/;
    9 
   10 / {
   11         model = "altr,qsys_ghrd_3c120";
   12         compatible = "altr,qsys_ghrd_3c120";
   13         #address-cells = <1>;
   14         #size-cells = <1>;
   15 
   16         cpus {
   17                 #address-cells = <1>;
   18                 #size-cells = <0>;
   19 
   20                 cpu: cpu@0 {
   21                         device_type = "cpu";
   22                         compatible = "altr,nios2-1.0";
   23                         reg = <0x00000000>;
   24                         interrupt-controller;
   25                         #interrupt-cells = <1>;
   26                         clock-frequency = <125000000>;
   27                         dcache-line-size = <32>;
   28                         icache-line-size = <32>;
   29                         dcache-size = <32768>;
   30                         icache-size = <32768>;
   31                         altr,implementation = "fast";
   32                         altr,pid-num-bits = <8>;
   33                         altr,tlb-num-ways = <16>;
   34                         altr,tlb-num-entries = <128>;
   35                         altr,tlb-ptr-sz = <7>;
   36                         altr,has-div = <1>;
   37                         altr,has-mul = <1>;
   38                         altr,reset-addr = <0xc2800000>;
   39                         altr,fast-tlb-miss-addr = <0xc7fff400>;
   40                         altr,exception-addr = <0xd0000020>;
   41                         altr,has-initda = <1>;
   42                         altr,has-mmu = <1>;
   43                 };
   44         };
   45 
   46         memory@0 {
   47                 device_type = "memory";
   48                 reg = <0x10000000 0x08000000>,
   49                         <0x07fff400 0x00000400>;
   50         };
   51 
   52         sopc@0 {
   53                 device_type = "soc";
   54                 ranges;
   55                 #address-cells = <1>;
   56                 #size-cells = <1>;
   57                 compatible = "altr,avalon", "simple-bus";
   58                 bus-frequency = <125000000>;
   59 
   60                 pb_cpu_to_io: bridge@8000000 {
   61                         compatible = "simple-bus";
   62                         reg = <0x08000000 0x00800000>;
   63                         #address-cells = <1>;
   64                         #size-cells = <1>;
   65                         ranges = <0x00002000 0x08002000 0x00002000>,
   66                                 <0x00004000 0x08004000 0x00000400>,
   67                                 <0x00004400 0x08004400 0x00000040>,
   68                                 <0x00004800 0x08004800 0x00000040>,
   69                                 <0x00004c80 0x08004c80 0x00000020>,
   70                                 <0x00004d50 0x08004d50 0x00000008>,
   71                                 <0x00008000 0x08008000 0x00000020>,
   72                                 <0x00400000 0x08400000 0x00000020>;
   73 
   74                         timer_1ms: timer@400000 {
   75                                 compatible = "altr,timer-1.0";
   76                                 reg = <0x00400000 0x00000020>;
   77                                 interrupt-parent = <&cpu>;
   78                                 interrupts = <11>;
   79                                 clock-frequency = <125000000>;
   80                         };
   81 
   82                         timer_0: timer@8000 {
   83                                 compatible = "altr,timer-1.0";
   84                                 reg = < 0x00008000 0x00000020 >;
   85                                 interrupt-parent = < &cpu >;
   86                                 interrupts = < 5 >;
   87                                 clock-frequency = < 125000000 >;
   88                         };
   89 
   90                         jtag_uart: serial@4d50 {
   91                                 compatible = "altr,juart-1.0";
   92                                 reg = <0x00004d50 0x00000008>;
   93                                 interrupt-parent = <&cpu>;
   94                                 interrupts = <1>;
   95                         };
   96 
   97                         tse_mac: ethernet@4000 {
   98                                 compatible = "altr,tse-1.0";
   99                                 reg = <0x00004000 0x00000400>,
  100                                         <0x00004400 0x00000040>,
  101                                         <0x00004800 0x00000040>,
  102                                         <0x00002000 0x00002000>;
  103                                 reg-names = "control_port", "rx_csr", "tx_csr", "s1";
  104                                 interrupt-parent = <&cpu>;
  105                                 interrupts = <2 3>;
  106                                 interrupt-names = "rx_irq", "tx_irq";
  107                                 rx-fifo-depth = <8192>;
  108                                 tx-fifo-depth = <8192>;
  109                                 max-frame-size = <1518>;
  110                                 local-mac-address = [ 00 00 00 00 00 00 ];
  111                                 phy-mode = "rgmii-id";
  112                                 phy-handle = <&phy0>;
  113                                 tse_mac_mdio: mdio {
  114                                         compatible = "altr,tse-mdio";
  115                                         #address-cells = <1>;
  116                                         #size-cells = <0>;
  117                                         phy0: ethernet-phy@18 {
  118                                                 reg = <18>;
  119                                                 device_type = "ethernet-phy";
  120                                         };
  121                                 };
  122                         };
  123 
  124                         uart: serial@4c80 {
  125                                 compatible = "altr,uart-1.0";
  126                                 reg = <0x00004c80 0x00000020>;
  127                                 interrupt-parent = <&cpu>;
  128                                 interrupts = <10>;
  129                                 current-speed = <115200>;
  130                                 clock-frequency = <62500000>;
  131                         };
  132                 };
  133 
  134                 cfi_flash_64m: flash@0 {
  135                         compatible = "cfi-flash";
  136                         reg = <0x00000000 0x04000000>;
  137                         bank-width = <2>;
  138                         device-width = <1>;
  139                         #address-cells = <1>;
  140                         #size-cells = <1>;
  141 
  142                         partition@800000 {
  143                                 reg = <0x00800000 0x01e00000>;
  144                                 label = "JFFS2 Filesystem";
  145                         };
  146                 };
  147         };
  148 
  149         chosen {
  150                 bootargs = "debug earlycon console=ttyJ0,115200";
  151                 stdout-path = &jtag_uart;
  152         };
  153 };

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/nios2/3c120_devboard.dts

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/nios2/3c120_devboard.dts