The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)

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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/openrisc/or1ksim.dts

Version: -  FREEBSD  -  FREEBSD-13-STABLE  -  FREEBSD-13-0  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  l41  -  OPENBSD  -  linux-2.6  -  MK84  -  PLAN9  -  xnu-8792 
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    1 // SPDX-License-Identifier: GPL-2.0
    2 /dts-v1/;
    3 / {
    4         compatible = "opencores,or1ksim";
    5         #address-cells = <1>;
    6         #size-cells = <1>;
    7         interrupt-parent = <&pic>;
    8 
    9         aliases {
   10                 uart0 = &serial0;
   11         };
   12 
   13         chosen {
   14                 bootargs = "earlycon";
   15                 stdout-path = "uart0:115200";
   16         };
   17 
   18         memory@0 {
   19                 device_type = "memory";
   20                 reg = <0x00000000 0x02000000>;
   21         };
   22 
   23         cpus {
   24                 #address-cells = <1>;
   25                 #size-cells = <0>;
   26                 cpu@0 {
   27                         compatible = "opencores,or1200-rtlsvn481";
   28                         reg = <0>;
   29                         clock-frequency = <20000000>;
   30                 };
   31         };
   32 
   33         /*
   34          * OR1K PIC is built into CPU and accessed via special purpose
   35          * registers.  It is not addressable and, hence, has no 'reg'
   36          * property.
   37          */
   38         pic: pic {
   39                 compatible = "opencores,or1k-pic";
   40                 #interrupt-cells = <1>;
   41                 interrupt-controller;
   42         };
   43 
   44         serial0: serial@90000000 {
   45                 compatible = "opencores,uart16550-rtlsvn105", "ns16550a";
   46                 reg = <0x90000000 0x100>;
   47                 interrupts = <2>;
   48                 clock-frequency = <20000000>;
   49         };
   50 
   51         enet0: ethoc@92000000 {
   52                 compatible = "opencores,ethoc";
   53                 reg = <0x92000000 0x800>;
   54                 interrupts = <4>;
   55                 big-endian;
   56         };
   57 };

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