The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)

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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/openrisc/simple_smp.dts

Version: -  FREEBSD  -  FREEBSD-13-STABLE  -  FREEBSD-13-0  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  l41  -  OPENBSD  -  linux-2.6  -  MK84  -  PLAN9  -  xnu-8792 
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    1 /dts-v1/;
    2 / {
    3         compatible = "opencores,or1ksim";
    4         #address-cells = <1>;
    5         #size-cells = <1>;
    6         interrupt-parent = <&pic>;
    7 
    8         aliases {
    9                 uart0 = &serial0;
   10         };
   11 
   12         chosen {
   13                 bootargs = "earlycon";
   14                 stdout-path = "uart0:115200";
   15         };
   16 
   17         memory@0 {
   18                 device_type = "memory";
   19                 reg = <0x00000000 0x02000000>;
   20         };
   21 
   22         cpus {
   23                 #address-cells = <1>;
   24                 #size-cells = <0>;
   25                 cpu@0 {
   26                         compatible = "opencores,or1200-rtlsvn481";
   27                         reg = <0>;
   28                         clock-frequency = <20000000>;
   29                 };
   30                 cpu@1 {
   31                         compatible = "opencores,or1200-rtlsvn481";
   32                         reg = <1>;
   33                         clock-frequency = <20000000>;
   34                 };
   35         };
   36 
   37         ompic: ompic@98000000 {
   38                 compatible = "openrisc,ompic";
   39                 reg = <0x98000000 16>;
   40                 interrupt-controller;
   41                 #interrupt-cells = <0>;
   42                 interrupts = <1>;
   43         };
   44 
   45         /*
   46          * OR1K PIC is built into CPU and accessed via special purpose
   47          * registers.  It is not addressable and, hence, has no 'reg'
   48          * property.
   49          */
   50         pic: pic {
   51                 compatible = "opencores,or1k-pic-level";
   52                 #interrupt-cells = <1>;
   53                 interrupt-controller;
   54         };
   55 
   56         serial0: serial@90000000 {
   57                 compatible = "opencores,uart16550-rtlsvn105", "ns16550a";
   58                 reg = <0x90000000 0x100>;
   59                 interrupts = <2>;
   60                 clock-frequency = <20000000>;
   61         };
   62 
   63         enet0: ethoc@92000000 {
   64                 compatible = "opencores,ethoc";
   65                 reg = <0x92000000 0x800>;
   66                 interrupts = <4>;
   67                 big-endian;
   68         };
   69 };

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