mpc8544si-post.dtsi

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    1 /*
    2  * MPC8544 Silicon/SoC Device Tree Source (post include)
    3  *
    4  * Copyright 2011 Freescale Semiconductor Inc.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions are met:
    8  *     * Redistributions of source code must retain the above copyright
    9  *       notice, this list of conditions and the following disclaimer.
   10  *     * Redistributions in binary form must reproduce the above copyright
   11  *       notice, this list of conditions and the following disclaimer in the
   12  *       documentation and/or other materials provided with the distribution.
   13  *     * Neither the name of Freescale Semiconductor nor the
   14  *       names of its contributors may be used to endorse or promote products
   15  *       derived from this software without specific prior written permission.
   16  *
   17  *
   18  * ALTERNATIVELY, this software may be distributed under the terms of the
   19  * GNU General Public License ("GPL") as published by the Free Software
   20  * Foundation, either version 2 of that License or (at your option) any
   21  * later version.
   22  *
   23  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
   24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
   25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
   26  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
   27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
   28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
   29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
   30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
   32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   33  */
   34 
   35 &lbc {
   36         #address-cells = <2>;
   37         #size-cells = <1>;
   38         compatible = "fsl,mpc8544-lbc", "fsl,pq3-localbus", "simple-bus";
   39         interrupts = <19 2 0 0>;
   40 };
   41 
   42 /* controller at 0x8000 */
   43 &pci0 {
   44         compatible = "fsl,mpc8540-pci";
   45         device_type = "pci";
   46         interrupts = <24 0x2 0 0>;
   47         bus-range = <0 0xff>;
   48         #interrupt-cells = <1>;
   49         #size-cells = <2>;
   50         #address-cells = <3>;
   51 };
   52 
   53 /* controller at 0x9000 */
   54 &pci1 {
   55         compatible = "fsl,mpc8548-pcie";
   56         device_type = "pci";
   57         #size-cells = <2>;
   58         #address-cells = <3>;
   59         bus-range = <0 255>;
   60         clock-frequency = <33333333>;
   61         interrupts = <25 2 0 0>;
   62 
   63         pcie@0 {
   64                 reg = <0 0 0 0 0>;
   65                 #interrupt-cells = <1>;
   66                 #size-cells = <2>;
   67                 #address-cells = <3>;
   68                 device_type = "pci";
   69                 interrupts = <25 2 0 0>;
   70                 interrupt-map-mask = <0xf800 0 0 7>;
   71 
   72                 interrupt-map = <
   73                         /* IDSEL 0x0 */
   74                         0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
   75                         0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
   76                         0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
   77                         0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
   78                         >;
   79         };
   80 };
   81 
   82 /* controller at 0xa000 */
   83 &pci2 {
   84         compatible = "fsl,mpc8548-pcie";
   85         device_type = "pci";
   86         #size-cells = <2>;
   87         #address-cells = <3>;
   88         bus-range = <0 255>;
   89         clock-frequency = <33333333>;
   90         interrupts = <26 2 0 0>;
   91 
   92         pcie@0 {
   93                 reg = <0 0 0 0 0>;
   94                 #interrupt-cells = <1>;
   95                 #size-cells = <2>;
   96                 #address-cells = <3>;
   97                 device_type = "pci";
   98                 interrupts = <26 2 0 0>;
   99                 interrupt-map-mask = <0xf800 0 0 7>;
  100                 interrupt-map = <
  101                         /* IDSEL 0x0 */
  102                         0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
  103                         0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
  104                         0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
  105                         0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
  106                         >;
  107         };
  108 };
  109 
  110 /* controller at 0xb000 */
  111 &pci3 {
  112         compatible = "fsl,mpc8548-pcie";
  113         device_type = "pci";
  114         #size-cells = <2>;
  115         #address-cells = <3>;
  116         bus-range = <0 255>;
  117         clock-frequency = <33333333>;
  118         interrupts = <27 2 0 0>;
  119 
  120         pcie@0 {
  121                 reg = <0 0 0 0 0>;
  122                 #interrupt-cells = <1>;
  123                 #size-cells = <2>;
  124                 #address-cells = <3>;
  125                 device_type = "pci";
  126                 interrupts = <27 2 0 0>;
  127                 interrupt-map-mask = <0xf800 0 0 7>;
  128                 interrupt-map = <
  129                         /* IDSEL 0x0 */
  130                         0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
  131                         0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
  132                         0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
  133                         0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
  134                         >;
  135         };
  136 };
  137 
  138 &soc {
  139         #address-cells = <1>;
  140         #size-cells = <1>;
  141         device_type = "soc";
  142         compatible = "fsl,mpc8544-immr", "simple-bus";
  143         bus-frequency = <0>;            // Filled out by uboot.
  144 
  145         ecm-law@0 {
  146                 compatible = "fsl,ecm-law";
  147                 reg = <0x0 0x1000>;
  148                 fsl,num-laws = <10>;
  149         };
  150 
  151         ecm@1000 {
  152                 compatible = "fsl,mpc8544-ecm", "fsl,ecm";
  153                 reg = <0x1000 0x1000>;
  154                 interrupts = <17 2 0 0>;
  155         };
  156 
  157         memory-controller@2000 {
  158                 compatible = "fsl,mpc8544-memory-controller";
  159                 reg = <0x2000 0x1000>;
  160                 interrupts = <18 2 0 0>;
  161         };
  162 
  163 /include/ "pq3-i2c-0.dtsi"
  164 /include/ "pq3-i2c-1.dtsi"
  165 /include/ "pq3-duart-0.dtsi"
  166 
  167         L2: l2-cache-controller@20000 {
  168                 compatible = "fsl,mpc8544-l2-cache-controller";
  169                 reg = <0x20000 0x1000>;
  170                 cache-line-size = <32>; // 32 bytes
  171                 cache-size = <0x40000>; // L2, 256K
  172                 interrupts = <16 2 0 0>;
  173         };
  174 
  175 /include/ "pq3-dma-0.dtsi"
  176 /include/ "pq3-etsec1-0.dtsi"
  177 /include/ "pq3-etsec1-2.dtsi"
  178 
  179         ethernet@26000 {
  180                 cell-index = <1>;
  181         };
  182 
  183 /include/ "pq3-sec2.1-0.dtsi"
  184 /include/ "pq3-mpic.dtsi"
  185 
  186         global-utilities@e0000 {
  187                 compatible = "fsl,mpc8544-guts";
  188                 reg = <0xe0000 0x1000>;
  189                 fsl,has-rstcr;
  190         };
  191 };

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