The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/powerpc/fsl/mpc8568mds.dts

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    1 // SPDX-License-Identifier: GPL-2.0-or-later
    2 /*
    3  * MPC8568E MDS Device Tree Source
    4  *
    5  * Copyright 2007, 2008 Freescale Semiconductor Inc.
    6  */
    7 
    8 /include/ "mpc8568si-pre.dtsi"
    9 
   10 / {
   11         model = "MPC8568EMDS";
   12         compatible = "MPC8568EMDS", "MPC85xxMDS";
   13 
   14         aliases {
   15                 pci0 = &pci0;
   16                 pci1 = &pci1;
   17                 rapidio0 = &rio;
   18         };
   19 
   20         memory {
   21                 device_type = "memory";
   22                 reg = <0x0 0x0 0x0 0x0>;
   23         };
   24 
   25         lbc: localbus@e0005000 {
   26                 reg = <0x0 0xe0005000 0x0 0x1000>;
   27                 ranges = <0x0 0x0 0xfe000000 0x02000000
   28                           0x1 0x0 0xf8000000 0x00008000
   29                           0x2 0x0 0xf0000000 0x04000000
   30                           0x4 0x0 0xf8008000 0x00008000
   31                           0x5 0x0 0xf8010000 0x00008000>;
   32 
   33                 nor@0,0 {
   34                         #address-cells = <1>;
   35                         #size-cells = <1>;
   36                         compatible = "cfi-flash";
   37                         reg = <0x0 0x0 0x02000000>;
   38                         bank-width = <2>;
   39                         device-width = <2>;
   40                 };
   41 
   42                 bcsr@1,0 {
   43                         #address-cells = <1>;
   44                         #size-cells = <1>;
   45                         compatible = "fsl,mpc8568mds-bcsr";
   46                         reg = <1 0 0x8000>;
   47                         ranges = <0 1 0 0x8000>;
   48 
   49                         bcsr5: gpio-controller@11 {
   50                                 #gpio-cells = <2>;
   51                                 compatible = "fsl,mpc8568mds-bcsr-gpio";
   52                                 reg = <0x5 0x1>;
   53                                 gpio-controller;
   54                         };
   55                 };
   56 
   57                 pib@4,0 {
   58                         compatible = "fsl,mpc8568mds-pib";
   59                         reg = <4 0 0x8000>;
   60                 };
   61 
   62                 pib@5,0 {
   63                         compatible = "fsl,mpc8568mds-pib";
   64                         reg = <5 0 0x8000>;
   65                 };
   66         };
   67 
   68         soc: soc8568@e0000000 {
   69                 ranges = <0x0 0x0 0xe0000000 0x100000>;
   70 
   71                 i2c-sleep-nexus {
   72                         i2c@3000 {
   73                                 rtc@68 {
   74                                         compatible = "dallas,ds1374";
   75                                         reg = <0x68>;
   76                                         interrupts = <3 1 0 0>;
   77                                 };
   78                         };
   79                 };
   80 
   81                 enet0: ethernet@24000 {
   82                         tbi-handle = <&tbi0>;
   83                         phy-handle = <&phy2>;
   84                 };
   85 
   86                 mdio@24520 {
   87                         phy0: ethernet-phy@7 {
   88                                 interrupts = <1 1 0 0>;
   89                                 reg = <0x7>;
   90                         };
   91                         phy1: ethernet-phy@1 {
   92                                 interrupts = <2 1 0 0>;
   93                                 reg = <0x1>;
   94                         };
   95                         phy2: ethernet-phy@2 {
   96                                 interrupts = <1 1 0 0>;
   97                                 reg = <0x2>;
   98                         };
   99                         phy3: ethernet-phy@3 {
  100                                 interrupts = <2 1 0 0>;
  101                                 reg = <0x3>;
  102                         };
  103                         tbi0: tbi-phy@11 {
  104                                 reg = <0x11>;
  105                                 device_type = "tbi-phy";
  106                         };
  107                 };
  108 
  109                 enet1: ethernet@25000 {
  110                         tbi-handle = <&tbi1>;
  111                         phy-handle = <&phy3>;
  112                         sleep = <&pmc 0x00000040>;
  113                 };
  114 
  115                 mdio@25520 {
  116                         tbi1: tbi-phy@11 {
  117                                 reg = <0x11>;
  118                                 device_type = "tbi-phy";
  119                         };
  120                 };
  121 
  122                 par_io@e0100 {
  123                         num-ports = <7>;
  124 
  125                         pio1: ucc_pin@1 {
  126                                 pio-map = <
  127                         /* port  pin  dir  open_drain  assignment  has_irq */
  128                                         0x4  0xa  0x1  0x0  0x2  0x0    /* TxD0 */
  129                                         0x4  0x9  0x1  0x0  0x2  0x0    /* TxD1 */
  130                                         0x4  0x8  0x1  0x0  0x2  0x0    /* TxD2 */
  131                                         0x4  0x7  0x1  0x0  0x2  0x0    /* TxD3 */
  132                                         0x4  0x17  0x1  0x0  0x2  0x0   /* TxD4 */
  133                                         0x4  0x16  0x1  0x0  0x2  0x0   /* TxD5 */
  134                                         0x4  0x15  0x1  0x0  0x2  0x0   /* TxD6 */
  135                                         0x4  0x14  0x1  0x0  0x2  0x0   /* TxD7 */
  136                                         0x4  0xf  0x2  0x0  0x2  0x0    /* RxD0 */
  137                                         0x4  0xe  0x2  0x0  0x2  0x0    /* RxD1 */
  138                                         0x4  0xd  0x2  0x0  0x2  0x0    /* RxD2 */
  139                                         0x4  0xc  0x2  0x0  0x2  0x0    /* RxD3 */
  140                                         0x4  0x1d  0x2  0x0  0x2  0x0   /* RxD4 */
  141                                         0x4  0x1c  0x2  0x0  0x2  0x0   /* RxD5 */
  142                                         0x4  0x1b  0x2  0x0  0x2  0x0   /* RxD6 */
  143                                         0x4  0x1a  0x2  0x0  0x2  0x0   /* RxD7 */
  144                                         0x4  0xb  0x1  0x0  0x2  0x0    /* TX_EN */
  145                                         0x4  0x18  0x1  0x0  0x2  0x0   /* TX_ER */
  146                                         0x4  0x10  0x2  0x0  0x2  0x0   /* RX_DV */
  147                                         0x4  0x1e  0x2  0x0  0x2  0x0   /* RX_ER */
  148                                         0x4  0x11  0x2  0x0  0x2  0x0   /* RX_CLK */
  149                                         0x4  0x13  0x1  0x0  0x2  0x0   /* GTX_CLK */
  150                                         0x1  0x1f  0x2  0x0  0x3  0x0>; /* GTX125 */
  151                         };
  152 
  153                         pio2: ucc_pin@2 {
  154                                 pio-map = <
  155                         /* port  pin  dir  open_drain  assignment  has_irq */
  156                                         0x5  0xa 0x1  0x0  0x2  0x0   /* TxD0 */
  157                                         0x5  0x9 0x1  0x0  0x2  0x0   /* TxD1 */
  158                                         0x5  0x8 0x1  0x0  0x2  0x0   /* TxD2 */
  159                                         0x5  0x7 0x1  0x0  0x2  0x0   /* TxD3 */
  160                                         0x5  0x17 0x1  0x0  0x2  0x0   /* TxD4 */
  161                                         0x5  0x16 0x1  0x0  0x2  0x0   /* TxD5 */
  162                                         0x5  0x15 0x1  0x0  0x2  0x0   /* TxD6 */
  163                                         0x5  0x14 0x1  0x0  0x2  0x0   /* TxD7 */
  164                                         0x5  0xf 0x2  0x0  0x2  0x0   /* RxD0 */
  165                                         0x5  0xe 0x2  0x0  0x2  0x0   /* RxD1 */
  166                                         0x5  0xd 0x2  0x0  0x2  0x0   /* RxD2 */
  167                                         0x5  0xc 0x2  0x0  0x2  0x0   /* RxD3 */
  168                                         0x5  0x1d 0x2  0x0  0x2  0x0   /* RxD4 */
  169                                         0x5  0x1c 0x2  0x0  0x2  0x0   /* RxD5 */
  170                                         0x5  0x1b 0x2  0x0  0x2  0x0   /* RxD6 */
  171                                         0x5  0x1a 0x2  0x0  0x2  0x0   /* RxD7 */
  172                                         0x5  0xb 0x1  0x0  0x2  0x0   /* TX_EN */
  173                                         0x5  0x18 0x1  0x0  0x2  0x0   /* TX_ER */
  174                                         0x5  0x10 0x2  0x0  0x2  0x0   /* RX_DV */
  175                                         0x5  0x1e 0x2  0x0  0x2  0x0   /* RX_ER */
  176                                         0x5  0x11 0x2  0x0  0x2  0x0   /* RX_CLK */
  177                                         0x5  0x13 0x1  0x0  0x2  0x0   /* GTX_CLK */
  178                                         0x1  0x1f 0x2  0x0  0x3  0x0   /* GTX125 */
  179                                         0x4  0x6 0x3  0x0  0x2  0x0   /* MDIO */
  180                                         0x4  0x5 0x1  0x0  0x2  0x0>; /* MDC */
  181                         };
  182                 };
  183         };
  184 
  185         qe: qe@e0080000 {
  186                 ranges = <0x0 0x0 0xe0080000 0x40000>;
  187                 reg = <0x0 0xe0080000 0x0 0x480>;
  188 
  189                 spi@4c0 {
  190                         mode = "cpu";
  191                 };
  192 
  193                 spi@500 {
  194                         mode = "cpu";
  195                 };
  196 
  197                 enet2: ucc@2000 {
  198                         device_type = "network";
  199                         compatible = "ucc_geth";
  200                         local-mac-address = [ 00 00 00 00 00 00 ];
  201                         rx-clock-name = "none";
  202                         tx-clock-name = "clk16";
  203                         pio-handle = <&pio1>;
  204                         phy-handle = <&phy0>;
  205                         phy-connection-type = "rgmii-id";
  206                 };
  207 
  208                 enet3: ucc@3000 {
  209                         device_type = "network";
  210                         compatible = "ucc_geth";
  211                         local-mac-address = [ 00 00 00 00 00 00 ];
  212                         rx-clock-name = "none";
  213                         tx-clock-name = "clk16";
  214                         pio-handle = <&pio2>;
  215                         phy-handle = <&phy1>;
  216                         phy-connection-type = "rgmii-id";
  217                 };
  218 
  219                 mdio@2120 {
  220                         #address-cells = <1>;
  221                         #size-cells = <0>;
  222                         reg = <0x2120 0x18>;
  223                         compatible = "fsl,ucc-mdio";
  224 
  225                         /* These are the same PHYs as on
  226                          * gianfar's MDIO bus */
  227                         qe_phy0: ethernet-phy@7 {
  228                                 interrupt-parent = <&mpic>;
  229                                 interrupts = <1 1 0 0>;
  230                                 reg = <0x7>;
  231                         };
  232                         qe_phy1: ethernet-phy@1 {
  233                                 interrupt-parent = <&mpic>;
  234                                 interrupts = <2 1 0 0>;
  235                                 reg = <0x1>;
  236                         };
  237                         qe_phy2: ethernet-phy@2 {
  238                                 interrupt-parent = <&mpic>;
  239                                 interrupts = <1 1 0 0>;
  240                                 reg = <0x2>;
  241                         };
  242                         qe_phy3: ethernet-phy@3 {
  243                                 interrupt-parent = <&mpic>;
  244                                 interrupts = <2 1 0 0>;
  245                                 reg = <0x3>;
  246                         };
  247                 };
  248         };
  249 
  250         pci0: pci@e0008000 {
  251                 reg = <0x0 0xe0008000 0x0 0x1000>;
  252                 ranges = <0x2000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000
  253                           0x1000000 0x0 0x00000000 0x0 0xe2000000 0x0 0x800000>;
  254                 clock-frequency = <66666666>;
  255                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  256                 interrupt-map = <
  257                         /* IDSEL 0x12 AD18 */
  258                         0x9000 0x0 0x0 0x1 &mpic 0x5 0x1 0 0
  259                         0x9000 0x0 0x0 0x2 &mpic 0x6 0x1 0 0
  260                         0x9000 0x0 0x0 0x3 &mpic 0x7 0x1 0 0
  261                         0x9000 0x0 0x0 0x4 &mpic 0x4 0x1 0 0
  262 
  263                         /* IDSEL 0x13 AD19 */
  264                         0x9800 0x0 0x0 0x1 &mpic 0x6 0x1 0 0
  265                         0x9800 0x0 0x0 0x2 &mpic 0x7 0x1 0 0
  266                         0x9800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
  267                         0x9800 0x0 0x0 0x4 &mpic 0x5 0x1 0 0>;
  268         };
  269 
  270         /* PCI Express */
  271         pci1: pcie@e000a000 {
  272                 ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x10000000
  273                           0x1000000 0x0 0x00000000 0x0 0xe2800000 0x0 0x800000>;
  274                 reg = <0x0 0xe000a000 0x0 0x1000>;
  275                 pcie@0 {
  276                         ranges = <0x2000000 0x0 0xa0000000
  277                                   0x2000000 0x0 0xa0000000
  278                                   0x0 0x10000000
  279 
  280                                   0x1000000 0x0 0x0
  281                                   0x1000000 0x0 0x0
  282                                   0x0 0x800000>;
  283                 };
  284         };
  285 
  286         rio: rapidio@e00c00000 {
  287                 reg = <0x0 0xe00c0000 0x0 0x20000>;
  288                 port1 {
  289                         ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;
  290                 };
  291         };
  292 
  293         leds {
  294                 compatible = "gpio-leds";
  295 
  296                 green {
  297                         gpios = <&bcsr5 1 0>;
  298                 };
  299 
  300                 amber {
  301                         gpios = <&bcsr5 2 0>;
  302                 };
  303 
  304                 red {
  305                         gpios = <&bcsr5 3 0>;
  306                 };
  307         };
  308 };
  309 
  310 /include/ "mpc8568si-post.dtsi"

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