mpc8572si-post.dtsi

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    1 /*
    2  * MPC8572 Silicon/SoC Device Tree Source (post include)
    3  *
    4  * Copyright 2011 Freescale Semiconductor Inc.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions are met:
    8  *     * Redistributions of source code must retain the above copyright
    9  *       notice, this list of conditions and the following disclaimer.
   10  *     * Redistributions in binary form must reproduce the above copyright
   11  *       notice, this list of conditions and the following disclaimer in the
   12  *       documentation and/or other materials provided with the distribution.
   13  *     * Neither the name of Freescale Semiconductor nor the
   14  *       names of its contributors may be used to endorse or promote products
   15  *       derived from this software without specific prior written permission.
   16  *
   17  *
   18  * ALTERNATIVELY, this software may be distributed under the terms of the
   19  * GNU General Public License ("GPL") as published by the Free Software
   20  * Foundation, either version 2 of that License or (at your option) any
   21  * later version.
   22  *
   23  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
   24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
   25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
   26  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
   27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
   28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
   29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
   30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
   32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   33  */
   34 
   35 &lbc {
   36         #address-cells = <2>;
   37         #size-cells = <1>;
   38         compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
   39         interrupts = <19 2 0 0>;
   40 };
   41 
   42 /* controller at 0x8000 */
   43 &pci0 {
   44         compatible = "fsl,mpc8548-pcie";
   45         device_type = "pci";
   46         #size-cells = <2>;
   47         #address-cells = <3>;
   48         bus-range = <0 255>;
   49         clock-frequency = <33333333>;
   50         interrupts = <24 2 0 0>;
   51 
   52         pcie@0 {
   53                 reg = <0 0 0 0 0>;
   54                 #interrupt-cells = <1>;
   55                 #size-cells = <2>;
   56                 #address-cells = <3>;
   57                 device_type = "pci";
   58                 interrupts = <24 2 0 0>;
   59                 interrupt-map-mask = <0xf800 0 0 7>;
   60 
   61                 interrupt-map = <
   62                         /* IDSEL 0x0 */
   63                         0000 0x0 0x0 0x1 &mpic 0x8 0x1 0x0 0x0
   64                         0000 0x0 0x0 0x2 &mpic 0x9 0x1 0x0 0x0
   65                         0000 0x0 0x0 0x3 &mpic 0xa 0x1 0x0 0x0
   66                         0000 0x0 0x0 0x4 &mpic 0xb 0x1 0x0 0x0
   67                         >;
   68         };
   69 };
   70 
   71 /* controller at 0x9000 */
   72 &pci1 {
   73         compatible = "fsl,mpc8548-pcie";
   74         device_type = "pci";
   75         #size-cells = <2>;
   76         #address-cells = <3>;
   77         bus-range = <0 255>;
   78         clock-frequency = <33333333>;
   79         interrupts = <25 2 0 0>;
   80 
   81         pcie@0 {
   82                 reg = <0 0 0 0 0>;
   83                 #interrupt-cells = <1>;
   84                 #size-cells = <2>;
   85                 #address-cells = <3>;
   86                 device_type = "pci";
   87                 interrupts = <25 2 0 0>;
   88                 interrupt-map-mask = <0xf800 0 0 7>;
   89 
   90                 interrupt-map = <
   91                         /* IDSEL 0x0 */
   92                         0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
   93                         0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
   94                         0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
   95                         0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
   96                         >;
   97         };
   98 };
   99 
  100 /* controller at 0xa000 */
  101 &pci2 {
  102         compatible = "fsl,mpc8548-pcie";
  103         device_type = "pci";
  104         #size-cells = <2>;
  105         #address-cells = <3>;
  106         bus-range = <0 255>;
  107         clock-frequency = <33333333>;
  108         interrupts = <26 2 0 0>;
  109 
  110         pcie@0 {
  111                 reg = <0 0 0 0 0>;
  112                 #interrupt-cells = <1>;
  113                 #size-cells = <2>;
  114                 #address-cells = <3>;
  115                 device_type = "pci";
  116                 interrupts = <26 2 0 0>;
  117                 interrupt-map-mask = <0xf800 0 0 7>;
  118                 interrupt-map = <
  119                         /* IDSEL 0x0 */
  120                         0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
  121                         0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
  122                         0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
  123                         0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
  124                         >;
  125         };
  126 };
  127 
  128 &soc {
  129         #address-cells = <1>;
  130         #size-cells = <1>;
  131         device_type = "soc";
  132         compatible = "fsl,mpc8572-immr", "simple-bus";
  133         bus-frequency = <0>;            // Filled out by uboot.
  134 
  135         ecm-law@0 {
  136                 compatible = "fsl,ecm-law";
  137                 reg = <0x0 0x1000>;
  138                 fsl,num-laws = <12>;
  139         };
  140 
  141         ecm@1000 {
  142                 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
  143                 reg = <0x1000 0x1000>;
  144                 interrupts = <17 2 0 0>;
  145         };
  146 
  147         memory-controller@2000 {
  148                 compatible = "fsl,mpc8572-memory-controller";
  149                 reg = <0x2000 0x1000>;
  150                 interrupts = <18 2 0 0>;
  151         };
  152 
  153         memory-controller@6000 {
  154                 compatible = "fsl,mpc8572-memory-controller";
  155                 reg = <0x6000 0x1000>;
  156                 interrupts = <18 2 0 0>;
  157         };
  158 
  159 /include/ "pq3-i2c-0.dtsi"
  160 /include/ "pq3-i2c-1.dtsi"
  161 /include/ "pq3-duart-0.dtsi"
  162 /include/ "pq3-dma-1.dtsi"
  163 /include/ "pq3-gpio-0.dtsi"
  164         gpio-controller@f000 {
  165                 compatible = "fsl,mpc8572-gpio";
  166         };
  167 
  168         L2: l2-cache-controller@20000 {
  169                 compatible = "fsl,mpc8572-l2-cache-controller";
  170                 reg = <0x20000 0x1000>;
  171                 cache-line-size = <32>; // 32 bytes
  172                 cache-size = <0x100000>; // L2,1M
  173                 interrupts = <16 2 0 0>;
  174         };
  175 
  176 /include/ "pq3-dma-0.dtsi"
  177 /include/ "pq3-etsec1-0.dtsi"
  178 /include/ "pq3-etsec1-timer-0.dtsi"
  179 
  180         ptp_clock@24e00 {
  181                 interrupts = <68 2 0 0 69 2 0 0 70 2 0 0 71 2 0 0>;
  182         };
  183 
  184 /include/ "pq3-etsec1-1.dtsi"
  185 /include/ "pq3-etsec1-2.dtsi"
  186 /include/ "pq3-etsec1-3.dtsi"
  187 /include/ "pq3-sec3.0-0.dtsi"
  188 /include/ "pq3-mpic.dtsi"
  189 /include/ "pq3-mpic-timer-B.dtsi"
  190 
  191         global-utilities@e0000 {
  192                 compatible = "fsl,mpc8572-guts";
  193                 reg = <0xe0000 0x1000>;
  194                 fsl,has-rstcr;
  195         };
  196 };

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/powerpc/fsl/mpc8572si-post.dtsi

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sys/contrib/device-tree/src/powerpc/fsl/mpc8572si-post.dtsi