Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/powerpc/fsl/p5040ds.dts
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1 /* 2 * P5040DS Device Tree Source 3 * 4 * Copyright 2012 - 2015 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * This software is provided by Freescale Semiconductor "as is" and any 24 * express or implied warranties, including, but not limited to, the implied 25 * warranties of merchantability and fitness for a particular purpose are 26 * disclaimed. In no event shall Freescale Semiconductor be liable for any 27 * direct, indirect, incidental, special, exemplary, or consequential damages 28 * (including, but not limited to, procurement of substitute goods or services; 29 * loss of use, data, or profits; or business interruption) however caused and 30 * on any theory of liability, whether in contract, strict liability, or tort 31 * (including negligence or otherwise) arising in any way out of the use of this 32 * software, even if advised of the possibility of such damage. 33 */ 34 35 /include/ "p5040si-pre.dtsi" 36 37 / { 38 model = "fsl,P5040DS"; 39 compatible = "fsl,P5040DS"; 40 #address-cells = <2>; 41 #size-cells = <2>; 42 interrupt-parent = <&mpic>; 43 44 aliases{ 45 phy_sgmii_slot2_1c = &phy_sgmii_slot2_1c; 46 phy_sgmii_slot2_1d = &phy_sgmii_slot2_1d; 47 phy_sgmii_slot2_1e = &phy_sgmii_slot2_1e; 48 phy_sgmii_slot2_1f = &phy_sgmii_slot2_1f; 49 phy_sgmii_slot3_1c = &phy_sgmii_slot3_1c; 50 phy_sgmii_slot3_1d = &phy_sgmii_slot3_1d; 51 phy_sgmii_slot3_1e = &phy_sgmii_slot3_1e; 52 phy_sgmii_slot3_1f = &phy_sgmii_slot3_1f; 53 phy_sgmii_slot5_1c = &phy_sgmii_slot5_1c; 54 phy_sgmii_slot5_1d = &phy_sgmii_slot5_1d; 55 phy_sgmii_slot5_1e = &phy_sgmii_slot5_1e; 56 phy_sgmii_slot5_1f = &phy_sgmii_slot5_1f; 57 phy_sgmii_slot6_1c = &phy_sgmii_slot6_1c; 58 phy_sgmii_slot6_1d = &phy_sgmii_slot6_1d; 59 phy_sgmii_slot6_1e = &phy_sgmii_slot6_1e; 60 phy_sgmii_slot6_1f = &phy_sgmii_slot6_1f; 61 hydra_rg = &hydra_rg; 62 hydra_sg_slot2 = &hydra_sg_slot2; 63 hydra_sg_slot3 = &hydra_sg_slot3; 64 hydra_sg_slot5 = &hydra_sg_slot5; 65 hydra_sg_slot6 = &hydra_sg_slot6; 66 hydra_xg_slot1 = &hydra_xg_slot1; 67 hydra_xg_slot2 = &hydra_xg_slot2; 68 }; 69 70 memory { 71 device_type = "memory"; 72 }; 73 74 reserved-memory { 75 #address-cells = <2>; 76 #size-cells = <2>; 77 ranges; 78 79 bman_fbpr: bman-fbpr { 80 size = <0 0x1000000>; 81 alignment = <0 0x1000000>; 82 }; 83 qman_fqd: qman-fqd { 84 size = <0 0x400000>; 85 alignment = <0 0x400000>; 86 }; 87 qman_pfdr: qman-pfdr { 88 size = <0 0x2000000>; 89 alignment = <0 0x2000000>; 90 }; 91 }; 92 93 dcsr: dcsr@f00000000 { 94 ranges = <0x00000000 0xf 0x00000000 0x01008000>; 95 }; 96 97 bportals: bman-portals@ff4000000 { 98 ranges = <0x0 0xf 0xf4000000 0x200000>; 99 }; 100 101 qportals: qman-portals@ff4200000 { 102 ranges = <0x0 0xf 0xf4200000 0x200000>; 103 }; 104 105 soc: soc@ffe000000 { 106 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; 107 reg = <0xf 0xfe000000 0 0x00001000>; 108 spi@110000 { 109 flash@0 { 110 #address-cells = <1>; 111 #size-cells = <1>; 112 compatible = "spansion,s25sl12801", "jedec,spi-nor"; 113 reg = <0>; 114 spi-max-frequency = <40000000>; /* input clock */ 115 partition@u-boot { 116 label = "u-boot"; 117 reg = <0x00000000 0x00100000>; 118 }; 119 partition@kernel { 120 label = "kernel"; 121 reg = <0x00100000 0x00500000>; 122 }; 123 partition@dtb { 124 label = "dtb"; 125 reg = <0x00600000 0x00100000>; 126 }; 127 partition@fs { 128 label = "file system"; 129 reg = <0x00700000 0x00900000>; 130 }; 131 }; 132 }; 133 134 i2c@118100 { 135 eeprom@51 { 136 compatible = "atmel,24c256"; 137 reg = <0x51>; 138 }; 139 eeprom@52 { 140 compatible = "atmel,24c256"; 141 reg = <0x52>; 142 }; 143 }; 144 145 i2c@119100 { 146 rtc@68 { 147 compatible = "dallas,ds3232"; 148 reg = <0x68>; 149 interrupts = <0x1 0x1 0 0>; 150 }; 151 ina220@40 { 152 compatible = "ti,ina220"; 153 reg = <0x40>; 154 shunt-resistor = <1000>; 155 }; 156 ina220@41 { 157 compatible = "ti,ina220"; 158 reg = <0x41>; 159 shunt-resistor = <1000>; 160 }; 161 ina220@44 { 162 compatible = "ti,ina220"; 163 reg = <0x44>; 164 shunt-resistor = <1000>; 165 }; 166 ina220@45 { 167 compatible = "ti,ina220"; 168 reg = <0x45>; 169 shunt-resistor = <1000>; 170 }; 171 adt7461@4c { 172 compatible = "adi,adt7461"; 173 reg = <0x4c>; 174 }; 175 }; 176 177 fman@400000 { 178 ethernet@e0000 { 179 phy-connection-type = "sgmii"; 180 }; 181 182 ethernet@e2000 { 183 phy-connection-type = "sgmii"; 184 }; 185 186 ethernet@e4000 { 187 phy-connection-type = "sgmii"; 188 }; 189 190 ethernet@e6000 { 191 phy-connection-type = "sgmii"; 192 }; 193 194 ethernet@e8000 { 195 phy-handle = <&phy_rgmii_0>; 196 phy-connection-type = "rgmii"; 197 }; 198 199 ethernet@f0000 { 200 phy-handle = <&phy_xgmii_slot_2>; 201 phy-connection-type = "xgmii"; 202 }; 203 }; 204 205 fman@500000 { 206 ethernet@e0000 { 207 phy-connection-type = "sgmii"; 208 }; 209 210 ethernet@e2000 { 211 phy-connection-type = "sgmii"; 212 }; 213 214 ethernet@e4000 { 215 phy-connection-type = "sgmii"; 216 }; 217 218 ethernet@e6000 { 219 phy-connection-type = "sgmii"; 220 }; 221 222 ethernet@e8000 { 223 phy-handle = <&phy_rgmii_1>; 224 phy-connection-type = "rgmii"; 225 }; 226 227 ethernet@f0000 { 228 phy-handle = <&phy_xgmii_slot_1>; 229 phy-connection-type = "xgmii"; 230 }; 231 }; 232 }; 233 234 lbc: localbus@ffe124000 { 235 reg = <0xf 0xfe124000 0 0x1000>; 236 ranges = <0 0 0xf 0xe8000000 0x08000000 237 2 0 0xf 0xffa00000 0x00040000 238 3 0 0xf 0xffdf0000 0x00008000>; 239 240 flash@0,0 { 241 compatible = "cfi-flash"; 242 reg = <0 0 0x08000000>; 243 bank-width = <2>; 244 device-width = <2>; 245 }; 246 247 nand@2,0 { 248 #address-cells = <1>; 249 #size-cells = <1>; 250 compatible = "fsl,elbc-fcm-nand"; 251 reg = <0x2 0x0 0x40000>; 252 253 partition@0 { 254 label = "NAND U-Boot Image"; 255 reg = <0x0 0x02000000>; 256 }; 257 258 partition@2000000 { 259 label = "NAND Root File System"; 260 reg = <0x02000000 0x10000000>; 261 }; 262 263 partition@12000000 { 264 label = "NAND Compressed RFS Image"; 265 reg = <0x12000000 0x08000000>; 266 }; 267 268 partition@1a000000 { 269 label = "NAND Linux Kernel Image"; 270 reg = <0x1a000000 0x04000000>; 271 }; 272 273 partition@1e000000 { 274 label = "NAND DTB Image"; 275 reg = <0x1e000000 0x01000000>; 276 }; 277 278 partition@1f000000 { 279 label = "NAND Writable User area"; 280 reg = <0x1f000000 0x01000000>; 281 }; 282 }; 283 284 board-control@3,0 { 285 #address-cells = <1>; 286 #size-cells = <1>; 287 compatible = "fsl,p5040ds-fpga", "fsl,fpga-ngpixis"; 288 reg = <3 0 0x40>; 289 ranges = <0 3 0 0x40>; 290 291 mdio-mux-emi1 { 292 #address-cells = <1>; 293 #size-cells = <0>; 294 compatible = "mdio-mux-mmioreg", "mdio-mux"; 295 mdio-parent-bus = <&mdio0>; 296 reg = <9 1>; 297 mux-mask = <0x78>; 298 299 hydra_rg:rgmii-mdio@8 { 300 #address-cells = <1>; 301 #size-cells = <0>; 302 reg = <8>; 303 status = "disabled"; 304 305 phy_rgmii_0: ethernet-phy@0 { 306 reg = <0x0>; 307 }; 308 309 phy_rgmii_1: ethernet-phy@1 { 310 reg = <0x1>; 311 }; 312 }; 313 314 hydra_sg_slot2: sgmii-mdio@28 { 315 #address-cells = <1>; 316 #size-cells = <0>; 317 reg = <0x28>; 318 status = "disabled"; 319 320 phy_sgmii_slot2_1c: ethernet-phy@1c { 321 reg = <0x1c>; 322 }; 323 324 phy_sgmii_slot2_1d: ethernet-phy@1d { 325 reg = <0x1d>; 326 }; 327 328 phy_sgmii_slot2_1e: ethernet-phy@1e { 329 reg = <0x1e>; 330 }; 331 332 phy_sgmii_slot2_1f: ethernet-phy@1f { 333 reg = <0x1f>; 334 }; 335 }; 336 337 hydra_sg_slot3: sgmii-mdio@68 { 338 #address-cells = <1>; 339 #size-cells = <0>; 340 reg = <0x68>; 341 status = "disabled"; 342 343 phy_sgmii_slot3_1c: ethernet-phy@1c { 344 reg = <0x1c>; 345 }; 346 347 phy_sgmii_slot3_1d: ethernet-phy@1d { 348 reg = <0x1d>; 349 }; 350 351 phy_sgmii_slot3_1e: ethernet-phy@1e { 352 reg = <0x1e>; 353 }; 354 355 phy_sgmii_slot3_1f: ethernet-phy@1f { 356 reg = <0x1f>; 357 }; 358 }; 359 360 hydra_sg_slot5: sgmii-mdio@38 { 361 #address-cells = <1>; 362 #size-cells = <0>; 363 reg = <0x38>; 364 status = "disabled"; 365 366 phy_sgmii_slot5_1c: ethernet-phy@1c { 367 reg = <0x1c>; 368 }; 369 370 phy_sgmii_slot5_1d: ethernet-phy@1d { 371 reg = <0x1d>; 372 }; 373 374 phy_sgmii_slot5_1e: ethernet-phy@1e { 375 reg = <0x1e>; 376 }; 377 378 phy_sgmii_slot5_1f: ethernet-phy@1f { 379 reg = <0x1f>; 380 }; 381 }; 382 hydra_sg_slot6: sgmii-mdio@48 { 383 #address-cells = <1>; 384 #size-cells = <0>; 385 reg = <0x48>; 386 status = "disabled"; 387 388 phy_sgmii_slot6_1c: ethernet-phy@1c { 389 reg = <0x1c>; 390 }; 391 392 phy_sgmii_slot6_1d: ethernet-phy@1d { 393 reg = <0x1d>; 394 }; 395 396 phy_sgmii_slot6_1e: ethernet-phy@1e { 397 reg = <0x1e>; 398 }; 399 400 phy_sgmii_slot6_1f: ethernet-phy@1f { 401 reg = <0x1f>; 402 }; 403 }; 404 }; 405 406 mdio-mux-emi2 { 407 #address-cells = <1>; 408 #size-cells = <0>; 409 compatible = "mdio-mux-mmioreg", "mdio-mux"; 410 mdio-parent-bus = <&xmdio0>; 411 reg = <9 1>; 412 mux-mask = <0x06>; 413 414 hydra_xg_slot1: hydra-xg-slot1@0 { 415 #address-cells = <1>; 416 #size-cells = <0>; 417 reg = <0>; 418 status = "disabled"; 419 420 phy_xgmii_slot_1: ethernet-phy@0 { 421 compatible = "ethernet-phy-ieee802.3-c45"; 422 reg = <4>; 423 }; 424 }; 425 426 hydra_xg_slot2: hydra-xg-slot2@2 { 427 #address-cells = <1>; 428 #size-cells = <0>; 429 reg = <2>; 430 431 phy_xgmii_slot_2: ethernet-phy@4 { 432 compatible = "ethernet-phy-ieee802.3-c45"; 433 reg = <0>; 434 }; 435 }; 436 }; 437 }; 438 }; 439 440 pci0: pcie@ffe200000 { 441 reg = <0xf 0xfe200000 0 0x1000>; 442 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 443 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 444 pcie@0 { 445 ranges = <0x02000000 0 0xe0000000 446 0x02000000 0 0xe0000000 447 0 0x20000000 448 449 0x01000000 0 0x00000000 450 0x01000000 0 0x00000000 451 0 0x00010000>; 452 }; 453 }; 454 455 pci1: pcie@ffe201000 { 456 reg = <0xf 0xfe201000 0 0x1000>; 457 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 458 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 459 pcie@0 { 460 ranges = <0x02000000 0 0xe0000000 461 0x02000000 0 0xe0000000 462 0 0x20000000 463 464 0x01000000 0 0x00000000 465 0x01000000 0 0x00000000 466 0 0x00010000>; 467 }; 468 }; 469 470 pci2: pcie@ffe202000 { 471 reg = <0xf 0xfe202000 0 0x1000>; 472 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 473 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 474 pcie@0 { 475 ranges = <0x02000000 0 0xe0000000 476 0x02000000 0 0xe0000000 477 0 0x20000000 478 479 0x01000000 0 0x00000000 480 0x01000000 0 0x00000000 481 0 0x00010000>; 482 }; 483 }; 484 }; 485 486 /include/ "p5040si-post.dtsi"
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