Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/powerpc/fsl/t104xqds.dtsi
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1 /* 2 * T104xQDS Device Tree Source 3 * 4 * Copyright 2013 - 2015 Freescale Semiconductor Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY 24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 / { 36 model = "fsl,T1040QDS"; 37 #address-cells = <2>; 38 #size-cells = <2>; 39 interrupt-parent = <&mpic>; 40 41 aliases { 42 emi1_rgmii0 = &t1040mdio0; 43 emi1_rgmii1 = &t1040mdio1; 44 emi1_slot3 = &t1040mdio3; 45 emi1_slot5 = &t1040mdio5; 46 emi1_slot6 = &t1040mdio6; 47 emi1_slot7 = &t1040mdio7; 48 rgmii_phy1 = &rgmii_phy1; 49 rgmii_phy2 = &rgmii_phy2; 50 phy_s3_01 = &phy_s3_01; 51 phy_s3_02 = &phy_s3_02; 52 phy_s3_03 = &phy_s3_03; 53 phy_s3_04 = &phy_s3_04; 54 phy_s5_01 = &phy_s5_01; 55 phy_s5_02 = &phy_s5_02; 56 phy_s5_03 = &phy_s5_03; 57 phy_s5_04 = &phy_s5_04; 58 phy_s6_01 = &phy_s6_01; 59 phy_s6_02 = &phy_s6_02; 60 phy_s6_03 = &phy_s6_03; 61 phy_s6_04 = &phy_s6_04; 62 phy_s7_01 = &phy_s7_01; 63 phy_s7_02 = &phy_s7_02; 64 phy_s7_03 = &phy_s7_03; 65 phy_s7_04 = &phy_s7_04; 66 }; 67 68 reserved-memory { 69 #address-cells = <2>; 70 #size-cells = <2>; 71 ranges; 72 73 bman_fbpr: bman-fbpr { 74 size = <0 0x1000000>; 75 alignment = <0 0x1000000>; 76 }; 77 qman_fqd: qman-fqd { 78 size = <0 0x400000>; 79 alignment = <0 0x400000>; 80 }; 81 qman_pfdr: qman-pfdr { 82 size = <0 0x2000000>; 83 alignment = <0 0x2000000>; 84 }; 85 }; 86 87 ifc: localbus@ffe124000 { 88 reg = <0xf 0xfe124000 0 0x2000>; 89 ranges = <0 0 0xf 0xe8000000 0x08000000 90 2 0 0xf 0xff800000 0x00010000 91 3 0 0xf 0xffdf0000 0x00008000>; 92 93 nor@0,0 { 94 #address-cells = <1>; 95 #size-cells = <1>; 96 compatible = "cfi-flash"; 97 reg = <0x0 0x0 0x8000000>; 98 99 bank-width = <2>; 100 device-width = <1>; 101 }; 102 103 nand@2,0 { 104 #address-cells = <1>; 105 #size-cells = <1>; 106 compatible = "fsl,ifc-nand"; 107 reg = <0x2 0x0 0x10000>; 108 }; 109 110 board-control@3,0 { 111 #address-cells = <1>; 112 #size-cells = <1>; 113 compatible = "fsl,fpga-qixis"; 114 reg = <3 0 0x300>; 115 ranges = <0 3 0 0x300>; 116 117 mdio-mux-emi1 { 118 #address-cells = <1>; 119 #size-cells = <0>; 120 compatible = "mdio-mux-mmioreg", "mdio-mux"; 121 mdio-parent-bus = <&mdio0>; 122 reg = <0x54 1>; 123 mux-mask = <0xe0>; 124 125 t1040mdio0: mdio@0 { 126 #address-cells = <1>; 127 #size-cells = <0>; 128 reg = <0x00>; 129 status = "disabled"; 130 131 rgmii_phy1: ethernet-phy@1 { 132 reg = <0x1>; 133 }; 134 }; 135 136 t1040mdio1: mdio@20 { 137 #address-cells = <1>; 138 #size-cells = <0>; 139 reg = <0x20>; 140 status = "disabled"; 141 142 rgmii_phy2: ethernet-phy@2 { 143 reg = <0x2>; 144 }; 145 }; 146 147 t1040mdio3: mdio@60 { 148 #address-cells = <1>; 149 #size-cells = <0>; 150 reg = <0x60>; 151 status = "disabled"; 152 153 phy_s3_01: ethernet-phy@1c { 154 reg = <0x1c>; 155 }; 156 157 phy_s3_02: ethernet-phy@1d { 158 reg = <0x1d>; 159 }; 160 161 phy_s3_03: ethernet-phy@1e { 162 reg = <0x1e>; 163 }; 164 165 phy_s3_04: ethernet-phy@1f { 166 reg = <0x1f>; 167 }; 168 }; 169 170 t1040mdio5: mdio@a0 { 171 #address-cells = <1>; 172 #size-cells = <0>; 173 reg = <0xa0>; 174 175 phy_s5_01: ethernet-phy@1c { 176 reg = <0x14>; 177 }; 178 179 phy_s5_02: ethernet-phy@1d { 180 reg = <0x15>; 181 }; 182 183 phy_s5_03: ethernet-phy@1e { 184 reg = <0x16>; 185 }; 186 187 phy_s5_04: ethernet-phy@1f { 188 reg = <0x17>; 189 }; 190 }; 191 192 t1040mdio6: mdio@c0 { 193 #address-cells = <1>; 194 #size-cells = <0>; 195 reg = <0xc0>; 196 197 phy_s6_01: ethernet-phy@1c { 198 reg = <0x18>; 199 }; 200 201 phy_s6_02: ethernet-phy@1d { 202 reg = <0x19>; 203 }; 204 205 phy_s6_03: ethernet-phy@1e { 206 reg = <0x1a>; 207 }; 208 209 phy_s6_04: ethernet-phy@1f { 210 reg = <0x1b>; 211 }; 212 }; 213 214 t1040mdio7: mdio@e0 { 215 #address-cells = <1>; 216 #size-cells = <0>; 217 reg = <0xe0>; 218 status = "disabled"; 219 220 phy_s7_01: ethernet-phy@1c { 221 reg = <0x1c>; 222 }; 223 224 phy_s7_02: ethernet-phy@1d { 225 reg = <0x1d>; 226 }; 227 228 phy_s7_03: ethernet-phy@1e { 229 reg = <0x1e>; 230 }; 231 232 phy_s7_04: ethernet-phy@1f { 233 reg = <0x1f>; 234 }; 235 }; 236 }; 237 }; 238 }; 239 240 memory { 241 device_type = "memory"; 242 }; 243 244 dcsr: dcsr@f00000000 { 245 ranges = <0x00000000 0xf 0x00000000 0x01072000>; 246 }; 247 248 bportals: bman-portals@ff4000000 { 249 ranges = <0x0 0xf 0xf4000000 0x2000000>; 250 }; 251 252 qportals: qman-portals@ff6000000 { 253 ranges = <0x0 0xf 0xf6000000 0x2000000>; 254 }; 255 256 soc: soc@ffe000000 { 257 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; 258 reg = <0xf 0xfe000000 0 0x00001000>; 259 260 spi@110000 { 261 flash@0 { 262 #address-cells = <1>; 263 #size-cells = <1>; 264 compatible = "micron,n25q128a11", "jedec,spi-nor"; 265 reg = <0>; 266 spi-max-frequency = <10000000>; /* input clock */ 267 }; 268 }; 269 270 i2c@118000 { 271 pca9547@77 { 272 compatible = "nxp,pca9547"; 273 reg = <0x77>; 274 }; 275 rtc@68 { 276 compatible = "dallas,ds3232"; 277 reg = <0x68>; 278 interrupts = <0x1 0x1 0 0>; 279 }; 280 }; 281 282 fman@400000 { 283 ethernet@e0000 { 284 fixed-link = <0 1 1000 0 0>; 285 phy-connection-type = "sgmii"; 286 }; 287 288 ethernet@e2000 { 289 fixed-link = <1 1 1000 0 0>; 290 phy-connection-type = "sgmii"; 291 }; 292 293 ethernet@e4000 { 294 phy-handle = <&phy_s7_03>; 295 phy-connection-type = "sgmii"; 296 }; 297 298 ethernet@e6000 { 299 phy-handle = <&rgmii_phy1>; 300 phy-connection-type = "rgmii"; 301 }; 302 303 ethernet@e8000 { 304 phy-handle = <&rgmii_phy2>; 305 phy-connection-type = "rgmii"; 306 }; 307 }; 308 }; 309 310 pci0: pcie@ffe240000 { 311 reg = <0xf 0xfe240000 0 0x10000>; 312 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x10000000 313 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 314 pcie@0 { 315 ranges = <0x02000000 0 0xe0000000 316 0x02000000 0 0xe0000000 317 0 0x10000000 318 319 0x01000000 0 0x00000000 320 0x01000000 0 0x00000000 321 0 0x00010000>; 322 }; 323 }; 324 325 pci1: pcie@ffe250000 { 326 reg = <0xf 0xfe250000 0 0x10000>; 327 ranges = <0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000 328 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 329 pcie@0 { 330 ranges = <0x02000000 0 0xe0000000 331 0x02000000 0 0xe0000000 332 0 0x10000000 333 334 0x01000000 0 0x00000000 335 0x01000000 0 0x00000000 336 0 0x00010000>; 337 }; 338 }; 339 340 pci2: pcie@ffe260000 { 341 reg = <0xf 0xfe260000 0 0x10000>; 342 ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000 343 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 344 pcie@0 { 345 ranges = <0x02000000 0 0xe0000000 346 0x02000000 0 0xe0000000 347 0 0x10000000 348 349 0x01000000 0 0x00000000 350 0x01000000 0 0x00000000 351 0 0x00010000>; 352 }; 353 }; 354 355 pci3: pcie@ffe270000 { 356 reg = <0xf 0xfe270000 0 0x10000>; 357 ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000 358 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; 359 pcie@0 { 360 ranges = <0x02000000 0 0xe0000000 361 0x02000000 0 0xe0000000 362 0 0x10000000 363 364 0x01000000 0 0x00000000 365 0x01000000 0 0x00000000 366 0 0x00010000>; 367 }; 368 }; 369 370 qe: qe@ffe140000 { 371 ranges = <0x0 0xf 0xfe140000 0x40000>; 372 reg = <0xf 0xfe140000 0 0x480>; 373 brg-frequency = <0>; 374 bus-frequency = <0>; 375 376 si1: si@700 { 377 compatible = "fsl,t1040-qe-si"; 378 reg = <0x700 0x80>; 379 }; 380 381 siram1: siram@1000 { 382 compatible = "fsl,t1040-qe-siram"; 383 reg = <0x1000 0x800>; 384 }; 385 386 ucc_hdlc: ucc@2000 { 387 compatible = "fsl,ucc-hdlc"; 388 rx-clock-name = "clk8"; 389 tx-clock-name = "clk9"; 390 fsl,rx-sync-clock = "rsync_pin"; 391 fsl,tx-sync-clock = "tsync_pin"; 392 fsl,tx-timeslot-mask = <0xfffffffe>; 393 fsl,rx-timeslot-mask = <0xfffffffe>; 394 fsl,tdm-framer-type = "e1"; 395 fsl,tdm-id = <0>; 396 fsl,siram-entry-id = <0>; 397 fsl,tdm-interface; 398 }; 399 400 ucc_serial: ucc@2200 { 401 compatible = "fsl,t1040-ucc-uart"; 402 port-number = <0>; 403 rx-clock-name = "brg2"; 404 tx-clock-name = "brg2"; 405 }; 406 }; 407 };
Cache object: e1fbd902a3562214a03807867320cfb0
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