Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/powerpc/taishan.dts
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /* 2 * Device Tree Source for IBM/AMCC Taishan 3 * 4 * Copyright 2007 IBM Corp. 5 * Hugh Blemings <hugh@au.ibm.com> based off code by 6 * Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without 10 * any warranty of any kind, whether express or implied. 11 */ 12 13 /dts-v1/; 14 15 / { 16 #address-cells = <2>; 17 #size-cells = <1>; 18 model = "amcc,taishan"; 19 compatible = "amcc,taishan"; 20 dcr-parent = <&{/cpus/cpu@0}>; 21 22 aliases { 23 ethernet0 = &EMAC2; 24 ethernet1 = &EMAC3; 25 serial0 = &UART0; 26 serial1 = &UART1; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu@0 { 34 device_type = "cpu"; 35 model = "PowerPC,440GX"; 36 reg = <0x00000000>; 37 clock-frequency = <800000000>; // 800MHz 38 timebase-frequency = <0>; // Filled in by zImage 39 i-cache-line-size = <50>; 40 d-cache-line-size = <50>; 41 i-cache-size = <32768>; /* 32 kB */ 42 d-cache-size = <32768>; /* 32 kB */ 43 dcr-controller; 44 dcr-access-method = "native"; 45 }; 46 }; 47 48 memory { 49 device_type = "memory"; 50 reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage 51 }; 52 53 54 UICB0: interrupt-controller-base { 55 compatible = "ibm,uic-440gx", "ibm,uic"; 56 interrupt-controller; 57 cell-index = <3>; 58 dcr-reg = <0x200 0x009>; 59 #address-cells = <0>; 60 #size-cells = <0>; 61 #interrupt-cells = <2>; 62 }; 63 64 65 UIC0: interrupt-controller0 { 66 compatible = "ibm,uic-440gx", "ibm,uic"; 67 interrupt-controller; 68 cell-index = <0>; 69 dcr-reg = <0x0c0 0x009>; 70 #address-cells = <0>; 71 #size-cells = <0>; 72 #interrupt-cells = <2>; 73 interrupts = <0x1 0x4 0x0 0x4>; /* cascade - first non-critical */ 74 interrupt-parent = <&UICB0>; 75 76 }; 77 78 UIC1: interrupt-controller1 { 79 compatible = "ibm,uic-440gx", "ibm,uic"; 80 interrupt-controller; 81 cell-index = <1>; 82 dcr-reg = <0x0d0 0x009>; 83 #address-cells = <0>; 84 #size-cells = <0>; 85 #interrupt-cells = <2>; 86 interrupts = <0x3 0x4 0x2 0x4>; /* cascade */ 87 interrupt-parent = <&UICB0>; 88 }; 89 90 UIC2: interrupt-controller2 { 91 compatible = "ibm,uic-440gx", "ibm,uic"; 92 interrupt-controller; 93 cell-index = <2>; /* was 1 */ 94 dcr-reg = <0x210 0x009>; 95 #address-cells = <0>; 96 #size-cells = <0>; 97 #interrupt-cells = <2>; 98 interrupts = <0x5 0x4 0x4 0x4>; /* cascade */ 99 interrupt-parent = <&UICB0>; 100 }; 101 102 103 CPC0: cpc { 104 compatible = "ibm,cpc-440gp"; 105 dcr-reg = <0x0b0 0x003 0x0e0 0x010>; 106 // FIXME: anything else? 107 }; 108 109 L2C0: l2c { 110 compatible = "ibm,l2-cache-440gx", "ibm,l2-cache"; 111 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */ 112 0x030 0x008>; /* L2 cache DCR's */ 113 cache-line-size = <32>; /* 32 bytes */ 114 cache-size = <262144>; /* L2, 256K */ 115 interrupt-parent = <&UIC2>; 116 interrupts = <0x17 0x1>; 117 }; 118 119 plb { 120 compatible = "ibm,plb-440gx", "ibm,plb4"; 121 #address-cells = <2>; 122 #size-cells = <1>; 123 ranges; 124 clock-frequency = <160000000>; // 160MHz 125 126 SDRAM0: memory-controller { 127 compatible = "ibm,sdram-440gp"; 128 dcr-reg = <0x010 0x002>; 129 // FIXME: anything else? 130 }; 131 132 SRAM0: sram { 133 compatible = "ibm,sram-440gp"; 134 dcr-reg = <0x020 0x008 0x00a 0x001>; 135 }; 136 137 DMA0: dma { 138 // FIXME: ??? 139 compatible = "ibm,dma-440gp"; 140 dcr-reg = <0x100 0x027>; 141 }; 142 143 MAL0: mcmal { 144 compatible = "ibm,mcmal-440gx", "ibm,mcmal2"; 145 dcr-reg = <0x180 0x062>; 146 num-tx-chans = <4>; 147 num-rx-chans = <4>; 148 interrupt-parent = <&MAL0>; 149 interrupts = <0x0 0x1 0x2 0x3 0x4>; 150 #interrupt-cells = <1>; 151 #address-cells = <0>; 152 #size-cells = <0>; 153 interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4 154 /*RXEOB*/ 0x1 &UIC0 0xb 0x4 155 /*SERR*/ 0x2 &UIC1 0x0 0x4 156 /*TXDE*/ 0x3 &UIC1 0x1 0x4 157 /*RXDE*/ 0x4 &UIC1 0x2 0x4>; 158 interrupt-map-mask = <0xffffffff>; 159 }; 160 161 POB0: opb { 162 compatible = "ibm,opb-440gx", "ibm,opb"; 163 #address-cells = <1>; 164 #size-cells = <1>; 165 /* Wish there was a nicer way of specifying a full 32-bit 166 range */ 167 ranges = <0x00000000 0x00000001 0x00000000 0x80000000 168 0x80000000 0x00000001 0x80000000 0x80000000>; 169 dcr-reg = <0x090 0x00b>; 170 interrupt-parent = <&UIC1>; 171 interrupts = <0x7 0x4>; 172 clock-frequency = <80000000>; // 80MHz 173 174 175 EBC0: ebc { 176 compatible = "ibm,ebc-440gx", "ibm,ebc"; 177 dcr-reg = <0x012 0x002>; 178 #address-cells = <2>; 179 #size-cells = <1>; 180 clock-frequency = <80000000>; // 80MHz 181 182 /* ranges property is supplied by zImage 183 * based on firmware's configuration of the 184 * EBC bridge */ 185 186 interrupts = <0x5 0x4>; 187 interrupt-parent = <&UIC1>; 188 189 nor_flash@0,0 { 190 compatible = "cfi-flash"; 191 bank-width = <4>; 192 device-width = <2>; 193 reg = <0x0 0x0 0x4000000>; 194 #address-cells = <1>; 195 #size-cells = <1>; 196 partition@0 { 197 label = "kernel"; 198 reg = <0x0 0x180000>; 199 }; 200 partition@180000 { 201 label = "root"; 202 reg = <0x180000 0x200000>; 203 }; 204 partition@380000 { 205 label = "user"; 206 reg = <0x380000 0x3bc0000>; 207 }; 208 partition@3f40000 { 209 label = "env"; 210 reg = <0x3f40000 0x80000>; 211 }; 212 partition@3fc0000 { 213 label = "u-boot"; 214 reg = <0x3fc0000 0x40000>; 215 }; 216 }; 217 }; 218 219 220 221 UART0: serial@40000200 { 222 device_type = "serial"; 223 compatible = "ns16550"; 224 reg = <0x40000200 0x00000008>; 225 virtual-reg = <0xe0000200>; 226 clock-frequency = <11059200>; 227 current-speed = <115200>; /* 115200 */ 228 interrupt-parent = <&UIC0>; 229 interrupts = <0x0 0x4>; 230 }; 231 232 UART1: serial@40000300 { 233 device_type = "serial"; 234 compatible = "ns16550"; 235 reg = <0x40000300 0x00000008>; 236 virtual-reg = <0xe0000300>; 237 clock-frequency = <11059200>; 238 current-speed = <115200>; /* 115200 */ 239 interrupt-parent = <&UIC0>; 240 interrupts = <0x1 0x4>; 241 }; 242 243 IIC0: i2c@40000400 { 244 /* FIXME */ 245 compatible = "ibm,iic-440gp", "ibm,iic"; 246 reg = <0x40000400 0x00000014>; 247 interrupt-parent = <&UIC0>; 248 interrupts = <0x2 0x4>; 249 }; 250 IIC1: i2c@40000500 { 251 /* FIXME */ 252 compatible = "ibm,iic-440gp", "ibm,iic"; 253 reg = <0x40000500 0x00000014>; 254 interrupt-parent = <&UIC0>; 255 interrupts = <0x3 0x4>; 256 }; 257 258 GPIO0: gpio@40000700 { 259 /* FIXME */ 260 compatible = "ibm,gpio-440gp"; 261 reg = <0x40000700 0x00000020>; 262 }; 263 264 ZMII0: emac-zmii@40000780 { 265 compatible = "ibm,zmii-440gx", "ibm,zmii"; 266 reg = <0x40000780 0x0000000c>; 267 }; 268 269 RGMII0: emac-rgmii@40000790 { 270 compatible = "ibm,rgmii"; 271 reg = <0x40000790 0x00000008>; 272 }; 273 274 TAH0: emac-tah@40000b50 { 275 compatible = "ibm,tah-440gx", "ibm,tah"; 276 reg = <0x40000b50 0x00000030>; 277 }; 278 279 TAH1: emac-tah@40000d50 { 280 compatible = "ibm,tah-440gx", "ibm,tah"; 281 reg = <0x40000d50 0x00000030>; 282 }; 283 284 EMAC0: ethernet@40000800 { 285 unused = <0x1>; 286 device_type = "network"; 287 compatible = "ibm,emac-440gx", "ibm,emac4"; 288 interrupt-parent = <&UIC1>; 289 interrupts = <0x1c 0x4 0x1d 0x4>; 290 reg = <0x40000800 0x00000074>; 291 local-mac-address = [000000000000]; // Filled in by zImage 292 mal-device = <&MAL0>; 293 mal-tx-channel = <0>; 294 mal-rx-channel = <0>; 295 cell-index = <0>; 296 max-frame-size = <1500>; 297 rx-fifo-size = <4096>; 298 tx-fifo-size = <2048>; 299 phy-mode = "rmii"; 300 phy-map = <0x00000001>; 301 zmii-device = <&ZMII0>; 302 zmii-channel = <0>; 303 }; 304 EMAC1: ethernet@40000900 { 305 unused = <0x1>; 306 device_type = "network"; 307 compatible = "ibm,emac-440gx", "ibm,emac4"; 308 interrupt-parent = <&UIC1>; 309 interrupts = <0x1e 0x4 0x1f 0x4>; 310 reg = <0x40000900 0x00000074>; 311 local-mac-address = [000000000000]; // Filled in by zImage 312 mal-device = <&MAL0>; 313 mal-tx-channel = <1>; 314 mal-rx-channel = <1>; 315 cell-index = <1>; 316 max-frame-size = <1500>; 317 rx-fifo-size = <4096>; 318 tx-fifo-size = <2048>; 319 phy-mode = "rmii"; 320 phy-map = <0x00000001>; 321 zmii-device = <&ZMII0>; 322 zmii-channel = <1>; 323 }; 324 325 EMAC2: ethernet@40000c00 { 326 device_type = "network"; 327 compatible = "ibm,emac-440gx", "ibm,emac4"; 328 interrupt-parent = <&UIC2>; 329 interrupts = <0x0 0x4 0x1 0x4>; 330 reg = <0x40000c00 0x00000074>; 331 local-mac-address = [000000000000]; // Filled in by zImage 332 mal-device = <&MAL0>; 333 mal-tx-channel = <2>; 334 mal-rx-channel = <2>; 335 cell-index = <2>; 336 max-frame-size = <9000>; 337 rx-fifo-size = <4096>; 338 tx-fifo-size = <2048>; 339 phy-mode = "rgmii"; 340 phy-address = <1>; 341 rgmii-device = <&RGMII0>; 342 rgmii-channel = <0>; 343 zmii-device = <&ZMII0>; 344 zmii-channel = <2>; 345 tah-device = <&TAH0>; 346 tah-channel = <0>; 347 }; 348 349 EMAC3: ethernet@40000e00 { 350 device_type = "network"; 351 compatible = "ibm,emac-440gx", "ibm,emac4"; 352 interrupt-parent = <&UIC2>; 353 interrupts = <0x2 0x4 0x3 0x4>; 354 reg = <0x40000e00 0x00000074>; 355 local-mac-address = [000000000000]; // Filled in by zImage 356 mal-device = <&MAL0>; 357 mal-tx-channel = <3>; 358 mal-rx-channel = <3>; 359 cell-index = <3>; 360 max-frame-size = <9000>; 361 rx-fifo-size = <4096>; 362 tx-fifo-size = <2048>; 363 phy-mode = "rgmii"; 364 phy-address = <3>; 365 rgmii-device = <&RGMII0>; 366 rgmii-channel = <1>; 367 zmii-device = <&ZMII0>; 368 zmii-channel = <3>; 369 tah-device = <&TAH1>; 370 tah-channel = <0>; 371 }; 372 373 374 GPT0: gpt@40000a00 { 375 /* FIXME */ 376 reg = <0x40000a00 0x000000d4>; 377 interrupt-parent = <&UIC0>; 378 interrupts = <0x12 0x4 0x13 0x4 0x14 0x4 0x15 0x4 0x16 0x4>; 379 }; 380 381 }; 382 383 PCIX0: pci@20ec00000 { 384 device_type = "pci"; 385 #interrupt-cells = <1>; 386 #size-cells = <2>; 387 #address-cells = <3>; 388 compatible = "ibm,plb440gp-pcix", "ibm,plb-pcix"; 389 primary; 390 large-inbound-windows; 391 enable-msi-hole; 392 reg = <0x00000002 0x0ec00000 0x00000008 /* Config space access */ 393 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ 394 0x00000002 0x0ed00000 0x00000004 /* Special cycles */ 395 0x00000002 0x0ec80000 0x00000100 /* Internal registers */ 396 0x00000002 0x0ec80100 0x000000fc>; /* Internal messaging registers */ 397 398 /* Outbound ranges, one memory and one IO, 399 * later cannot be changed 400 */ 401 ranges = <0x02000000 0x00000000 0x80000000 0x00000003 0x80000000 0x00000000 0x80000000 402 0x01000000 0x00000000 0x00000000 0x00000002 0x08000000 0x00000000 0x00010000>; 403 404 /* Inbound 2GB range starting at 0 */ 405 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; 406 407 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 408 interrupt-map = < 409 /* IDSEL 1 */ 410 0x800 0x0 0x0 0x1 &UIC0 0x17 0x8 411 0x800 0x0 0x0 0x2 &UIC0 0x18 0x8 412 0x800 0x0 0x0 0x3 &UIC0 0x19 0x8 413 0x800 0x0 0x0 0x4 &UIC0 0x1a 0x8 414 415 /* IDSEL 2 */ 416 0x1000 0x0 0x0 0x1 &UIC0 0x18 0x8 417 0x1000 0x0 0x0 0x2 &UIC0 0x19 0x8 418 0x1000 0x0 0x0 0x3 &UIC0 0x1a 0x8 419 0x1000 0x0 0x0 0x4 &UIC0 0x17 0x8 420 >; 421 }; 422 }; 423 424 chosen { 425 stdout-path = "/plb/opb/serial@40000300"; 426 }; 427 };
Cache object: fcc95ba4ff124a2aad5d9e82fd9f8e97
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]