Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/powerpc/xcalibur1501.dts
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1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2008 Extreme Engineering Solutions, Inc. 4 * Based on MPC8572DS device tree from Freescale Semiconductor, Inc. 5 * 6 * XCalibur1501 6U CompactPCI single-board computer based on MPC8572E 7 */ 8 9 /dts-v1/; 10 / { 11 model = "xes,xcalibur1501"; 12 compatible = "xes,xcalibur1501", "xes,MPC8572"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 aliases { 17 ethernet0 = &enet0; 18 ethernet1 = &enet1; 19 ethernet2 = &enet2; 20 ethernet3 = &enet3; 21 serial0 = &serial0; 22 serial1 = &serial1; 23 pci2 = &pci2; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 PowerPC,8572@0 { 31 device_type = "cpu"; 32 reg = <0x0>; 33 d-cache-line-size = <32>; // 32 bytes 34 i-cache-line-size = <32>; // 32 bytes 35 d-cache-size = <0x8000>; // L1, 32K 36 i-cache-size = <0x8000>; // L1, 32K 37 timebase-frequency = <0>; 38 bus-frequency = <0>; 39 clock-frequency = <0>; 40 next-level-cache = <&L2>; 41 }; 42 43 PowerPC,8572@1 { 44 device_type = "cpu"; 45 reg = <0x1>; 46 d-cache-line-size = <32>; // 32 bytes 47 i-cache-line-size = <32>; // 32 bytes 48 d-cache-size = <0x8000>; // L1, 32K 49 i-cache-size = <0x8000>; // L1, 32K 50 timebase-frequency = <0>; 51 bus-frequency = <0>; 52 clock-frequency = <0>; 53 next-level-cache = <&L2>; 54 }; 55 }; 56 57 memory { 58 device_type = "memory"; 59 reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot 60 }; 61 62 localbus@ef005000 { 63 #address-cells = <2>; 64 #size-cells = <1>; 65 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus"; 66 reg = <0 0xef005000 0 0x1000>; 67 interrupts = <19 2>; 68 interrupt-parent = <&mpic>; 69 /* Local bus region mappings */ 70 ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Flash 1 */ 71 1 0 0 0xf0000000 0x8000000 /* CS1: Flash 2 */ 72 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */ 73 3 0 0 0xef840000 0x40000 /* CS3: NAND CE2 */ 74 4 0 0 0xe9000000 0x100000>; /* CS4: USB */ 75 76 nor-boot@0,0 { 77 compatible = "amd,s29gl01gp", "cfi-flash"; 78 bank-width = <2>; 79 reg = <0 0 0x8000000>; /* 128MB */ 80 #address-cells = <1>; 81 #size-cells = <1>; 82 partition@0 { 83 label = "Primary user space"; 84 reg = <0x00000000 0x6f00000>; /* 111 MB */ 85 }; 86 partition@6f00000 { 87 label = "Primary kernel"; 88 reg = <0x6f00000 0x1000000>; /* 16 MB */ 89 }; 90 partition@7f00000 { 91 label = "Primary DTB"; 92 reg = <0x7f00000 0x40000>; /* 256 KB */ 93 }; 94 partition@7f40000 { 95 label = "Primary U-Boot environment"; 96 reg = <0x7f40000 0x40000>; /* 256 KB */ 97 }; 98 partition@7f80000 { 99 label = "Primary U-Boot"; 100 reg = <0x7f80000 0x80000>; /* 512 KB */ 101 read-only; 102 }; 103 }; 104 105 nor-alternate@1,0 { 106 compatible = "amd,s29gl01gp", "cfi-flash"; 107 bank-width = <2>; 108 //reg = <0xf0000000 0x08000000>; /* 128MB */ 109 reg = <1 0 0x8000000>; /* 128MB */ 110 #address-cells = <1>; 111 #size-cells = <1>; 112 partition@0 { 113 label = "Secondary user space"; 114 reg = <0x00000000 0x6f00000>; /* 111 MB */ 115 }; 116 partition@6f00000 { 117 label = "Secondary kernel"; 118 reg = <0x6f00000 0x1000000>; /* 16 MB */ 119 }; 120 partition@7f00000 { 121 label = "Secondary DTB"; 122 reg = <0x7f00000 0x40000>; /* 256 KB */ 123 }; 124 partition@7f40000 { 125 label = "Secondary U-Boot environment"; 126 reg = <0x7f40000 0x40000>; /* 256 KB */ 127 }; 128 partition@7f80000 { 129 label = "Secondary U-Boot"; 130 reg = <0x7f80000 0x80000>; /* 512 KB */ 131 read-only; 132 }; 133 }; 134 135 nand@2,0 { 136 #address-cells = <1>; 137 #size-cells = <1>; 138 /* 139 * Actual part could be ST Micro NAND08GW3B2A (1 GB), 140 * Micron MT29F8G08DAA (2x 512 MB), or Micron 141 * MT29F16G08FAA (2x 1 GB), depending on the build 142 * configuration 143 */ 144 compatible = "fsl,mpc8572-fcm-nand", 145 "fsl,elbc-fcm-nand"; 146 reg = <2 0 0x40000>; 147 /* U-Boot should fix this up if chip size > 1 GB */ 148 partition@0 { 149 label = "NAND Filesystem"; 150 reg = <0 0x40000000>; 151 }; 152 }; 153 154 usb@4,0 { 155 compatible = "nxp,usb-isp1761"; 156 reg = <4 0 0x100000>; 157 bus-width = <32>; 158 interrupt-parent = <&mpic>; 159 interrupts = <10 1>; 160 }; 161 }; 162 163 soc8572@ef000000 { 164 #address-cells = <1>; 165 #size-cells = <1>; 166 device_type = "soc"; 167 compatible = "fsl,mpc8572-immr", "simple-bus"; 168 ranges = <0x0 0 0xef000000 0x100000>; 169 bus-frequency = <0>; // Filled out by uboot. 170 171 ecm-law@0 { 172 compatible = "fsl,ecm-law"; 173 reg = <0x0 0x1000>; 174 fsl,num-laws = <12>; 175 }; 176 177 ecm@1000 { 178 compatible = "fsl,mpc8572-ecm", "fsl,ecm"; 179 reg = <0x1000 0x1000>; 180 interrupts = <17 2>; 181 interrupt-parent = <&mpic>; 182 }; 183 184 memory-controller@2000 { 185 compatible = "fsl,mpc8572-memory-controller"; 186 reg = <0x2000 0x1000>; 187 interrupt-parent = <&mpic>; 188 interrupts = <18 2>; 189 }; 190 191 memory-controller@6000 { 192 compatible = "fsl,mpc8572-memory-controller"; 193 reg = <0x6000 0x1000>; 194 interrupt-parent = <&mpic>; 195 interrupts = <18 2>; 196 }; 197 198 L2: l2-cache-controller@20000 { 199 compatible = "fsl,mpc8572-l2-cache-controller"; 200 reg = <0x20000 0x1000>; 201 cache-line-size = <32>; // 32 bytes 202 cache-size = <0x100000>; // L2, 1M 203 interrupt-parent = <&mpic>; 204 interrupts = <16 2>; 205 }; 206 207 i2c@3000 { 208 #address-cells = <1>; 209 #size-cells = <0>; 210 cell-index = <0>; 211 compatible = "fsl-i2c"; 212 reg = <0x3000 0x100>; 213 interrupts = <43 2>; 214 interrupt-parent = <&mpic>; 215 dfsrr; 216 217 temp-sensor@48 { 218 compatible = "dallas,ds1631", "dallas,ds1621"; 219 reg = <0x48>; 220 }; 221 222 temp-sensor@4c { 223 compatible = "adi,adt7461"; 224 reg = <0x4c>; 225 }; 226 227 cpu-supervisor@51 { 228 compatible = "dallas,ds4510"; 229 reg = <0x51>; 230 }; 231 232 eeprom@54 { 233 compatible = "atmel,at24c128b"; 234 reg = <0x54>; 235 }; 236 237 rtc@68 { 238 compatible = "st,m41t00", 239 "dallas,ds1338"; 240 reg = <0x68>; 241 }; 242 243 pcie-switch@6a { 244 compatible = "plx,pex8648"; 245 reg = <0x6a>; 246 }; 247 248 /* On-board signals for VID, flash, serial */ 249 gpio1: gpio@18 { 250 compatible = "nxp,pca9557"; 251 reg = <0x18>; 252 #gpio-cells = <2>; 253 gpio-controller; 254 polarity = <0x00>; 255 }; 256 257 /* PMC0/XMC0 signals */ 258 gpio2: gpio@1c { 259 compatible = "nxp,pca9557"; 260 reg = <0x1c>; 261 #gpio-cells = <2>; 262 gpio-controller; 263 polarity = <0x00>; 264 }; 265 266 /* PMC1/XMC1 signals */ 267 gpio3: gpio@1d { 268 compatible = "nxp,pca9557"; 269 reg = <0x1d>; 270 #gpio-cells = <2>; 271 gpio-controller; 272 polarity = <0x00>; 273 }; 274 275 /* CompactPCI signals (sysen, GA[4:0]) */ 276 gpio4: gpio@1e { 277 compatible = "nxp,pca9557"; 278 reg = <0x1e>; 279 #gpio-cells = <2>; 280 gpio-controller; 281 polarity = <0x00>; 282 }; 283 284 /* CompactPCI J5 GPIO and FAL/DEG/PRST */ 285 gpio5: gpio@1f { 286 compatible = "nxp,pca9557"; 287 reg = <0x1f>; 288 #gpio-cells = <2>; 289 gpio-controller; 290 polarity = <0x00>; 291 }; 292 }; 293 294 i2c@3100 { 295 #address-cells = <1>; 296 #size-cells = <0>; 297 cell-index = <1>; 298 compatible = "fsl-i2c"; 299 reg = <0x3100 0x100>; 300 interrupts = <43 2>; 301 interrupt-parent = <&mpic>; 302 dfsrr; 303 }; 304 305 dma@c300 { 306 #address-cells = <1>; 307 #size-cells = <1>; 308 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; 309 reg = <0xc300 0x4>; 310 ranges = <0x0 0xc100 0x200>; 311 cell-index = <1>; 312 dma-channel@0 { 313 compatible = "fsl,mpc8572-dma-channel", 314 "fsl,eloplus-dma-channel"; 315 reg = <0x0 0x80>; 316 cell-index = <0>; 317 interrupt-parent = <&mpic>; 318 interrupts = <76 2>; 319 }; 320 dma-channel@80 { 321 compatible = "fsl,mpc8572-dma-channel", 322 "fsl,eloplus-dma-channel"; 323 reg = <0x80 0x80>; 324 cell-index = <1>; 325 interrupt-parent = <&mpic>; 326 interrupts = <77 2>; 327 }; 328 dma-channel@100 { 329 compatible = "fsl,mpc8572-dma-channel", 330 "fsl,eloplus-dma-channel"; 331 reg = <0x100 0x80>; 332 cell-index = <2>; 333 interrupt-parent = <&mpic>; 334 interrupts = <78 2>; 335 }; 336 dma-channel@180 { 337 compatible = "fsl,mpc8572-dma-channel", 338 "fsl,eloplus-dma-channel"; 339 reg = <0x180 0x80>; 340 cell-index = <3>; 341 interrupt-parent = <&mpic>; 342 interrupts = <79 2>; 343 }; 344 }; 345 346 dma@21300 { 347 #address-cells = <1>; 348 #size-cells = <1>; 349 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; 350 reg = <0x21300 0x4>; 351 ranges = <0x0 0x21100 0x200>; 352 cell-index = <0>; 353 dma-channel@0 { 354 compatible = "fsl,mpc8572-dma-channel", 355 "fsl,eloplus-dma-channel"; 356 reg = <0x0 0x80>; 357 cell-index = <0>; 358 interrupt-parent = <&mpic>; 359 interrupts = <20 2>; 360 }; 361 dma-channel@80 { 362 compatible = "fsl,mpc8572-dma-channel", 363 "fsl,eloplus-dma-channel"; 364 reg = <0x80 0x80>; 365 cell-index = <1>; 366 interrupt-parent = <&mpic>; 367 interrupts = <21 2>; 368 }; 369 dma-channel@100 { 370 compatible = "fsl,mpc8572-dma-channel", 371 "fsl,eloplus-dma-channel"; 372 reg = <0x100 0x80>; 373 cell-index = <2>; 374 interrupt-parent = <&mpic>; 375 interrupts = <22 2>; 376 }; 377 dma-channel@180 { 378 compatible = "fsl,mpc8572-dma-channel", 379 "fsl,eloplus-dma-channel"; 380 reg = <0x180 0x80>; 381 cell-index = <3>; 382 interrupt-parent = <&mpic>; 383 interrupts = <23 2>; 384 }; 385 }; 386 387 /* eTSEC 1 front panel 0 */ 388 enet0: ethernet@24000 { 389 #address-cells = <1>; 390 #size-cells = <1>; 391 cell-index = <0>; 392 device_type = "network"; 393 model = "eTSEC"; 394 compatible = "gianfar"; 395 reg = <0x24000 0x1000>; 396 ranges = <0x0 0x24000 0x1000>; 397 local-mac-address = [ 00 00 00 00 00 00 ]; 398 interrupts = <29 2 30 2 34 2>; 399 interrupt-parent = <&mpic>; 400 tbi-handle = <&tbi0>; 401 phy-handle = <&phy0>; 402 phy-connection-type = "sgmii"; 403 404 mdio@520 { 405 #address-cells = <1>; 406 #size-cells = <0>; 407 compatible = "fsl,gianfar-mdio"; 408 reg = <0x520 0x20>; 409 410 phy0: ethernet-phy@1 { 411 interrupt-parent = <&mpic>; 412 interrupts = <4 1>; 413 reg = <0x1>; 414 }; 415 phy1: ethernet-phy@2 { 416 interrupt-parent = <&mpic>; 417 interrupts = <4 1>; 418 reg = <0x2>; 419 }; 420 phy2: ethernet-phy@3 { 421 interrupt-parent = <&mpic>; 422 interrupts = <5 1>; 423 reg = <0x3>; 424 }; 425 phy3: ethernet-phy@4 { 426 interrupt-parent = <&mpic>; 427 interrupts = <5 1>; 428 reg = <0x4>; 429 }; 430 tbi0: tbi-phy@11 { 431 reg = <0x11>; 432 device_type = "tbi-phy"; 433 }; 434 }; 435 }; 436 437 /* eTSEC 2 front panel 1 */ 438 enet1: ethernet@25000 { 439 #address-cells = <1>; 440 #size-cells = <1>; 441 cell-index = <1>; 442 device_type = "network"; 443 model = "eTSEC"; 444 compatible = "gianfar"; 445 reg = <0x25000 0x1000>; 446 ranges = <0x0 0x25000 0x1000>; 447 local-mac-address = [ 00 00 00 00 00 00 ]; 448 interrupts = <35 2 36 2 40 2>; 449 interrupt-parent = <&mpic>; 450 tbi-handle = <&tbi1>; 451 phy-handle = <&phy1>; 452 phy-connection-type = "sgmii"; 453 454 mdio@520 { 455 #address-cells = <1>; 456 #size-cells = <0>; 457 compatible = "fsl,gianfar-tbi"; 458 reg = <0x520 0x20>; 459 460 tbi1: tbi-phy@11 { 461 reg = <0x11>; 462 device_type = "tbi-phy"; 463 }; 464 }; 465 }; 466 467 /* eTSEC 3 PICMG2.16 backplane port 0 */ 468 enet2: ethernet@26000 { 469 #address-cells = <1>; 470 #size-cells = <1>; 471 cell-index = <2>; 472 device_type = "network"; 473 model = "eTSEC"; 474 compatible = "gianfar"; 475 reg = <0x26000 0x1000>; 476 ranges = <0x0 0x26000 0x1000>; 477 local-mac-address = [ 00 00 00 00 00 00 ]; 478 interrupts = <31 2 32 2 33 2>; 479 interrupt-parent = <&mpic>; 480 tbi-handle = <&tbi2>; 481 phy-handle = <&phy2>; 482 phy-connection-type = "sgmii"; 483 484 mdio@520 { 485 #address-cells = <1>; 486 #size-cells = <0>; 487 compatible = "fsl,gianfar-tbi"; 488 reg = <0x520 0x20>; 489 490 tbi2: tbi-phy@11 { 491 reg = <0x11>; 492 device_type = "tbi-phy"; 493 }; 494 }; 495 }; 496 497 /* eTSEC 4 PICMG2.16 backplane port 1 */ 498 enet3: ethernet@27000 { 499 #address-cells = <1>; 500 #size-cells = <1>; 501 cell-index = <3>; 502 device_type = "network"; 503 model = "eTSEC"; 504 compatible = "gianfar"; 505 reg = <0x27000 0x1000>; 506 ranges = <0x0 0x27000 0x1000>; 507 local-mac-address = [ 00 00 00 00 00 00 ]; 508 interrupts = <37 2 38 2 39 2>; 509 interrupt-parent = <&mpic>; 510 tbi-handle = <&tbi3>; 511 phy-handle = <&phy3>; 512 phy-connection-type = "sgmii"; 513 514 mdio@520 { 515 #address-cells = <1>; 516 #size-cells = <0>; 517 compatible = "fsl,gianfar-tbi"; 518 reg = <0x520 0x20>; 519 520 tbi3: tbi-phy@11 { 521 reg = <0x11>; 522 device_type = "tbi-phy"; 523 }; 524 }; 525 }; 526 527 /* UART0 */ 528 serial0: serial@4500 { 529 cell-index = <0>; 530 device_type = "serial"; 531 compatible = "fsl,ns16550", "ns16550"; 532 reg = <0x4500 0x100>; 533 clock-frequency = <0>; 534 interrupts = <42 2>; 535 interrupt-parent = <&mpic>; 536 }; 537 538 /* UART1 */ 539 serial1: serial@4600 { 540 cell-index = <1>; 541 device_type = "serial"; 542 compatible = "fsl,ns16550", "ns16550"; 543 reg = <0x4600 0x100>; 544 clock-frequency = <0>; 545 interrupts = <42 2>; 546 interrupt-parent = <&mpic>; 547 }; 548 549 global-utilities@e0000 { //global utilities block 550 compatible = "fsl,mpc8572-guts"; 551 reg = <0xe0000 0x1000>; 552 fsl,has-rstcr; 553 }; 554 555 msi@41600 { 556 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi"; 557 reg = <0x41600 0x80>; 558 msi-available-ranges = <0 0x100>; 559 interrupts = < 560 0xe0 0 561 0xe1 0 562 0xe2 0 563 0xe3 0 564 0xe4 0 565 0xe5 0 566 0xe6 0 567 0xe7 0>; 568 interrupt-parent = <&mpic>; 569 }; 570 571 crypto@30000 { 572 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", 573 "fsl,sec2.1", "fsl,sec2.0"; 574 reg = <0x30000 0x10000>; 575 interrupts = <45 2 58 2>; 576 interrupt-parent = <&mpic>; 577 fsl,num-channels = <4>; 578 fsl,channel-fifo-len = <24>; 579 fsl,exec-units-mask = <0x9fe>; 580 fsl,descriptor-types-mask = <0x3ab0ebf>; 581 }; 582 583 mpic: pic@40000 { 584 interrupt-controller; 585 #address-cells = <0>; 586 #interrupt-cells = <2>; 587 reg = <0x40000 0x40000>; 588 compatible = "chrp,open-pic"; 589 device_type = "open-pic"; 590 }; 591 592 gpio0: gpio@f000 { 593 compatible = "fsl,mpc8572-gpio"; 594 reg = <0xf000 0x1000>; 595 interrupts = <47 2>; 596 interrupt-parent = <&mpic>; 597 #gpio-cells = <2>; 598 gpio-controller; 599 }; 600 601 gpio-leds { 602 compatible = "gpio-leds"; 603 604 heartbeat { 605 label = "Heartbeat"; 606 gpios = <&gpio0 4 1>; 607 linux,default-trigger = "heartbeat"; 608 }; 609 610 yellow { 611 label = "Yellow"; 612 gpios = <&gpio0 5 1>; 613 }; 614 615 red { 616 label = "Red"; 617 gpios = <&gpio0 6 1>; 618 }; 619 620 green { 621 label = "Green"; 622 gpios = <&gpio0 7 1>; 623 }; 624 }; 625 626 /* PME (pattern-matcher) */ 627 pme@10000 { 628 compatible = "fsl,mpc8572-pme", "pme8572"; 629 reg = <0x10000 0x5000>; 630 interrupts = <57 2 64 2 65 2 66 2 67 2>; 631 interrupt-parent = <&mpic>; 632 }; 633 634 tlu@2f000 { 635 compatible = "fsl,mpc8572-tlu", "fsl_tlu"; 636 reg = <0x2f000 0x1000>; 637 interrupts = <61 2>; 638 interrupt-parent = <&mpic>; 639 }; 640 641 tlu@15000 { 642 compatible = "fsl,mpc8572-tlu", "fsl_tlu"; 643 reg = <0x15000 0x1000>; 644 interrupts = <75 2>; 645 interrupt-parent = <&mpic>; 646 }; 647 }; 648 649 /* 650 * PCI Express controller 3 @ ef008000 is not used. 651 * This would have been pci0 on other mpc85xx platforms. 652 * 653 * PCI Express controller 2 @ ef009000 is not used. 654 * This would have been pci1 on other mpc85xx platforms. 655 */ 656 657 /* PCI Express controller 1, wired to PEX8648 PCIe switch */ 658 pci2: pcie@ef00a000 { 659 compatible = "fsl,mpc8548-pcie"; 660 device_type = "pci"; 661 #interrupt-cells = <1>; 662 #size-cells = <2>; 663 #address-cells = <3>; 664 reg = <0 0xef00a000 0 0x1000>; 665 bus-range = <0 255>; 666 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000 667 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>; 668 clock-frequency = <33333333>; 669 interrupt-parent = <&mpic>; 670 interrupts = <26 2>; 671 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 672 interrupt-map = < 673 /* IDSEL 0x0 */ 674 0x0 0x0 0x0 0x1 &mpic 0x0 0x1 675 0x0 0x0 0x0 0x2 &mpic 0x1 0x1 676 0x0 0x0 0x0 0x3 &mpic 0x2 0x1 677 0x0 0x0 0x0 0x4 &mpic 0x3 0x1 678 >; 679 pcie@0 { 680 reg = <0x0 0x0 0x0 0x0 0x0>; 681 #size-cells = <2>; 682 #address-cells = <3>; 683 device_type = "pci"; 684 ranges = <0x2000000 0x0 0x80000000 685 0x2000000 0x0 0x80000000 686 0x0 0x40000000 687 688 0x1000000 0x0 0x0 689 0x1000000 0x0 0x0 690 0x0 0x100000>; 691 }; 692 }; 693 };
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