Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/powerpc/xpedite5370.dts
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1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2008 Extreme Engineering Solutions, Inc. 4 * Based on MPC8572DS device tree from Freescale Semiconductor, Inc. 5 * 6 * XPedite5370 3U VPX single-board computer based on MPC8572E 7 */ 8 9 /dts-v1/; 10 / { 11 model = "xes,xpedite5370"; 12 compatible = "xes,xpedite5370", "xes,MPC8572"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 aliases { 17 ethernet0 = &enet0; 18 ethernet1 = &enet1; 19 serial0 = &serial0; 20 serial1 = &serial1; 21 pci1 = &pci1; 22 pci2 = &pci2; 23 }; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 PowerPC,8572@0 { 30 device_type = "cpu"; 31 reg = <0x0>; 32 d-cache-line-size = <32>; // 32 bytes 33 i-cache-line-size = <32>; // 32 bytes 34 d-cache-size = <0x8000>; // L1, 32K 35 i-cache-size = <0x8000>; // L1, 32K 36 timebase-frequency = <0>; 37 bus-frequency = <0>; 38 clock-frequency = <0>; 39 next-level-cache = <&L2>; 40 }; 41 42 PowerPC,8572@1 { 43 device_type = "cpu"; 44 reg = <0x1>; 45 d-cache-line-size = <32>; // 32 bytes 46 i-cache-line-size = <32>; // 32 bytes 47 d-cache-size = <0x8000>; // L1, 32K 48 i-cache-size = <0x8000>; // L1, 32K 49 timebase-frequency = <0>; 50 bus-frequency = <0>; 51 clock-frequency = <0>; 52 next-level-cache = <&L2>; 53 }; 54 }; 55 56 memory { 57 device_type = "memory"; 58 reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot 59 }; 60 61 localbus@ef005000 { 62 #address-cells = <2>; 63 #size-cells = <1>; 64 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus"; 65 reg = <0 0xef005000 0 0x1000>; 66 interrupts = <19 2>; 67 interrupt-parent = <&mpic>; 68 /* Local bus region mappings */ 69 ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */ 70 1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */ 71 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */ 72 3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */ 73 74 nor-boot@0,0 { 75 compatible = "amd,s29gl01gp", "cfi-flash"; 76 bank-width = <2>; 77 reg = <0 0 0x8000000>; /* 128MB */ 78 #address-cells = <1>; 79 #size-cells = <1>; 80 partition@0 { 81 label = "Primary user space"; 82 reg = <0x00000000 0x6f00000>; /* 111 MB */ 83 }; 84 partition@6f00000 { 85 label = "Primary kernel"; 86 reg = <0x6f00000 0x1000000>; /* 16 MB */ 87 }; 88 partition@7f00000 { 89 label = "Primary DTB"; 90 reg = <0x7f00000 0x40000>; /* 256 KB */ 91 }; 92 partition@7f40000 { 93 label = "Primary U-Boot environment"; 94 reg = <0x7f40000 0x40000>; /* 256 KB */ 95 }; 96 partition@7f80000 { 97 label = "Primary U-Boot"; 98 reg = <0x7f80000 0x80000>; /* 512 KB */ 99 read-only; 100 }; 101 }; 102 103 nor-alternate@1,0 { 104 compatible = "amd,s29gl01gp", "cfi-flash"; 105 bank-width = <2>; 106 //reg = <0xf0000000 0x08000000>; /* 128MB */ 107 reg = <1 0 0x8000000>; /* 128MB */ 108 #address-cells = <1>; 109 #size-cells = <1>; 110 partition@0 { 111 label = "Secondary user space"; 112 reg = <0x00000000 0x6f00000>; /* 111 MB */ 113 }; 114 partition@6f00000 { 115 label = "Secondary kernel"; 116 reg = <0x6f00000 0x1000000>; /* 16 MB */ 117 }; 118 partition@7f00000 { 119 label = "Secondary DTB"; 120 reg = <0x7f00000 0x40000>; /* 256 KB */ 121 }; 122 partition@7f40000 { 123 label = "Secondary U-Boot environment"; 124 reg = <0x7f40000 0x40000>; /* 256 KB */ 125 }; 126 partition@7f80000 { 127 label = "Secondary U-Boot"; 128 reg = <0x7f80000 0x80000>; /* 512 KB */ 129 read-only; 130 }; 131 }; 132 133 nand@2,0 { 134 #address-cells = <1>; 135 #size-cells = <1>; 136 /* 137 * Actual part could be ST Micro NAND08GW3B2A (1 GB), 138 * Micron MT29F8G08DAA (2x 512 MB), or Micron 139 * MT29F16G08FAA (2x 1 GB), depending on the build 140 * configuration 141 */ 142 compatible = "fsl,mpc8572-fcm-nand", 143 "fsl,elbc-fcm-nand"; 144 reg = <2 0 0x40000>; 145 /* U-Boot should fix this up if chip size > 1 GB */ 146 partition@0 { 147 label = "NAND Filesystem"; 148 reg = <0 0x40000000>; 149 }; 150 }; 151 152 }; 153 154 soc8572@ef000000 { 155 #address-cells = <1>; 156 #size-cells = <1>; 157 device_type = "soc"; 158 compatible = "fsl,mpc8572-immr", "simple-bus"; 159 ranges = <0x0 0 0xef000000 0x100000>; 160 bus-frequency = <0>; // Filled out by uboot. 161 162 ecm-law@0 { 163 compatible = "fsl,ecm-law"; 164 reg = <0x0 0x1000>; 165 fsl,num-laws = <12>; 166 }; 167 168 ecm@1000 { 169 compatible = "fsl,mpc8572-ecm", "fsl,ecm"; 170 reg = <0x1000 0x1000>; 171 interrupts = <17 2>; 172 interrupt-parent = <&mpic>; 173 }; 174 175 memory-controller@2000 { 176 compatible = "fsl,mpc8572-memory-controller"; 177 reg = <0x2000 0x1000>; 178 interrupt-parent = <&mpic>; 179 interrupts = <18 2>; 180 }; 181 182 memory-controller@6000 { 183 compatible = "fsl,mpc8572-memory-controller"; 184 reg = <0x6000 0x1000>; 185 interrupt-parent = <&mpic>; 186 interrupts = <18 2>; 187 }; 188 189 L2: l2-cache-controller@20000 { 190 compatible = "fsl,mpc8572-l2-cache-controller"; 191 reg = <0x20000 0x1000>; 192 cache-line-size = <32>; // 32 bytes 193 cache-size = <0x100000>; // L2, 1M 194 interrupt-parent = <&mpic>; 195 interrupts = <16 2>; 196 }; 197 198 i2c@3000 { 199 #address-cells = <1>; 200 #size-cells = <0>; 201 cell-index = <0>; 202 compatible = "fsl-i2c"; 203 reg = <0x3000 0x100>; 204 interrupts = <43 2>; 205 interrupt-parent = <&mpic>; 206 dfsrr; 207 208 temp-sensor@48 { 209 compatible = "dallas,ds1631", "dallas,ds1621"; 210 reg = <0x48>; 211 }; 212 213 temp-sensor@4c { 214 compatible = "adi,adt7461"; 215 reg = <0x4c>; 216 }; 217 218 cpu-supervisor@51 { 219 compatible = "dallas,ds4510"; 220 reg = <0x51>; 221 }; 222 223 eeprom@54 { 224 compatible = "atmel,at24c128b"; 225 reg = <0x54>; 226 }; 227 228 rtc@68 { 229 compatible = "st,m41t00", 230 "dallas,ds1338"; 231 reg = <0x68>; 232 }; 233 234 pcie-switch@70 { 235 compatible = "plx,pex8518"; 236 reg = <0x70>; 237 }; 238 239 gpio1: gpio@18 { 240 compatible = "nxp,pca9557"; 241 reg = <0x18>; 242 #gpio-cells = <2>; 243 gpio-controller; 244 polarity = <0x00>; 245 }; 246 247 gpio2: gpio@1c { 248 compatible = "nxp,pca9557"; 249 reg = <0x1c>; 250 #gpio-cells = <2>; 251 gpio-controller; 252 polarity = <0x00>; 253 }; 254 255 gpio3: gpio@1e { 256 compatible = "nxp,pca9557"; 257 reg = <0x1e>; 258 #gpio-cells = <2>; 259 gpio-controller; 260 polarity = <0x00>; 261 }; 262 263 gpio4: gpio@1f { 264 compatible = "nxp,pca9557"; 265 reg = <0x1f>; 266 #gpio-cells = <2>; 267 gpio-controller; 268 polarity = <0x00>; 269 }; 270 }; 271 272 i2c@3100 { 273 #address-cells = <1>; 274 #size-cells = <0>; 275 cell-index = <1>; 276 compatible = "fsl-i2c"; 277 reg = <0x3100 0x100>; 278 interrupts = <43 2>; 279 interrupt-parent = <&mpic>; 280 dfsrr; 281 }; 282 283 dma@c300 { 284 #address-cells = <1>; 285 #size-cells = <1>; 286 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; 287 reg = <0xc300 0x4>; 288 ranges = <0x0 0xc100 0x200>; 289 cell-index = <1>; 290 dma-channel@0 { 291 compatible = "fsl,mpc8572-dma-channel", 292 "fsl,eloplus-dma-channel"; 293 reg = <0x0 0x80>; 294 cell-index = <0>; 295 interrupt-parent = <&mpic>; 296 interrupts = <76 2>; 297 }; 298 dma-channel@80 { 299 compatible = "fsl,mpc8572-dma-channel", 300 "fsl,eloplus-dma-channel"; 301 reg = <0x80 0x80>; 302 cell-index = <1>; 303 interrupt-parent = <&mpic>; 304 interrupts = <77 2>; 305 }; 306 dma-channel@100 { 307 compatible = "fsl,mpc8572-dma-channel", 308 "fsl,eloplus-dma-channel"; 309 reg = <0x100 0x80>; 310 cell-index = <2>; 311 interrupt-parent = <&mpic>; 312 interrupts = <78 2>; 313 }; 314 dma-channel@180 { 315 compatible = "fsl,mpc8572-dma-channel", 316 "fsl,eloplus-dma-channel"; 317 reg = <0x180 0x80>; 318 cell-index = <3>; 319 interrupt-parent = <&mpic>; 320 interrupts = <79 2>; 321 }; 322 }; 323 324 dma@21300 { 325 #address-cells = <1>; 326 #size-cells = <1>; 327 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma"; 328 reg = <0x21300 0x4>; 329 ranges = <0x0 0x21100 0x200>; 330 cell-index = <0>; 331 dma-channel@0 { 332 compatible = "fsl,mpc8572-dma-channel", 333 "fsl,eloplus-dma-channel"; 334 reg = <0x0 0x80>; 335 cell-index = <0>; 336 interrupt-parent = <&mpic>; 337 interrupts = <20 2>; 338 }; 339 dma-channel@80 { 340 compatible = "fsl,mpc8572-dma-channel", 341 "fsl,eloplus-dma-channel"; 342 reg = <0x80 0x80>; 343 cell-index = <1>; 344 interrupt-parent = <&mpic>; 345 interrupts = <21 2>; 346 }; 347 dma-channel@100 { 348 compatible = "fsl,mpc8572-dma-channel", 349 "fsl,eloplus-dma-channel"; 350 reg = <0x100 0x80>; 351 cell-index = <2>; 352 interrupt-parent = <&mpic>; 353 interrupts = <22 2>; 354 }; 355 dma-channel@180 { 356 compatible = "fsl,mpc8572-dma-channel", 357 "fsl,eloplus-dma-channel"; 358 reg = <0x180 0x80>; 359 cell-index = <3>; 360 interrupt-parent = <&mpic>; 361 interrupts = <23 2>; 362 }; 363 }; 364 365 /* eTSEC 1 */ 366 enet0: ethernet@24000 { 367 #address-cells = <1>; 368 #size-cells = <1>; 369 cell-index = <0>; 370 device_type = "network"; 371 model = "eTSEC"; 372 compatible = "gianfar"; 373 reg = <0x24000 0x1000>; 374 ranges = <0x0 0x24000 0x1000>; 375 local-mac-address = [ 00 00 00 00 00 00 ]; 376 interrupts = <29 2 30 2 34 2>; 377 interrupt-parent = <&mpic>; 378 tbi-handle = <&tbi0>; 379 phy-handle = <&phy0>; 380 phy-connection-type = "sgmii"; 381 382 mdio@520 { 383 #address-cells = <1>; 384 #size-cells = <0>; 385 compatible = "fsl,gianfar-mdio"; 386 reg = <0x520 0x20>; 387 388 phy0: ethernet-phy@1 { 389 interrupt-parent = <&mpic>; 390 interrupts = <8 1>; 391 reg = <0x1>; 392 }; 393 phy1: ethernet-phy@2 { 394 interrupt-parent = <&mpic>; 395 interrupts = <8 1>; 396 reg = <0x2>; 397 }; 398 tbi0: tbi-phy@11 { 399 reg = <0x11>; 400 device_type = "tbi-phy"; 401 }; 402 }; 403 }; 404 405 /* eTSEC 2 */ 406 enet1: ethernet@25000 { 407 #address-cells = <1>; 408 #size-cells = <1>; 409 cell-index = <1>; 410 device_type = "network"; 411 model = "eTSEC"; 412 compatible = "gianfar"; 413 reg = <0x25000 0x1000>; 414 ranges = <0x0 0x25000 0x1000>; 415 local-mac-address = [ 00 00 00 00 00 00 ]; 416 interrupts = <35 2 36 2 40 2>; 417 interrupt-parent = <&mpic>; 418 tbi-handle = <&tbi1>; 419 phy-handle = <&phy1>; 420 phy-connection-type = "sgmii"; 421 422 mdio@520 { 423 #address-cells = <1>; 424 #size-cells = <0>; 425 compatible = "fsl,gianfar-tbi"; 426 reg = <0x520 0x20>; 427 428 tbi1: tbi-phy@11 { 429 reg = <0x11>; 430 device_type = "tbi-phy"; 431 }; 432 }; 433 }; 434 435 /* UART0 */ 436 serial0: serial@4500 { 437 cell-index = <0>; 438 device_type = "serial"; 439 compatible = "fsl,ns16550", "ns16550"; 440 reg = <0x4500 0x100>; 441 clock-frequency = <0>; 442 interrupts = <42 2>; 443 interrupt-parent = <&mpic>; 444 }; 445 446 /* UART1 */ 447 serial1: serial@4600 { 448 cell-index = <1>; 449 device_type = "serial"; 450 compatible = "fsl,ns16550", "ns16550"; 451 reg = <0x4600 0x100>; 452 clock-frequency = <0>; 453 interrupts = <42 2>; 454 interrupt-parent = <&mpic>; 455 }; 456 457 global-utilities@e0000 { //global utilities block 458 compatible = "fsl,mpc8572-guts"; 459 reg = <0xe0000 0x1000>; 460 fsl,has-rstcr; 461 }; 462 463 msi@41600 { 464 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi"; 465 reg = <0x41600 0x80>; 466 msi-available-ranges = <0 0x100>; 467 interrupts = < 468 0xe0 0 469 0xe1 0 470 0xe2 0 471 0xe3 0 472 0xe4 0 473 0xe5 0 474 0xe6 0 475 0xe7 0>; 476 interrupt-parent = <&mpic>; 477 }; 478 479 crypto@30000 { 480 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2", 481 "fsl,sec2.1", "fsl,sec2.0"; 482 reg = <0x30000 0x10000>; 483 interrupts = <45 2 58 2>; 484 interrupt-parent = <&mpic>; 485 fsl,num-channels = <4>; 486 fsl,channel-fifo-len = <24>; 487 fsl,exec-units-mask = <0x9fe>; 488 fsl,descriptor-types-mask = <0x3ab0ebf>; 489 }; 490 491 mpic: pic@40000 { 492 interrupt-controller; 493 #address-cells = <0>; 494 #interrupt-cells = <2>; 495 reg = <0x40000 0x40000>; 496 compatible = "chrp,open-pic"; 497 device_type = "open-pic"; 498 }; 499 500 gpio0: gpio@f000 { 501 compatible = "fsl,mpc8572-gpio"; 502 reg = <0xf000 0x1000>; 503 interrupts = <47 2>; 504 interrupt-parent = <&mpic>; 505 #gpio-cells = <2>; 506 gpio-controller; 507 }; 508 509 gpio-leds { 510 compatible = "gpio-leds"; 511 512 heartbeat { 513 label = "Heartbeat"; 514 gpios = <&gpio0 4 1>; 515 linux,default-trigger = "heartbeat"; 516 }; 517 518 yellow { 519 label = "Yellow"; 520 gpios = <&gpio0 5 1>; 521 }; 522 523 red { 524 label = "Red"; 525 gpios = <&gpio0 6 1>; 526 }; 527 528 green { 529 label = "Green"; 530 gpios = <&gpio0 7 1>; 531 }; 532 }; 533 534 /* PME (pattern-matcher) */ 535 pme@10000 { 536 compatible = "fsl,mpc8572-pme", "pme8572"; 537 reg = <0x10000 0x5000>; 538 interrupts = <57 2 64 2 65 2 66 2 67 2>; 539 interrupt-parent = <&mpic>; 540 }; 541 542 tlu@2f000 { 543 compatible = "fsl,mpc8572-tlu", "fsl_tlu"; 544 reg = <0x2f000 0x1000>; 545 interrupts = <61 2>; 546 interrupt-parent = <&mpic>; 547 }; 548 549 tlu@15000 { 550 compatible = "fsl,mpc8572-tlu", "fsl_tlu"; 551 reg = <0x15000 0x1000>; 552 interrupts = <75 2>; 553 interrupt-parent = <&mpic>; 554 }; 555 }; 556 557 /* 558 * PCI Express controller 3 @ ef008000 is not used. 559 * This would have been pci0 on other mpc85xx platforms. 560 */ 561 562 /* PCI Express controller 2, wired to VPX P1,P2 backplane */ 563 pci1: pcie@ef009000 { 564 compatible = "fsl,mpc8548-pcie"; 565 device_type = "pci"; 566 #interrupt-cells = <1>; 567 #size-cells = <2>; 568 #address-cells = <3>; 569 reg = <0 0xef009000 0 0x1000>; 570 bus-range = <0 255>; 571 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000 572 0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x00010000>; 573 clock-frequency = <33333333>; 574 interrupt-parent = <&mpic>; 575 interrupts = <25 2>; 576 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 577 interrupt-map = < 578 /* IDSEL 0x0 */ 579 0x0 0x0 0x0 0x1 &mpic 0x4 0x1 580 0x0 0x0 0x0 0x2 &mpic 0x5 0x1 581 0x0 0x0 0x0 0x3 &mpic 0x6 0x1 582 0x0 0x0 0x0 0x4 &mpic 0x7 0x1 583 >; 584 pcie@0 { 585 reg = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>; 586 #size-cells = <2>; 587 #address-cells = <3>; 588 device_type = "pci"; 589 ranges = <0x2000000 0x0 0xc0000000 590 0x2000000 0x0 0xc0000000 591 0x0 0x10000000 592 593 0x1000000 0x0 0x0 594 0x1000000 0x0 0x0 595 0x0 0x100000>; 596 }; 597 }; 598 599 /* PCI Express controller 1, wired to PEX8518 PCIe switch */ 600 pci2: pcie@ef00a000 { 601 compatible = "fsl,mpc8548-pcie"; 602 device_type = "pci"; 603 #interrupt-cells = <1>; 604 #size-cells = <2>; 605 #address-cells = <3>; 606 reg = <0 0xef00a000 0 0x1000>; 607 bus-range = <0 255>; 608 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000 609 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>; 610 clock-frequency = <33333333>; 611 interrupt-parent = <&mpic>; 612 interrupts = <26 2>; 613 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 614 interrupt-map = < 615 /* IDSEL 0x0 */ 616 0x0 0x0 0x0 0x1 &mpic 0x0 0x1 617 0x0 0x0 0x0 0x2 &mpic 0x1 0x1 618 0x0 0x0 0x0 0x3 &mpic 0x2 0x1 619 0x0 0x0 0x0 0x4 &mpic 0x3 0x1 620 >; 621 pcie@0 { 622 reg = <0x0 0x0 0x0 0x0 0x0>; 623 #size-cells = <2>; 624 #address-cells = <3>; 625 device_type = "pci"; 626 ranges = <0x2000000 0x0 0x80000000 627 0x2000000 0x0 0x80000000 628 0x0 0x40000000 629 630 0x1000000 0x0 0x0 631 0x1000000 0x0 0x0 632 0x0 0x100000>; 633 }; 634 }; 635 };
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