| 
     1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
    2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
    3 
    4 / {
    5         core_pwm0: pwm@41000000 {
    6                 compatible = "microchip,corepwm-rtl-v4";
    7                 reg = <0x0 0x41000000 0x0 0xF0>;
    8                 microchip,sync-update-mask = /bits/ 32 <0>;
    9                 #pwm-cells = <2>;
   10                 clocks = <&fabric_clk3>;
   11                 status = "disabled";
   12         };
   13 
   14         i2c2: i2c@44000000 {
   15                 compatible = "microchip,corei2c-rtl-v7";
   16                 reg = <0x0 0x44000000 0x0 0x1000>;
   17                 #address-cells = <1>;
   18                 #size-cells = <0>;
   19                 clocks = <&fabric_clk3>;
   20                 interrupt-parent = <&plic>;
   21                 interrupts = <122>;
   22                 clock-frequency = <100000>;
   23                 status = "disabled";
   24         };
   25 
   26         fabric_clk3: fabric-clk3 {
   27                 compatible = "fixed-clock";
   28                 #clock-cells = <0>;
   29                 clock-frequency = <62500000>;
   30         };
   31 
   32         fabric_clk1: fabric-clk1 {
   33                 compatible = "fixed-clock";
   34                 #clock-cells = <0>;
   35                 clock-frequency = <125000000>;
   36         };
   37 };
Cache object: 86b15b64384b4380663cb260f379c384 
 
 |