1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
3
4 /dts-v1/;
5
6 #include "microchip-mpfs.dtsi"
7
8 /* Clock frequency (in Hz) of the rtcclk */
9 #define RTCCLK_FREQ 1000000
10
11 / {
12 model = "Microchip PolarFire-SoC Icicle Kit";
13 compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
14
15 aliases {
16 ethernet0 = &mac1;
17 serial0 = &mmuart0;
18 serial1 = &mmuart1;
19 serial2 = &mmuart2;
20 serial3 = &mmuart3;
21 serial4 = &mmuart4;
22 };
23
24 chosen {
25 stdout-path = "serial1:115200n8";
26 };
27
28 cpus {
29 timebase-frequency = <RTCCLK_FREQ>;
30 };
31
32 ddrc_cache_lo: memory@80000000 {
33 device_type = "memory";
34 reg = <0x0 0x80000000 0x0 0x2e000000>;
35 clocks = <&clkcfg CLK_DDRC>;
36 status = "okay";
37 };
38
39 ddrc_cache_hi: memory@1000000000 {
40 device_type = "memory";
41 reg = <0x10 0x0 0x0 0x40000000>;
42 clocks = <&clkcfg CLK_DDRC>;
43 status = "okay";
44 };
45 };
46
47 &refclk {
48 clock-frequency = <125000000>;
49 };
50
51 &mmuart1 {
52 status = "okay";
53 };
54
55 &mmuart2 {
56 status = "okay";
57 };
58
59 &mmuart3 {
60 status = "okay";
61 };
62
63 &mmuart4 {
64 status = "okay";
65 };
66
67 &mmc {
68 status = "okay";
69
70 bus-width = <4>;
71 disable-wp;
72 cap-sd-highspeed;
73 cap-mmc-highspeed;
74 card-detect-delay = <200>;
75 mmc-ddr-1_8v;
76 mmc-hs200-1_8v;
77 sd-uhs-sdr12;
78 sd-uhs-sdr25;
79 sd-uhs-sdr50;
80 sd-uhs-sdr104;
81 };
82
83 &spi0 {
84 status = "okay";
85 };
86
87 &spi1 {
88 status = "okay";
89 };
90
91 &qspi {
92 status = "okay";
93 };
94
95 &i2c0 {
96 status = "okay";
97 };
98
99 &i2c1 {
100 status = "okay";
101 };
102
103 &i2c2 {
104 status = "okay";
105 };
106
107 &mac0 {
108 phy-mode = "sgmii";
109 phy-handle = <&phy0>;
110 };
111
112 &mac1 {
113 status = "okay";
114 phy-mode = "sgmii";
115 phy-handle = <&phy1>;
116 phy1: ethernet-phy@9 {
117 reg = <9>;
118 ti,fifo-depth = <0x1>;
119 };
120 phy0: ethernet-phy@8 {
121 reg = <8>;
122 ti,fifo-depth = <0x1>;
123 };
124 };
125
126 &gpio2 {
127 interrupts = <53>, <53>, <53>, <53>,
128 <53>, <53>, <53>, <53>,
129 <53>, <53>, <53>, <53>,
130 <53>, <53>, <53>, <53>,
131 <53>, <53>, <53>, <53>,
132 <53>, <53>, <53>, <53>,
133 <53>, <53>, <53>, <53>,
134 <53>, <53>, <53>, <53>;
135 status = "okay";
136 };
137
138 &rtc {
139 status = "okay";
140 };
141
142 &usb {
143 status = "okay";
144 dr_mode = "host";
145 };
146
147 &mbox {
148 status = "okay";
149 };
150
151 &syscontroller {
152 status = "okay";
153 };
154
155 &pcie {
156 status = "okay";
157 };
158
159 &core_pwm0 {
160 status = "okay";
161 };
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