| 
     1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
    2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
    3 
    4 / {
    5         compatible = "microchip,mpfs-icicle-reference-rtlv2203", "microchip,mpfs";
    6 
    7         core_pwm0: pwm@41000000 {
    8                 compatible = "microchip,corepwm-rtl-v4";
    9                 reg = <0x0 0x41000000 0x0 0xF0>;
   10                 microchip,sync-update-mask = /bits/ 32 <0>;
   11                 #pwm-cells = <2>;
   12                 clocks = <&fabric_clk3>;
   13                 status = "disabled";
   14         };
   15 
   16         i2c2: i2c@44000000 {
   17                 compatible = "microchip,corei2c-rtl-v7";
   18                 reg = <0x0 0x44000000 0x0 0x1000>;
   19                 #address-cells = <1>;
   20                 #size-cells = <0>;
   21                 clocks = <&fabric_clk3>;
   22                 interrupt-parent = <&plic>;
   23                 interrupts = <122>;
   24                 clock-frequency = <100000>;
   25                 status = "disabled";
   26         };
   27 
   28         fabric_clk3: fabric-clk3 {
   29                 compatible = "fixed-clock";
   30                 #clock-cells = <0>;
   31                 clock-frequency = <62500000>;
   32         };
   33 
   34         fabric_clk1: fabric-clk1 {
   35                 compatible = "fixed-clock";
   36                 #clock-cells = <0>;
   37                 clock-frequency = <125000000>;
   38         };
   39 };
Cache object: f4a1ba5d176504ea74d94a6563311771 
 
 |