mpfs-icicle-kit.dts

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    1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
    2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
    3 
    4 /dts-v1/;
    5 
    6 #include "mpfs.dtsi"
    7 #include "mpfs-icicle-kit-fabric.dtsi"
    8 
    9 /* Clock frequency (in Hz) of the rtcclk */
   10 #define RTCCLK_FREQ             1000000
   11 
   12 / {
   13         model = "Microchip PolarFire-SoC Icicle Kit";
   14         compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
   15 
   16         aliases {
   17                 ethernet0 = &mac1;
   18                 serial0 = &mmuart0;
   19                 serial1 = &mmuart1;
   20                 serial2 = &mmuart2;
   21                 serial3 = &mmuart3;
   22                 serial4 = &mmuart4;
   23         };
   24 
   25         chosen {
   26                 stdout-path = "serial1:115200n8";
   27         };
   28 
   29         cpus {
   30                 timebase-frequency = <RTCCLK_FREQ>;
   31         };
   32 
   33         ddrc_cache_lo: memory@80000000 {
   34                 device_type = "memory";
   35                 reg = <0x0 0x80000000 0x0 0x2e000000>;
   36                 status = "okay";
   37         };
   38 
   39         ddrc_cache_hi: memory@1000000000 {
   40                 device_type = "memory";
   41                 reg = <0x10 0x0 0x0 0x40000000>;
   42                 status = "okay";
   43         };
   44 };
   45 
   46 &core_pwm0 {
   47         status = "okay";
   48 };
   49 
   50 &gpio2 {
   51         interrupts = <53>, <53>, <53>, <53>,
   52                      <53>, <53>, <53>, <53>,
   53                      <53>, <53>, <53>, <53>,
   54                      <53>, <53>, <53>, <53>,
   55                      <53>, <53>, <53>, <53>,
   56                      <53>, <53>, <53>, <53>,
   57                      <53>, <53>, <53>, <53>,
   58                      <53>, <53>, <53>, <53>;
   59         status = "okay";
   60 };
   61 
   62 &i2c0 {
   63         status = "okay";
   64 };
   65 
   66 &i2c1 {
   67         status = "okay";
   68 };
   69 
   70 &i2c2 {
   71         status = "okay";
   72 };
   73 
   74 &mac0 {
   75         phy-mode = "sgmii";
   76         phy-handle = <&phy0>;
   77         status = "okay";
   78 };
   79 
   80 &mac1 {
   81         phy-mode = "sgmii";
   82         phy-handle = <&phy1>;
   83         status = "okay";
   84 
   85         phy1: ethernet-phy@9 {
   86                 reg = <9>;
   87         };
   88 
   89         phy0: ethernet-phy@8 {
   90                 reg = <8>;
   91         };
   92 };
   93 
   94 &mbox {
   95         status = "okay";
   96 };
   97 
   98 &mmc {
   99         bus-width = <4>;
  100         disable-wp;
  101         cap-sd-highspeed;
  102         cap-mmc-highspeed;
  103         mmc-ddr-1_8v;
  104         mmc-hs200-1_8v;
  105         sd-uhs-sdr12;
  106         sd-uhs-sdr25;
  107         sd-uhs-sdr50;
  108         sd-uhs-sdr104;
  109         status = "okay";
  110 };
  111 
  112 &mmuart1 {
  113         status = "okay";
  114 };
  115 
  116 &mmuart2 {
  117         status = "okay";
  118 };
  119 
  120 &mmuart3 {
  121         status = "okay";
  122 };
  123 
  124 &mmuart4 {
  125         status = "okay";
  126 };
  127 
  128 &pcie {
  129         status = "okay";
  130 };
  131 
  132 &qspi {
  133         status = "okay";
  134 };
  135 
  136 &refclk {
  137         clock-frequency = <125000000>;
  138 };
  139 
  140 &rtc {
  141         status = "okay";
  142 };
  143 
  144 &spi0 {
  145         status = "okay";
  146 };
  147 
  148 &spi1 {
  149         status = "okay";
  150 };
  151 
  152 &syscontroller {
  153         status = "okay";
  154 };
  155 
  156 &usb {
  157         status = "okay";
  158         dr_mode = "host";
  159 };

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FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/riscv/microchip/mpfs-icicle-kit.dts

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/riscv/microchip/mpfs-icicle-kit.dts