Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/riscv/microchip/mpfs.dtsi
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1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright (c) 2020-2021 Microchip Technology Inc */ 3 4 /dts-v1/; 5 #include "dt-bindings/clock/microchip,mpfs-clock.h" 6 7 / { 8 #address-cells = <2>; 9 #size-cells = <2>; 10 model = "Microchip PolarFire SoC"; 11 compatible = "microchip,mpfs"; 12 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu0: cpu@0 { 18 compatible = "sifive,e51", "sifive,rocket0", "riscv"; 19 device_type = "cpu"; 20 i-cache-block-size = <64>; 21 i-cache-sets = <128>; 22 i-cache-size = <16384>; 23 reg = <0>; 24 riscv,isa = "rv64imac"; 25 clocks = <&clkcfg CLK_CPU>; 26 status = "disabled"; 27 28 cpu0_intc: interrupt-controller { 29 #interrupt-cells = <1>; 30 compatible = "riscv,cpu-intc"; 31 interrupt-controller; 32 }; 33 }; 34 35 cpu1: cpu@1 { 36 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 37 d-cache-block-size = <64>; 38 d-cache-sets = <64>; 39 d-cache-size = <32768>; 40 d-tlb-sets = <1>; 41 d-tlb-size = <32>; 42 device_type = "cpu"; 43 i-cache-block-size = <64>; 44 i-cache-sets = <64>; 45 i-cache-size = <32768>; 46 i-tlb-sets = <1>; 47 i-tlb-size = <32>; 48 mmu-type = "riscv,sv39"; 49 reg = <1>; 50 riscv,isa = "rv64imafdc"; 51 clocks = <&clkcfg CLK_CPU>; 52 tlb-split; 53 next-level-cache = <&cctrllr>; 54 status = "okay"; 55 56 cpu1_intc: interrupt-controller { 57 #interrupt-cells = <1>; 58 compatible = "riscv,cpu-intc"; 59 interrupt-controller; 60 }; 61 }; 62 63 cpu2: cpu@2 { 64 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 65 d-cache-block-size = <64>; 66 d-cache-sets = <64>; 67 d-cache-size = <32768>; 68 d-tlb-sets = <1>; 69 d-tlb-size = <32>; 70 device_type = "cpu"; 71 i-cache-block-size = <64>; 72 i-cache-sets = <64>; 73 i-cache-size = <32768>; 74 i-tlb-sets = <1>; 75 i-tlb-size = <32>; 76 mmu-type = "riscv,sv39"; 77 reg = <2>; 78 riscv,isa = "rv64imafdc"; 79 clocks = <&clkcfg CLK_CPU>; 80 tlb-split; 81 next-level-cache = <&cctrllr>; 82 status = "okay"; 83 84 cpu2_intc: interrupt-controller { 85 #interrupt-cells = <1>; 86 compatible = "riscv,cpu-intc"; 87 interrupt-controller; 88 }; 89 }; 90 91 cpu3: cpu@3 { 92 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 93 d-cache-block-size = <64>; 94 d-cache-sets = <64>; 95 d-cache-size = <32768>; 96 d-tlb-sets = <1>; 97 d-tlb-size = <32>; 98 device_type = "cpu"; 99 i-cache-block-size = <64>; 100 i-cache-sets = <64>; 101 i-cache-size = <32768>; 102 i-tlb-sets = <1>; 103 i-tlb-size = <32>; 104 mmu-type = "riscv,sv39"; 105 reg = <3>; 106 riscv,isa = "rv64imafdc"; 107 clocks = <&clkcfg CLK_CPU>; 108 tlb-split; 109 next-level-cache = <&cctrllr>; 110 status = "okay"; 111 112 cpu3_intc: interrupt-controller { 113 #interrupt-cells = <1>; 114 compatible = "riscv,cpu-intc"; 115 interrupt-controller; 116 }; 117 }; 118 119 cpu4: cpu@4 { 120 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 121 d-cache-block-size = <64>; 122 d-cache-sets = <64>; 123 d-cache-size = <32768>; 124 d-tlb-sets = <1>; 125 d-tlb-size = <32>; 126 device_type = "cpu"; 127 i-cache-block-size = <64>; 128 i-cache-sets = <64>; 129 i-cache-size = <32768>; 130 i-tlb-sets = <1>; 131 i-tlb-size = <32>; 132 mmu-type = "riscv,sv39"; 133 reg = <4>; 134 riscv,isa = "rv64imafdc"; 135 clocks = <&clkcfg CLK_CPU>; 136 tlb-split; 137 next-level-cache = <&cctrllr>; 138 status = "okay"; 139 cpu4_intc: interrupt-controller { 140 #interrupt-cells = <1>; 141 compatible = "riscv,cpu-intc"; 142 interrupt-controller; 143 }; 144 }; 145 146 cpu-map { 147 cluster0 { 148 core0 { 149 cpu = <&cpu0>; 150 }; 151 152 core1 { 153 cpu = <&cpu1>; 154 }; 155 156 core2 { 157 cpu = <&cpu2>; 158 }; 159 160 core3 { 161 cpu = <&cpu3>; 162 }; 163 164 core4 { 165 cpu = <&cpu4>; 166 }; 167 }; 168 }; 169 }; 170 171 refclk: mssrefclk { 172 compatible = "fixed-clock"; 173 #clock-cells = <0>; 174 }; 175 176 syscontroller: syscontroller { 177 compatible = "microchip,mpfs-sys-controller"; 178 mboxes = <&mbox 0>; 179 }; 180 181 soc { 182 #address-cells = <2>; 183 #size-cells = <2>; 184 compatible = "simple-bus"; 185 ranges; 186 187 cctrllr: cache-controller@2010000 { 188 compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache"; 189 reg = <0x0 0x2010000 0x0 0x1000>; 190 cache-block-size = <64>; 191 cache-level = <2>; 192 cache-sets = <1024>; 193 cache-size = <2097152>; 194 cache-unified; 195 interrupt-parent = <&plic>; 196 interrupts = <1>, <3>, <4>, <2>; 197 }; 198 199 clint: clint@2000000 { 200 compatible = "sifive,fu540-c000-clint", "sifive,clint0"; 201 reg = <0x0 0x2000000 0x0 0xC000>; 202 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 203 <&cpu1_intc 3>, <&cpu1_intc 7>, 204 <&cpu2_intc 3>, <&cpu2_intc 7>, 205 <&cpu3_intc 3>, <&cpu3_intc 7>, 206 <&cpu4_intc 3>, <&cpu4_intc 7>; 207 }; 208 209 plic: interrupt-controller@c000000 { 210 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; 211 reg = <0x0 0xc000000 0x0 0x4000000>; 212 #address-cells = <0>; 213 #interrupt-cells = <1>; 214 interrupt-controller; 215 interrupts-extended = <&cpu0_intc 11>, 216 <&cpu1_intc 11>, <&cpu1_intc 9>, 217 <&cpu2_intc 11>, <&cpu2_intc 9>, 218 <&cpu3_intc 11>, <&cpu3_intc 9>, 219 <&cpu4_intc 11>, <&cpu4_intc 9>; 220 riscv,ndev = <186>; 221 }; 222 223 pdma: dma-controller@3000000 { 224 compatible = "sifive,fu540-c000-pdma", "sifive,pdma0"; 225 reg = <0x0 0x3000000 0x0 0x8000>; 226 interrupt-parent = <&plic>; 227 interrupts = <5 6>, <7 8>, <9 10>, <11 12>; 228 dma-channels = <4>; 229 #dma-cells = <1>; 230 }; 231 232 clkcfg: clkcfg@20002000 { 233 compatible = "microchip,mpfs-clkcfg"; 234 reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; 235 clocks = <&refclk>; 236 #clock-cells = <1>; 237 }; 238 239 mmuart0: serial@20000000 { 240 compatible = "ns16550a"; 241 reg = <0x0 0x20000000 0x0 0x400>; 242 reg-io-width = <4>; 243 reg-shift = <2>; 244 interrupt-parent = <&plic>; 245 interrupts = <90>; 246 current-speed = <115200>; 247 clocks = <&clkcfg CLK_MMUART0>; 248 status = "disabled"; /* Reserved for the HSS */ 249 }; 250 251 mmuart1: serial@20100000 { 252 compatible = "ns16550a"; 253 reg = <0x0 0x20100000 0x0 0x400>; 254 reg-io-width = <4>; 255 reg-shift = <2>; 256 interrupt-parent = <&plic>; 257 interrupts = <91>; 258 current-speed = <115200>; 259 clocks = <&clkcfg CLK_MMUART1>; 260 status = "disabled"; 261 }; 262 263 mmuart2: serial@20102000 { 264 compatible = "ns16550a"; 265 reg = <0x0 0x20102000 0x0 0x400>; 266 reg-io-width = <4>; 267 reg-shift = <2>; 268 interrupt-parent = <&plic>; 269 interrupts = <92>; 270 current-speed = <115200>; 271 clocks = <&clkcfg CLK_MMUART2>; 272 status = "disabled"; 273 }; 274 275 mmuart3: serial@20104000 { 276 compatible = "ns16550a"; 277 reg = <0x0 0x20104000 0x0 0x400>; 278 reg-io-width = <4>; 279 reg-shift = <2>; 280 interrupt-parent = <&plic>; 281 interrupts = <93>; 282 current-speed = <115200>; 283 clocks = <&clkcfg CLK_MMUART3>; 284 status = "disabled"; 285 }; 286 287 mmuart4: serial@20106000 { 288 compatible = "ns16550a"; 289 reg = <0x0 0x20106000 0x0 0x400>; 290 reg-io-width = <4>; 291 reg-shift = <2>; 292 interrupt-parent = <&plic>; 293 interrupts = <94>; 294 clocks = <&clkcfg CLK_MMUART4>; 295 current-speed = <115200>; 296 status = "disabled"; 297 }; 298 299 /* Common node entry for emmc/sd */ 300 mmc: mmc@20008000 { 301 compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc"; 302 reg = <0x0 0x20008000 0x0 0x1000>; 303 interrupt-parent = <&plic>; 304 interrupts = <88>; 305 clocks = <&clkcfg CLK_MMC>; 306 max-frequency = <200000000>; 307 status = "disabled"; 308 }; 309 310 spi0: spi@20108000 { 311 compatible = "microchip,mpfs-spi"; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 reg = <0x0 0x20108000 0x0 0x1000>; 315 interrupt-parent = <&plic>; 316 interrupts = <54>; 317 clocks = <&clkcfg CLK_SPI0>; 318 status = "disabled"; 319 }; 320 321 spi1: spi@20109000 { 322 compatible = "microchip,mpfs-spi"; 323 #address-cells = <1>; 324 #size-cells = <0>; 325 reg = <0x0 0x20109000 0x0 0x1000>; 326 interrupt-parent = <&plic>; 327 interrupts = <55>; 328 clocks = <&clkcfg CLK_SPI1>; 329 status = "disabled"; 330 }; 331 332 qspi: spi@21000000 { 333 compatible = "microchip,mpfs-qspi"; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 reg = <0x0 0x21000000 0x0 0x1000>; 337 interrupt-parent = <&plic>; 338 interrupts = <85>; 339 clocks = <&clkcfg CLK_QSPI>; 340 status = "disabled"; 341 }; 342 343 i2c0: i2c@2010a000 { 344 compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7"; 345 reg = <0x0 0x2010a000 0x0 0x1000>; 346 #address-cells = <1>; 347 #size-cells = <0>; 348 interrupt-parent = <&plic>; 349 interrupts = <58>; 350 clocks = <&clkcfg CLK_I2C0>; 351 clock-frequency = <100000>; 352 status = "disabled"; 353 }; 354 355 i2c1: i2c@2010b000 { 356 compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7"; 357 reg = <0x0 0x2010b000 0x0 0x1000>; 358 #address-cells = <1>; 359 #size-cells = <0>; 360 interrupt-parent = <&plic>; 361 interrupts = <61>; 362 clocks = <&clkcfg CLK_I2C1>; 363 clock-frequency = <100000>; 364 status = "disabled"; 365 }; 366 367 can0: can@2010c000 { 368 compatible = "microchip,mpfs-can"; 369 reg = <0x0 0x2010c000 0x0 0x1000>; 370 clocks = <&clkcfg CLK_CAN0>; 371 interrupt-parent = <&plic>; 372 interrupts = <56>; 373 status = "disabled"; 374 }; 375 376 can1: can@2010d000 { 377 compatible = "microchip,mpfs-can"; 378 reg = <0x0 0x2010d000 0x0 0x1000>; 379 clocks = <&clkcfg CLK_CAN1>; 380 interrupt-parent = <&plic>; 381 interrupts = <57>; 382 status = "disabled"; 383 }; 384 385 mac0: ethernet@20110000 { 386 compatible = "cdns,macb"; 387 reg = <0x0 0x20110000 0x0 0x2000>; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 interrupt-parent = <&plic>; 391 interrupts = <64>, <65>, <66>, <67>, <68>, <69>; 392 local-mac-address = [00 00 00 00 00 00]; 393 clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; 394 clock-names = "pclk", "hclk"; 395 status = "disabled"; 396 }; 397 398 mac1: ethernet@20112000 { 399 compatible = "cdns,macb"; 400 reg = <0x0 0x20112000 0x0 0x2000>; 401 #address-cells = <1>; 402 #size-cells = <0>; 403 interrupt-parent = <&plic>; 404 interrupts = <70>, <71>, <72>, <73>, <74>, <75>; 405 local-mac-address = [00 00 00 00 00 00]; 406 clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; 407 clock-names = "pclk", "hclk"; 408 status = "disabled"; 409 }; 410 411 gpio0: gpio@20120000 { 412 compatible = "microchip,mpfs-gpio"; 413 reg = <0x0 0x20120000 0x0 0x1000>; 414 interrupt-parent = <&plic>; 415 interrupt-controller; 416 #interrupt-cells = <1>; 417 clocks = <&clkcfg CLK_GPIO0>; 418 gpio-controller; 419 #gpio-cells = <2>; 420 status = "disabled"; 421 }; 422 423 gpio1: gpio@20121000 { 424 compatible = "microchip,mpfs-gpio"; 425 reg = <0x0 0x20121000 0x0 0x1000>; 426 interrupt-parent = <&plic>; 427 interrupt-controller; 428 #interrupt-cells = <1>; 429 clocks = <&clkcfg CLK_GPIO1>; 430 gpio-controller; 431 #gpio-cells = <2>; 432 status = "disabled"; 433 }; 434 435 gpio2: gpio@20122000 { 436 compatible = "microchip,mpfs-gpio"; 437 reg = <0x0 0x20122000 0x0 0x1000>; 438 interrupt-parent = <&plic>; 439 interrupt-controller; 440 #interrupt-cells = <1>; 441 clocks = <&clkcfg CLK_GPIO2>; 442 gpio-controller; 443 #gpio-cells = <2>; 444 status = "disabled"; 445 }; 446 447 rtc: rtc@20124000 { 448 compatible = "microchip,mpfs-rtc"; 449 reg = <0x0 0x20124000 0x0 0x1000>; 450 interrupt-parent = <&plic>; 451 interrupts = <80>, <81>; 452 clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>; 453 clock-names = "rtc", "rtcref"; 454 status = "disabled"; 455 }; 456 457 usb: usb@20201000 { 458 compatible = "microchip,mpfs-musb"; 459 reg = <0x0 0x20201000 0x0 0x1000>; 460 interrupt-parent = <&plic>; 461 interrupts = <86>, <87>; 462 clocks = <&clkcfg CLK_USB>; 463 interrupt-names = "dma","mc"; 464 status = "disabled"; 465 }; 466 467 pcie: pcie@2000000000 { 468 compatible = "microchip,pcie-host-1.0"; 469 #address-cells = <0x3>; 470 #interrupt-cells = <0x1>; 471 #size-cells = <0x2>; 472 device_type = "pci"; 473 reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; 474 reg-names = "cfg", "apb"; 475 bus-range = <0x0 0x7f>; 476 interrupt-parent = <&plic>; 477 interrupts = <119>; 478 interrupt-map = <0 0 0 1 &pcie_intc 0>, 479 <0 0 0 2 &pcie_intc 1>, 480 <0 0 0 3 &pcie_intc 2>, 481 <0 0 0 4 &pcie_intc 3>; 482 interrupt-map-mask = <0 0 0 7>; 483 clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; 484 clock-names = "fic0", "fic1", "fic3"; 485 ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; 486 msi-parent = <&pcie>; 487 msi-controller; 488 status = "disabled"; 489 pcie_intc: interrupt-controller { 490 #address-cells = <0>; 491 #interrupt-cells = <1>; 492 interrupt-controller; 493 }; 494 }; 495 496 mbox: mailbox@37020000 { 497 compatible = "microchip,mpfs-mailbox"; 498 reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>; 499 interrupt-parent = <&plic>; 500 interrupts = <96>; 501 #mbox-cells = <1>; 502 status = "disabled"; 503 }; 504 }; 505 };
Cache object: 214347823b64f4e8121e5856f8c01819
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