Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/riscv/sifive/fu540-c000.dtsi
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1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Copyright (c) 2018-2019 SiFive, Inc */ 3 4 /dts-v1/; 5 6 #include <dt-bindings/clock/sifive-fu540-prci.h> 7 8 / { 9 #address-cells = <2>; 10 #size-cells = <2>; 11 compatible = "sifive,fu540-c000", "sifive,fu540"; 12 13 aliases { 14 serial0 = &uart0; 15 serial1 = &uart1; 16 ethernet0 = ð0; 17 }; 18 19 chosen { 20 }; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 cpu0: cpu@0 { 26 compatible = "sifive,e51", "sifive,rocket0", "riscv"; 27 device_type = "cpu"; 28 i-cache-block-size = <64>; 29 i-cache-sets = <128>; 30 i-cache-size = <16384>; 31 reg = <0>; 32 riscv,isa = "rv64imac"; 33 status = "disabled"; 34 cpu0_intc: interrupt-controller { 35 #interrupt-cells = <1>; 36 compatible = "riscv,cpu-intc"; 37 interrupt-controller; 38 }; 39 }; 40 cpu1: cpu@1 { 41 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 42 d-cache-block-size = <64>; 43 d-cache-sets = <64>; 44 d-cache-size = <32768>; 45 d-tlb-sets = <1>; 46 d-tlb-size = <32>; 47 device_type = "cpu"; 48 i-cache-block-size = <64>; 49 i-cache-sets = <64>; 50 i-cache-size = <32768>; 51 i-tlb-sets = <1>; 52 i-tlb-size = <32>; 53 mmu-type = "riscv,sv39"; 54 reg = <1>; 55 riscv,isa = "rv64imafdc"; 56 tlb-split; 57 next-level-cache = <&l2cache>; 58 cpu1_intc: interrupt-controller { 59 #interrupt-cells = <1>; 60 compatible = "riscv,cpu-intc"; 61 interrupt-controller; 62 }; 63 }; 64 cpu2: cpu@2 { 65 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 66 d-cache-block-size = <64>; 67 d-cache-sets = <64>; 68 d-cache-size = <32768>; 69 d-tlb-sets = <1>; 70 d-tlb-size = <32>; 71 device_type = "cpu"; 72 i-cache-block-size = <64>; 73 i-cache-sets = <64>; 74 i-cache-size = <32768>; 75 i-tlb-sets = <1>; 76 i-tlb-size = <32>; 77 mmu-type = "riscv,sv39"; 78 reg = <2>; 79 riscv,isa = "rv64imafdc"; 80 tlb-split; 81 next-level-cache = <&l2cache>; 82 cpu2_intc: interrupt-controller { 83 #interrupt-cells = <1>; 84 compatible = "riscv,cpu-intc"; 85 interrupt-controller; 86 }; 87 }; 88 cpu3: cpu@3 { 89 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 90 d-cache-block-size = <64>; 91 d-cache-sets = <64>; 92 d-cache-size = <32768>; 93 d-tlb-sets = <1>; 94 d-tlb-size = <32>; 95 device_type = "cpu"; 96 i-cache-block-size = <64>; 97 i-cache-sets = <64>; 98 i-cache-size = <32768>; 99 i-tlb-sets = <1>; 100 i-tlb-size = <32>; 101 mmu-type = "riscv,sv39"; 102 reg = <3>; 103 riscv,isa = "rv64imafdc"; 104 tlb-split; 105 next-level-cache = <&l2cache>; 106 cpu3_intc: interrupt-controller { 107 #interrupt-cells = <1>; 108 compatible = "riscv,cpu-intc"; 109 interrupt-controller; 110 }; 111 }; 112 cpu4: cpu@4 { 113 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; 114 d-cache-block-size = <64>; 115 d-cache-sets = <64>; 116 d-cache-size = <32768>; 117 d-tlb-sets = <1>; 118 d-tlb-size = <32>; 119 device_type = "cpu"; 120 i-cache-block-size = <64>; 121 i-cache-sets = <64>; 122 i-cache-size = <32768>; 123 i-tlb-sets = <1>; 124 i-tlb-size = <32>; 125 mmu-type = "riscv,sv39"; 126 reg = <4>; 127 riscv,isa = "rv64imafdc"; 128 tlb-split; 129 next-level-cache = <&l2cache>; 130 cpu4_intc: interrupt-controller { 131 #interrupt-cells = <1>; 132 compatible = "riscv,cpu-intc"; 133 interrupt-controller; 134 }; 135 }; 136 137 cpu-map { 138 cluster0 { 139 core0 { 140 cpu = <&cpu0>; 141 }; 142 143 core1 { 144 cpu = <&cpu1>; 145 }; 146 147 core2 { 148 cpu = <&cpu2>; 149 }; 150 151 core3 { 152 cpu = <&cpu3>; 153 }; 154 155 core4 { 156 cpu = <&cpu4>; 157 }; 158 }; 159 }; 160 }; 161 soc { 162 #address-cells = <2>; 163 #size-cells = <2>; 164 compatible = "simple-bus"; 165 ranges; 166 plic0: interrupt-controller@c000000 { 167 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; 168 reg = <0x0 0xc000000 0x0 0x4000000>; 169 #address-cells = <0>; 170 #interrupt-cells = <1>; 171 interrupt-controller; 172 interrupts-extended = 173 <&cpu0_intc 0xffffffff>, 174 <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>, 175 <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>, 176 <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>, 177 <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>; 178 riscv,ndev = <53>; 179 }; 180 prci: clock-controller@10000000 { 181 compatible = "sifive,fu540-c000-prci"; 182 reg = <0x0 0x10000000 0x0 0x1000>; 183 clocks = <&hfclk>, <&rtcclk>; 184 #clock-cells = <1>; 185 }; 186 uart0: serial@10010000 { 187 compatible = "sifive,fu540-c000-uart", "sifive,uart0"; 188 reg = <0x0 0x10010000 0x0 0x1000>; 189 interrupt-parent = <&plic0>; 190 interrupts = <4>; 191 clocks = <&prci FU540_PRCI_CLK_TLCLK>; 192 status = "disabled"; 193 }; 194 dma: dma-controller@3000000 { 195 compatible = "sifive,fu540-c000-pdma", "sifive,pdma0"; 196 reg = <0x0 0x3000000 0x0 0x8000>; 197 interrupt-parent = <&plic0>; 198 interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, 199 <30>; 200 dma-channels = <4>; 201 #dma-cells = <1>; 202 }; 203 uart1: serial@10011000 { 204 compatible = "sifive,fu540-c000-uart", "sifive,uart0"; 205 reg = <0x0 0x10011000 0x0 0x1000>; 206 interrupt-parent = <&plic0>; 207 interrupts = <5>; 208 clocks = <&prci FU540_PRCI_CLK_TLCLK>; 209 status = "disabled"; 210 }; 211 i2c0: i2c@10030000 { 212 compatible = "sifive,fu540-c000-i2c", "sifive,i2c0"; 213 reg = <0x0 0x10030000 0x0 0x1000>; 214 interrupt-parent = <&plic0>; 215 interrupts = <50>; 216 clocks = <&prci FU540_PRCI_CLK_TLCLK>; 217 reg-shift = <2>; 218 reg-io-width = <1>; 219 #address-cells = <1>; 220 #size-cells = <0>; 221 status = "disabled"; 222 }; 223 qspi0: spi@10040000 { 224 compatible = "sifive,fu540-c000-spi", "sifive,spi0"; 225 reg = <0x0 0x10040000 0x0 0x1000>, 226 <0x0 0x20000000 0x0 0x10000000>; 227 interrupt-parent = <&plic0>; 228 interrupts = <51>; 229 clocks = <&prci FU540_PRCI_CLK_TLCLK>; 230 #address-cells = <1>; 231 #size-cells = <0>; 232 status = "disabled"; 233 }; 234 qspi1: spi@10041000 { 235 compatible = "sifive,fu540-c000-spi", "sifive,spi0"; 236 reg = <0x0 0x10041000 0x0 0x1000>, 237 <0x0 0x30000000 0x0 0x10000000>; 238 interrupt-parent = <&plic0>; 239 interrupts = <52>; 240 clocks = <&prci FU540_PRCI_CLK_TLCLK>; 241 #address-cells = <1>; 242 #size-cells = <0>; 243 status = "disabled"; 244 }; 245 qspi2: spi@10050000 { 246 compatible = "sifive,fu540-c000-spi", "sifive,spi0"; 247 reg = <0x0 0x10050000 0x0 0x1000>; 248 interrupt-parent = <&plic0>; 249 interrupts = <6>; 250 clocks = <&prci FU540_PRCI_CLK_TLCLK>; 251 #address-cells = <1>; 252 #size-cells = <0>; 253 status = "disabled"; 254 }; 255 eth0: ethernet@10090000 { 256 compatible = "sifive,fu540-c000-gem"; 257 interrupt-parent = <&plic0>; 258 interrupts = <53>; 259 reg = <0x0 0x10090000 0x0 0x2000>, 260 <0x0 0x100a0000 0x0 0x1000>; 261 local-mac-address = [00 00 00 00 00 00]; 262 clock-names = "pclk", "hclk"; 263 clocks = <&prci FU540_PRCI_CLK_GEMGXLPLL>, 264 <&prci FU540_PRCI_CLK_GEMGXLPLL>; 265 #address-cells = <1>; 266 #size-cells = <0>; 267 status = "disabled"; 268 }; 269 pwm0: pwm@10020000 { 270 compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; 271 reg = <0x0 0x10020000 0x0 0x1000>; 272 interrupt-parent = <&plic0>; 273 interrupts = <42>, <43>, <44>, <45>; 274 clocks = <&prci FU540_PRCI_CLK_TLCLK>; 275 #pwm-cells = <3>; 276 status = "disabled"; 277 }; 278 pwm1: pwm@10021000 { 279 compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; 280 reg = <0x0 0x10021000 0x0 0x1000>; 281 interrupt-parent = <&plic0>; 282 interrupts = <46>, <47>, <48>, <49>; 283 clocks = <&prci FU540_PRCI_CLK_TLCLK>; 284 #pwm-cells = <3>; 285 status = "disabled"; 286 }; 287 l2cache: cache-controller@2010000 { 288 compatible = "sifive,fu540-c000-ccache", "cache"; 289 cache-block-size = <64>; 290 cache-level = <2>; 291 cache-sets = <1024>; 292 cache-size = <2097152>; 293 cache-unified; 294 interrupt-parent = <&plic0>; 295 interrupts = <1>, <2>, <3>; 296 reg = <0x0 0x2010000 0x0 0x1000>; 297 }; 298 gpio: gpio@10060000 { 299 compatible = "sifive,fu540-c000-gpio", "sifive,gpio0"; 300 interrupt-parent = <&plic0>; 301 interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>, 302 <14>, <15>, <16>, <17>, <18>, <19>, <20>, 303 <21>, <22>; 304 reg = <0x0 0x10060000 0x0 0x1000>; 305 gpio-controller; 306 #gpio-cells = <2>; 307 interrupt-controller; 308 #interrupt-cells = <2>; 309 clocks = <&prci FU540_PRCI_CLK_TLCLK>; 310 status = "disabled"; 311 }; 312 }; 313 };
Cache object: 4b18928ee9d637fef1e0458f21739763
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