jh7100.dtsi

Version: - FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10

    1 // SPDX-License-Identifier: GPL-2.0 OR MIT
    2 /*
    3  * Copyright (C) 2021 StarFive Technology Co., Ltd.
    4  * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
    5  */
    6 
    7 /dts-v1/;
    8 #include <dt-bindings/clock/starfive-jh7100.h>
    9 #include <dt-bindings/reset/starfive-jh7100.h>
   10 
   11 / {
   12         compatible = "starfive,jh7100";
   13         #address-cells = <2>;
   14         #size-cells = <2>;
   15 
   16         cpus {
   17                 #address-cells = <1>;
   18                 #size-cells = <0>;
   19 
   20                 U74_0: cpu@0 {
   21                         compatible = "sifive,u74-mc", "riscv";
   22                         reg = <0>;
   23                         d-cache-block-size = <64>;
   24                         d-cache-sets = <64>;
   25                         d-cache-size = <32768>;
   26                         d-tlb-sets = <1>;
   27                         d-tlb-size = <32>;
   28                         device_type = "cpu";
   29                         i-cache-block-size = <64>;
   30                         i-cache-sets = <64>;
   31                         i-cache-size = <32768>;
   32                         i-tlb-sets = <1>;
   33                         i-tlb-size = <32>;
   34                         mmu-type = "riscv,sv39";
   35                         riscv,isa = "rv64imafdc";
   36                         tlb-split;
   37 
   38                         cpu0_intc: interrupt-controller {
   39                                 compatible = "riscv,cpu-intc";
   40                                 interrupt-controller;
   41                                 #interrupt-cells = <1>;
   42                         };
   43                 };
   44 
   45                 U74_1: cpu@1 {
   46                         compatible = "sifive,u74-mc", "riscv";
   47                         reg = <1>;
   48                         d-cache-block-size = <64>;
   49                         d-cache-sets = <64>;
   50                         d-cache-size = <32768>;
   51                         d-tlb-sets = <1>;
   52                         d-tlb-size = <32>;
   53                         device_type = "cpu";
   54                         i-cache-block-size = <64>;
   55                         i-cache-sets = <64>;
   56                         i-cache-size = <32768>;
   57                         i-tlb-sets = <1>;
   58                         i-tlb-size = <32>;
   59                         mmu-type = "riscv,sv39";
   60                         riscv,isa = "rv64imafdc";
   61                         tlb-split;
   62 
   63                         cpu1_intc: interrupt-controller {
   64                                 compatible = "riscv,cpu-intc";
   65                                 interrupt-controller;
   66                                 #interrupt-cells = <1>;
   67                         };
   68                 };
   69 
   70                 cpu-map {
   71                         cluster0 {
   72                                 core0 {
   73                                         cpu = <&U74_0>;
   74                                 };
   75 
   76                                 core1 {
   77                                         cpu = <&U74_1>;
   78                                 };
   79                         };
   80                 };
   81         };
   82 
   83         osc_sys: osc_sys {
   84                 compatible = "fixed-clock";
   85                 #clock-cells = <0>;
   86                 /* This value must be overridden by the board */
   87                 clock-frequency = <0>;
   88         };
   89 
   90         osc_aud: osc_aud {
   91                 compatible = "fixed-clock";
   92                 #clock-cells = <0>;
   93                 /* This value must be overridden by the board */
   94                 clock-frequency = <0>;
   95         };
   96 
   97         gmac_rmii_ref: gmac_rmii_ref {
   98                 compatible = "fixed-clock";
   99                 #clock-cells = <0>;
  100                 /* Should be overridden by the board when needed */
  101                 clock-frequency = <0>;
  102         };
  103 
  104         gmac_gr_mii_rxclk: gmac_gr_mii_rxclk {
  105                 compatible = "fixed-clock";
  106                 #clock-cells = <0>;
  107                 /* Should be overridden by the board when needed */
  108                 clock-frequency = <0>;
  109         };
  110 
  111         soc {
  112                 compatible = "simple-bus";
  113                 interrupt-parent = <&plic>;
  114                 #address-cells = <2>;
  115                 #size-cells = <2>;
  116                 ranges;
  117 
  118                 clint: clint@2000000 {
  119                         compatible = "starfive,jh7100-clint", "sifive,clint0";
  120                         reg = <0x0 0x2000000 0x0 0x10000>;
  121                         interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
  122                                                &cpu1_intc 3 &cpu1_intc 7>;
  123                 };
  124 
  125                 plic: interrupt-controller@c000000 {
  126                         compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
  127                         reg = <0x0 0xc000000 0x0 0x4000000>;
  128                         interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9
  129                                                &cpu1_intc 11 &cpu1_intc 9>;
  130                         interrupt-controller;
  131                         #address-cells = <0>;
  132                         #interrupt-cells = <1>;
  133                         riscv,ndev = <133>;
  134                 };
  135 
  136                 clkgen: clock-controller@11800000 {
  137                         compatible = "starfive,jh7100-clkgen";
  138                         reg = <0x0 0x11800000 0x0 0x10000>;
  139                         clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>;
  140                         clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk";
  141                         #clock-cells = <1>;
  142                 };
  143 
  144                 rstgen: reset-controller@11840000 {
  145                         compatible = "starfive,jh7100-reset";
  146                         reg = <0x0 0x11840000 0x0 0x10000>;
  147                         #reset-cells = <1>;
  148                 };
  149 
  150                 i2c0: i2c@118b0000 {
  151                         compatible = "snps,designware-i2c";
  152                         reg = <0x0 0x118b0000 0x0 0x10000>;
  153                         clocks = <&clkgen JH7100_CLK_I2C0_CORE>,
  154                                  <&clkgen JH7100_CLK_I2C0_APB>;
  155                         clock-names = "ref", "pclk";
  156                         resets = <&rstgen JH7100_RSTN_I2C0_APB>;
  157                         interrupts = <96>;
  158                         #address-cells = <1>;
  159                         #size-cells = <0>;
  160                         status = "disabled";
  161                 };
  162 
  163                 i2c1: i2c@118c0000 {
  164                         compatible = "snps,designware-i2c";
  165                         reg = <0x0 0x118c0000 0x0 0x10000>;
  166                         clocks = <&clkgen JH7100_CLK_I2C1_CORE>,
  167                                  <&clkgen JH7100_CLK_I2C1_APB>;
  168                         clock-names = "ref", "pclk";
  169                         resets = <&rstgen JH7100_RSTN_I2C1_APB>;
  170                         interrupts = <97>;
  171                         #address-cells = <1>;
  172                         #size-cells = <0>;
  173                         status = "disabled";
  174                 };
  175 
  176                 gpio: pinctrl@11910000 {
  177                         compatible = "starfive,jh7100-pinctrl";
  178                         reg = <0x0 0x11910000 0x0 0x10000>,
  179                               <0x0 0x11858000 0x0 0x1000>;
  180                         reg-names = "gpio", "padctl";
  181                         clocks = <&clkgen JH7100_CLK_GPIO_APB>;
  182                         resets = <&rstgen JH7100_RSTN_GPIO_APB>;
  183                         interrupts = <32>;
  184                         gpio-controller;
  185                         #gpio-cells = <2>;
  186                         interrupt-controller;
  187                         #interrupt-cells = <2>;
  188                 };
  189 
  190                 uart2: serial@12430000 {
  191                         compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
  192                         reg = <0x0 0x12430000 0x0 0x10000>;
  193                         clocks = <&clkgen JH7100_CLK_UART2_CORE>,
  194                                  <&clkgen JH7100_CLK_UART2_APB>;
  195                         clock-names = "baudclk", "apb_pclk";
  196                         resets = <&rstgen JH7100_RSTN_UART2_APB>;
  197                         interrupts = <72>;
  198                         reg-io-width = <4>;
  199                         reg-shift = <2>;
  200                         status = "disabled";
  201                 };
  202 
  203                 uart3: serial@12440000 {
  204                         compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
  205                         reg = <0x0 0x12440000 0x0 0x10000>;
  206                         clocks = <&clkgen JH7100_CLK_UART3_CORE>,
  207                                  <&clkgen JH7100_CLK_UART3_APB>;
  208                         clock-names = "baudclk", "apb_pclk";
  209                         resets = <&rstgen JH7100_RSTN_UART3_APB>;
  210                         interrupts = <73>;
  211                         reg-io-width = <4>;
  212                         reg-shift = <2>;
  213                         status = "disabled";
  214                 };
  215 
  216                 i2c2: i2c@12450000 {
  217                         compatible = "snps,designware-i2c";
  218                         reg = <0x0 0x12450000 0x0 0x10000>;
  219                         clocks = <&clkgen JH7100_CLK_I2C2_CORE>,
  220                                  <&clkgen JH7100_CLK_I2C2_APB>;
  221                         clock-names = "ref", "pclk";
  222                         resets = <&rstgen JH7100_RSTN_I2C2_APB>;
  223                         interrupts = <74>;
  224                         #address-cells = <1>;
  225                         #size-cells = <0>;
  226                         status = "disabled";
  227                 };
  228 
  229                 i2c3: i2c@12460000 {
  230                         compatible = "snps,designware-i2c";
  231                         reg = <0x0 0x12460000 0x0 0x10000>;
  232                         clocks = <&clkgen JH7100_CLK_I2C3_CORE>,
  233                                  <&clkgen JH7100_CLK_I2C3_APB>;
  234                         clock-names = "ref", "pclk";
  235                         resets = <&rstgen JH7100_RSTN_I2C3_APB>;
  236                         interrupts = <75>;
  237                         #address-cells = <1>;
  238                         #size-cells = <0>;
  239                         status = "disabled";
  240                 };
  241         };
  242 };

Cache object: 58978810607d27b0ecbb11fed7e03f2b

[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.

FreeBSD/Linux Kernel Cross Reference sys/contrib/device-tree/src/riscv/starfive/jh7100.dtsi

FreeBSD/Linux Kernel Cross Reference
sys/contrib/device-tree/src/riscv/starfive/jh7100.dtsi