Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/contrib/ncsw/Peripherals/FM/Pcd/fm_plcr.h
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1 /* 2 * Copyright 2008-2012 Freescale Semiconductor Inc. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * * Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 8 * * Redistributions in binary form must reproduce the above copyright 9 * notice, this list of conditions and the following disclaimer in the 10 * documentation and/or other materials provided with the distribution. 11 * * Neither the name of Freescale Semiconductor nor the 12 * names of its contributors may be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * 16 * ALTERNATIVELY, this software may be distributed under the terms of the 17 * GNU General Public License ("GPL") as published by the Free Software 18 * Foundation, either version 2 of that License or (at your option) any 19 * later version. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 34 /****************************************************************************** 35 @File fm_plcr.h 36 37 @Description FM Policer private header 38 *//***************************************************************************/ 39 #ifndef __FM_PLCR_H 40 #define __FM_PLCR_H 41 42 #include "std_ext.h" 43 44 45 /***********************************************************************/ 46 /* Policer defines */ 47 /***********************************************************************/ 48 49 #define FM_PCD_PLCR_PAR_GO 0x80000000 50 #define FM_PCD_PLCR_PAR_PWSEL_MASK 0x0000FFFF 51 #define FM_PCD_PLCR_PAR_R 0x40000000 52 53 /* shifts */ 54 #define FM_PCD_PLCR_PAR_PNUM_SHIFT 16 55 56 /* masks */ 57 #define FM_PCD_PLCR_PEMODE_PI 0x80000000 58 #define FM_PCD_PLCR_PEMODE_CBLND 0x40000000 59 #define FM_PCD_PLCR_PEMODE_ALG_MASK 0x30000000 60 #define FM_PCD_PLCR_PEMODE_ALG_RFC2698 0x10000000 61 #define FM_PCD_PLCR_PEMODE_ALG_RFC4115 0x20000000 62 #define FM_PCD_PLCR_PEMODE_DEFC_MASK 0x0C000000 63 #define FM_PCD_PLCR_PEMODE_DEFC_Y 0x04000000 64 #define FM_PCD_PLCR_PEMODE_DEFC_R 0x08000000 65 #define FM_PCD_PLCR_PEMODE_DEFC_OVERRIDE 0x0C000000 66 #define FM_PCD_PLCR_PEMODE_OVCLR_MASK 0x03000000 67 #define FM_PCD_PLCR_PEMODE_OVCLR_Y 0x01000000 68 #define FM_PCD_PLCR_PEMODE_OVCLR_R 0x02000000 69 #define FM_PCD_PLCR_PEMODE_OVCLR_G_NC 0x03000000 70 #define FM_PCD_PLCR_PEMODE_PKT 0x00800000 71 #define FM_PCD_PLCR_PEMODE_FPP_MASK 0x001F0000 72 #define FM_PCD_PLCR_PEMODE_FPP_SHIFT 16 73 #define FM_PCD_PLCR_PEMODE_FLS_MASK 0x0000F000 74 #define FM_PCD_PLCR_PEMODE_FLS_L2 0x00003000 75 #define FM_PCD_PLCR_PEMODE_FLS_L3 0x0000B000 76 #define FM_PCD_PLCR_PEMODE_FLS_L4 0x0000E000 77 #define FM_PCD_PLCR_PEMODE_FLS_FULL 0x0000F000 78 #define FM_PCD_PLCR_PEMODE_RBFLS 0x00000800 79 #define FM_PCD_PLCR_PEMODE_TRA 0x00000004 80 #define FM_PCD_PLCR_PEMODE_TRB 0x00000002 81 #define FM_PCD_PLCR_PEMODE_TRC 0x00000001 82 #define FM_PCD_PLCR_DOUBLE_ECC 0x80000000 83 #define FM_PCD_PLCR_INIT_ENTRY_ERROR 0x40000000 84 #define FM_PCD_PLCR_PRAM_SELF_INIT_COMPLETE 0x80000000 85 #define FM_PCD_PLCR_ATOMIC_ACTION_COMPLETE 0x40000000 86 87 #define FM_PCD_PLCR_NIA_VALID 0x80000000 88 89 #define FM_PCD_PLCR_GCR_EN 0x80000000 90 #define FM_PCD_PLCR_GCR_STEN 0x40000000 91 #define FM_PCD_PLCR_GCR_DAR 0x20000000 92 #define FM_PCD_PLCR_GCR_DEFNIA 0x00FFFFFF 93 #define FM_PCD_PLCR_NIA_ABS 0x00000100 94 95 #define FM_PCD_PLCR_GSR_BSY 0x80000000 96 #define FM_PCD_PLCR_GSR_DQS 0x60000000 97 #define FM_PCD_PLCR_GSR_RPB 0x20000000 98 #define FM_PCD_PLCR_GSR_FQS 0x0C000000 99 #define FM_PCD_PLCR_GSR_LPALG 0x0000C000 100 #define FM_PCD_PLCR_GSR_LPCA 0x00003000 101 #define FM_PCD_PLCR_GSR_LPNUM 0x000000FF 102 103 #define FM_PCD_PLCR_EVR_PSIC 0x80000000 104 #define FM_PCD_PLCR_EVR_AAC 0x40000000 105 106 #define FM_PCD_PLCR_PAR_PSI 0x20000000 107 #define FM_PCD_PLCR_PAR_PNUM 0x00FF0000 108 /* PWSEL Selctive select options */ 109 #define FM_PCD_PLCR_PAR_PWSEL_PEMODE 0x00008000 /* 0 */ 110 #define FM_PCD_PLCR_PAR_PWSEL_PEGNIA 0x00004000 /* 1 */ 111 #define FM_PCD_PLCR_PAR_PWSEL_PEYNIA 0x00002000 /* 2 */ 112 #define FM_PCD_PLCR_PAR_PWSEL_PERNIA 0x00001000 /* 3 */ 113 #define FM_PCD_PLCR_PAR_PWSEL_PECIR 0x00000800 /* 4 */ 114 #define FM_PCD_PLCR_PAR_PWSEL_PECBS 0x00000400 /* 5 */ 115 #define FM_PCD_PLCR_PAR_PWSEL_PEPIR_EIR 0x00000200 /* 6 */ 116 #define FM_PCD_PLCR_PAR_PWSEL_PEPBS_EBS 0x00000100 /* 7 */ 117 #define FM_PCD_PLCR_PAR_PWSEL_PELTS 0x00000080 /* 8 */ 118 #define FM_PCD_PLCR_PAR_PWSEL_PECTS 0x00000040 /* 9 */ 119 #define FM_PCD_PLCR_PAR_PWSEL_PEPTS_ETS 0x00000020 /* 10 */ 120 #define FM_PCD_PLCR_PAR_PWSEL_PEGPC 0x00000010 /* 11 */ 121 #define FM_PCD_PLCR_PAR_PWSEL_PEYPC 0x00000008 /* 12 */ 122 #define FM_PCD_PLCR_PAR_PWSEL_PERPC 0x00000004 /* 13 */ 123 #define FM_PCD_PLCR_PAR_PWSEL_PERYPC 0x00000002 /* 14 */ 124 #define FM_PCD_PLCR_PAR_PWSEL_PERRPC 0x00000001 /* 15 */ 125 126 #define FM_PCD_PLCR_PAR_PMR_BRN_1TO1 0x0000 /* - Full bit replacement. {PBNUM[0:N-1] 127 1-> 2^N specific locations. */ 128 #define FM_PCD_PLCR_PAR_PMR_BRN_2TO2 0x1 /* - {PBNUM[0:N-2],PNUM[N-1]}. 129 2-> 2^(N-1) base locations. */ 130 #define FM_PCD_PLCR_PAR_PMR_BRN_4TO4 0x2 /* - {PBNUM[0:N-3],PNUM[N-2:N-1]}. 131 4-> 2^(N-2) base locations. */ 132 #define FM_PCD_PLCR_PAR_PMR_BRN_8TO8 0x3 /* - {PBNUM[0:N-4],PNUM[N-3:N-1]}. 133 8->2^(N-3) base locations. */ 134 #define FM_PCD_PLCR_PAR_PMR_BRN_16TO16 0x4 /* - {PBNUM[0:N-5],PNUM[N-4:N-1]}. 135 16-> 2^(N-4) base locations. */ 136 #define FM_PCD_PLCR_PAR_PMR_BRN_32TO32 0x5 /* {PBNUM[0:N-6],PNUM[N-5:N-1]}. 137 32-> 2^(N-5) base locations. */ 138 #define FM_PCD_PLCR_PAR_PMR_BRN_64TO64 0x6 /* {PBNUM[0:N-7],PNUM[N-6:N-1]}. 139 64-> 2^(N-6) base locations. */ 140 #define FM_PCD_PLCR_PAR_PMR_BRN_128TO128 0x7 /* {PBNUM[0:N-8],PNUM[N-7:N-1]}. 141 128-> 2^(N-7) base locations. */ 142 #define FM_PCD_PLCR_PAR_PMR_BRN_256TO256 0x8 /* - No bit replacement for N=8. {PNUM[N-8:N-1]}. 143 When N=8 this option maps all 256 profiles by the DISPATCH bus into one group. */ 144 145 #define FM_PCD_PLCR_PMR_V 0x80000000 146 #define PLCR_ERR_ECC_CAP 0x80000000 147 #define PLCR_ERR_ECC_TYPE_DOUBLE 0x40000000 148 #define PLCR_ERR_ECC_PNUM_MASK 0x00000FF0 149 #define PLCR_ERR_ECC_OFFSET_MASK 0x0000000F 150 151 #define PLCR_ERR_UNINIT_CAP 0x80000000 152 #define PLCR_ERR_UNINIT_NUM_MASK 0x000000FF 153 #define PLCR_ERR_UNINIT_PID_MASK 0x003f0000 154 #define PLCR_ERR_UNINIT_ABSOLUTE_MASK 0x00008000 155 156 /* shifts */ 157 #define PLCR_ERR_ECC_PNUM_SHIFT 4 158 #define PLCR_ERR_UNINIT_PID_SHIFT 16 159 160 #define FM_PCD_PLCR_PMR_BRN_SHIFT 16 161 162 #define PLCR_PORT_WINDOW_SIZE(hardwarePortId) 163 164 165 #endif /* __FM_PLCR_H */
Cache object: f584fa402da5f36696ba59681862bea4
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