The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/contrib/ncsw/inc/cores/ppc_ext.h

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    1 /*
    2  * Copyright 2008-2012 Freescale Semiconductor Inc.
    3  *
    4  * Redistribution and use in source and binary forms, with or without
    5  * modification, are permitted provided that the following conditions are met:
    6  *     * Redistributions of source code must retain the above copyright
    7  *       notice, this list of conditions and the following disclaimer.
    8  *     * Redistributions in binary form must reproduce the above copyright
    9  *       notice, this list of conditions and the following disclaimer in the
   10  *       documentation and/or other materials provided with the distribution.
   11  *     * Neither the name of Freescale Semiconductor nor the
   12  *       names of its contributors may be used to endorse or promote products
   13  *       derived from this software without specific prior written permission.
   14  *
   15  *
   16  * ALTERNATIVELY, this software may be distributed under the terms of the
   17  * GNU General Public License ("GPL") as published by the Free Software
   18  * Foundation, either version 2 of that License or (at your option) any
   19  * later version.
   20  *
   21  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
   22  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
   23  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
   24  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
   25  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
   26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
   27  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
   28  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
   30  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   31  */
   32 
   33 
   34 /**************************************************************************//**
   35  @File          ppc_ext.h
   36 
   37  @Description   Core API for PowerPC cores
   38 
   39                 These routines must be implemented by each specific PowerPC
   40                 core driver.
   41 *//***************************************************************************/
   42 #ifndef __PPC_EXT_H
   43 #define __PPC_EXT_H
   44 
   45 #include "part_ext.h"
   46 
   47 
   48 #define CORE_IS_BIG_ENDIAN
   49 
   50 #if defined(CORE_E300) || defined(CORE_E500V2)
   51 #define CORE_CACHELINE_SIZE     32
   52 #elif defined(CORE_E500MC) || defined(CORE_E5500) || defined(CORE_E6500)
   53 #define CORE_CACHELINE_SIZE     64
   54 #else
   55 #error "Core not defined!"
   56 #endif /* defined(CORE_E300) || ... */
   57 
   58 
   59 /**************************************************************************//**
   60  @Function      CORE_TestAndSet
   61 
   62  @Description   This routine tries to atomically test-and-set an integer
   63                 in memory to a non-zero value.
   64 
   65                 The memory will be set only if it is tested as zero, in which
   66                 case the routine returns the new non-zero value; otherwise the
   67                 routine returns zero.
   68 
   69  @Param[in]     p - pointer to a volatile int in memory, on which test-and-set
   70                     operation should be made.
   71 
   72  @Retval        Zero        - Operation failed - memory was already set.
   73  @Retval        Non-zero    - Operation succeeded - memory has been set.
   74 *//***************************************************************************/
   75 int CORE_TestAndSet(volatile int *p);
   76 
   77 /**************************************************************************//**
   78  @Function      CORE_InstructionSync
   79 
   80  @Description   This routine will cause the core to wait for previous instructions
   81                 (including any interrupts they generate) to complete before the
   82                 synchronization command executes, which purges all instructions
   83                 from the processor's pipeline and refetches the next instruction.
   84 
   85  @Return        None.
   86 *//***************************************************************************/
   87 void CORE_InstructionSync(void);
   88 
   89 /**************************************************************************//**
   90  @Function      CORE_DCacheEnable
   91 
   92  @Description   Enables the data cache for memory pages that are
   93                 not cache inhibited.
   94 
   95  @Return        None.
   96 *//***************************************************************************/
   97 void CORE_DCacheEnable(void);
   98 
   99 /**************************************************************************//**
  100  @Function      CORE_ICacheEnable
  101 
  102  @Description   Enables the instruction cache for memory pages that are
  103                 not cache inhibited.
  104 
  105  @Return        None.
  106 *//***************************************************************************/
  107 void CORE_ICacheEnable(void);
  108 
  109 /**************************************************************************//**
  110  @Function      CORE_DCacheDisable
  111 
  112  @Description   Disables the data cache.
  113 
  114  @Return        None.
  115 *//***************************************************************************/
  116 void CORE_DCacheDisable(void);
  117 
  118 /**************************************************************************//**
  119  @Function      CORE_ICacheDisable
  120 
  121  @Description   Disables the instruction cache.
  122 
  123  @Return        None.
  124 *//***************************************************************************/
  125 void CORE_ICacheDisable(void);
  126 
  127 
  128 
  129 #include "e500v2_ext.h"
  130 
  131 #endif /* __PPC_EXT_H */

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