1 /*-
2 * Copyright (c) 2003-2005 Nate Lawson (SDG)
3 * Copyright (c) 2001 Michael Smith
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
30
31 #include "opt_acpi.h"
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/cpu.h>
35 #include <sys/kernel.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/pcpu.h>
39 #include <sys/power.h>
40 #include <sys/proc.h>
41 #include <sys/sched.h>
42 #include <sys/sbuf.h>
43 #include <sys/smp.h>
44
45 #include <dev/pci/pcivar.h>
46 #include <machine/atomic.h>
47 #include <machine/bus.h>
48 #if defined(__amd64__) || defined(__i386__)
49 #include <machine/clock.h>
50 #include <machine/specialreg.h>
51 #include <machine/md_var.h>
52 #endif
53 #include <sys/rman.h>
54
55 #include <contrib/dev/acpica/include/acpi.h>
56 #include <contrib/dev/acpica/include/accommon.h>
57
58 #include <dev/acpica/acpivar.h>
59
60 /*
61 * Support for ACPI Processor devices, including C[1-3] sleep states.
62 */
63
64 /* Hooks for the ACPI CA debugging infrastructure */
65 #define _COMPONENT ACPI_PROCESSOR
66 ACPI_MODULE_NAME("PROCESSOR")
67
68 struct acpi_cx {
69 struct resource *p_lvlx; /* Register to read to enter state. */
70 uint32_t type; /* C1-3 (C4 and up treated as C3). */
71 uint32_t trans_lat; /* Transition latency (usec). */
72 uint32_t power; /* Power consumed (mW). */
73 int res_type; /* Resource type for p_lvlx. */
74 int res_rid; /* Resource ID for p_lvlx. */
75 bool do_mwait;
76 uint32_t mwait_hint;
77 bool mwait_hw_coord;
78 bool mwait_bm_avoidance;
79 };
80 #define MAX_CX_STATES 8
81
82 struct acpi_cpu_softc {
83 device_t cpu_dev;
84 ACPI_HANDLE cpu_handle;
85 struct pcpu *cpu_pcpu;
86 uint32_t cpu_acpi_id; /* ACPI processor id */
87 uint32_t cpu_p_blk; /* ACPI P_BLK location */
88 uint32_t cpu_p_blk_len; /* P_BLK length (must be 6). */
89 struct acpi_cx cpu_cx_states[MAX_CX_STATES];
90 int cpu_cx_count; /* Number of valid Cx states. */
91 int cpu_prev_sleep;/* Last idle sleep duration. */
92 int cpu_features; /* Child driver supported features. */
93 /* Runtime state. */
94 int cpu_non_c2; /* Index of lowest non-C2 state. */
95 int cpu_non_c3; /* Index of lowest non-C3 state. */
96 u_int cpu_cx_stats[MAX_CX_STATES];/* Cx usage history. */
97 /* Values for sysctl. */
98 struct sysctl_ctx_list cpu_sysctl_ctx;
99 struct sysctl_oid *cpu_sysctl_tree;
100 int cpu_cx_lowest;
101 int cpu_cx_lowest_lim;
102 int cpu_disable_idle; /* Disable entry to idle function */
103 char cpu_cx_supported[64];
104 };
105
106 struct acpi_cpu_device {
107 struct resource_list ad_rl;
108 };
109
110 #define CPU_GET_REG(reg, width) \
111 (bus_space_read_ ## width(rman_get_bustag((reg)), \
112 rman_get_bushandle((reg)), 0))
113 #define CPU_SET_REG(reg, width, val) \
114 (bus_space_write_ ## width(rman_get_bustag((reg)), \
115 rman_get_bushandle((reg)), 0, (val)))
116
117 #define PM_USEC(x) ((x) >> 2) /* ~4 clocks per usec (3.57955 Mhz) */
118
119 #define ACPI_NOTIFY_CX_STATES 0x81 /* _CST changed. */
120
121 #define CPU_QUIRK_NO_C3 (1<<0) /* C3-type states are not usable. */
122 #define CPU_QUIRK_NO_BM_CTRL (1<<2) /* No bus mastering control. */
123
124 #define PCI_VENDOR_INTEL 0x8086
125 #define PCI_DEVICE_82371AB_3 0x7113 /* PIIX4 chipset for quirks. */
126 #define PCI_REVISION_A_STEP 0
127 #define PCI_REVISION_B_STEP 1
128 #define PCI_REVISION_4E 2
129 #define PCI_REVISION_4M 3
130 #define PIIX4_DEVACTB_REG 0x58
131 #define PIIX4_BRLD_EN_IRQ0 (1<<0)
132 #define PIIX4_BRLD_EN_IRQ (1<<1)
133 #define PIIX4_BRLD_EN_IRQ8 (1<<5)
134 #define PIIX4_STOP_BREAK_MASK (PIIX4_BRLD_EN_IRQ0 | PIIX4_BRLD_EN_IRQ | PIIX4_BRLD_EN_IRQ8)
135 #define PIIX4_PCNTRL_BST_EN (1<<10)
136
137 #define CST_FFH_VENDOR_INTEL 1
138 #define CST_FFH_INTEL_CL_C1IO 1
139 #define CST_FFH_INTEL_CL_MWAIT 2
140 #define CST_FFH_MWAIT_HW_COORD 0x0001
141 #define CST_FFH_MWAIT_BM_AVOID 0x0002
142
143 #define CPUDEV_DEVICE_ID "ACPI0007"
144
145 /* Allow users to ignore processor orders in MADT. */
146 static int cpu_unordered;
147 SYSCTL_INT(_debug_acpi, OID_AUTO, cpu_unordered, CTLFLAG_RDTUN,
148 &cpu_unordered, 0,
149 "Do not use the MADT to match ACPI Processor objects to CPUs.");
150
151 /* Knob to disable acpi_cpu devices */
152 bool acpi_cpu_disabled = false;
153
154 /* Platform hardware resource information. */
155 static uint32_t cpu_smi_cmd; /* Value to write to SMI_CMD. */
156 static uint8_t cpu_cst_cnt; /* Indicate we are _CST aware. */
157 static int cpu_quirks; /* Indicate any hardware bugs. */
158
159 /* Values for sysctl. */
160 static struct sysctl_ctx_list cpu_sysctl_ctx;
161 static struct sysctl_oid *cpu_sysctl_tree;
162 static int cpu_cx_generic;
163 static int cpu_cx_lowest_lim;
164
165 static device_t *cpu_devices;
166 static int cpu_ndevices;
167 static struct acpi_cpu_softc **cpu_softc;
168 ACPI_SERIAL_DECL(cpu, "ACPI CPU");
169
170 static int acpi_cpu_probe(device_t dev);
171 static int acpi_cpu_attach(device_t dev);
172 static int acpi_cpu_suspend(device_t dev);
173 static int acpi_cpu_resume(device_t dev);
174 static int acpi_pcpu_get_id(device_t dev, uint32_t *acpi_id,
175 uint32_t *cpu_id);
176 static struct resource_list *acpi_cpu_get_rlist(device_t dev, device_t child);
177 static device_t acpi_cpu_add_child(device_t dev, u_int order, const char *name,
178 int unit);
179 static int acpi_cpu_read_ivar(device_t dev, device_t child, int index,
180 uintptr_t *result);
181 static int acpi_cpu_shutdown(device_t dev);
182 static void acpi_cpu_cx_probe(struct acpi_cpu_softc *sc);
183 static void acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc);
184 static int acpi_cpu_cx_cst(struct acpi_cpu_softc *sc);
185 static void acpi_cpu_startup(void *arg);
186 static void acpi_cpu_startup_cx(struct acpi_cpu_softc *sc);
187 static void acpi_cpu_cx_list(struct acpi_cpu_softc *sc);
188 #if defined(__i386__) || defined(__amd64__)
189 static void acpi_cpu_idle(sbintime_t sbt);
190 #endif
191 static void acpi_cpu_notify(ACPI_HANDLE h, UINT32 notify, void *context);
192 static void acpi_cpu_quirks(void);
193 static void acpi_cpu_quirks_piix4(void);
194 static int acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS);
195 static int acpi_cpu_usage_counters_sysctl(SYSCTL_HANDLER_ARGS);
196 static int acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc);
197 static int acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS);
198 static int acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS);
199 #if defined(__i386__) || defined(__amd64__)
200 static int acpi_cpu_method_sysctl(SYSCTL_HANDLER_ARGS);
201 #endif
202
203 static device_method_t acpi_cpu_methods[] = {
204 /* Device interface */
205 DEVMETHOD(device_probe, acpi_cpu_probe),
206 DEVMETHOD(device_attach, acpi_cpu_attach),
207 DEVMETHOD(device_detach, bus_generic_detach),
208 DEVMETHOD(device_shutdown, acpi_cpu_shutdown),
209 DEVMETHOD(device_suspend, acpi_cpu_suspend),
210 DEVMETHOD(device_resume, acpi_cpu_resume),
211
212 /* Bus interface */
213 DEVMETHOD(bus_add_child, acpi_cpu_add_child),
214 DEVMETHOD(bus_read_ivar, acpi_cpu_read_ivar),
215 DEVMETHOD(bus_get_resource_list, acpi_cpu_get_rlist),
216 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
217 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
218 DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource),
219 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
220 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
221 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
222 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
223 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
224
225 DEVMETHOD_END
226 };
227
228 static driver_t acpi_cpu_driver = {
229 "cpu",
230 acpi_cpu_methods,
231 sizeof(struct acpi_cpu_softc),
232 };
233
234 static devclass_t acpi_cpu_devclass;
235 DRIVER_MODULE(cpu, acpi, acpi_cpu_driver, acpi_cpu_devclass, 0, 0);
236 MODULE_DEPEND(cpu, acpi, 1, 1, 1);
237
238 static int
239 acpi_cpu_probe(device_t dev)
240 {
241 static char *cpudev_ids[] = { CPUDEV_DEVICE_ID, NULL };
242 int acpi_id, cpu_id;
243 ACPI_BUFFER buf;
244 ACPI_HANDLE handle;
245 ACPI_OBJECT *obj;
246 ACPI_STATUS status;
247 ACPI_OBJECT_TYPE type;
248
249 if (acpi_disabled("cpu") || acpi_cpu_disabled)
250 return (ENXIO);
251 type = acpi_get_type(dev);
252 if (type != ACPI_TYPE_PROCESSOR && type != ACPI_TYPE_DEVICE)
253 return (ENXIO);
254 if (type == ACPI_TYPE_DEVICE &&
255 ACPI_ID_PROBE(device_get_parent(dev), dev, cpudev_ids) == NULL)
256 return (ENXIO);
257
258 handle = acpi_get_handle(dev);
259 if (cpu_softc == NULL)
260 cpu_softc = malloc(sizeof(struct acpi_cpu_softc *) *
261 (mp_maxid + 1), M_TEMP /* XXX */, M_WAITOK | M_ZERO);
262
263 if (type == ACPI_TYPE_PROCESSOR) {
264 /* Get our Processor object. */
265 buf.Pointer = NULL;
266 buf.Length = ACPI_ALLOCATE_BUFFER;
267 status = AcpiEvaluateObject(handle, NULL, NULL, &buf);
268 if (ACPI_FAILURE(status)) {
269 device_printf(dev, "probe failed to get Processor obj - %s\n",
270 AcpiFormatException(status));
271 return (ENXIO);
272 }
273 obj = (ACPI_OBJECT *)buf.Pointer;
274 if (obj->Type != ACPI_TYPE_PROCESSOR) {
275 device_printf(dev, "Processor object has bad type %d\n",
276 obj->Type);
277 AcpiOsFree(obj);
278 return (ENXIO);
279 }
280
281 /*
282 * Find the processor associated with our unit. We could use the
283 * ProcId as a key, however, some boxes do not have the same values
284 * in their Processor object as the ProcId values in the MADT.
285 */
286 acpi_id = obj->Processor.ProcId;
287 AcpiOsFree(obj);
288 } else {
289 status = acpi_GetInteger(handle, "_UID", &acpi_id);
290 if (ACPI_FAILURE(status)) {
291 device_printf(dev, "Device object has bad value - %s\n",
292 AcpiFormatException(status));
293 return (ENXIO);
294 }
295 }
296 if (acpi_pcpu_get_id(dev, &acpi_id, &cpu_id) != 0)
297 return (ENXIO);
298
299 /*
300 * Check if we already probed this processor. We scan the bus twice
301 * so it's possible we've already seen this one.
302 */
303 if (cpu_softc[cpu_id] != NULL)
304 return (ENXIO);
305
306 /* Mark this processor as in-use and save our derived id for attach. */
307 cpu_softc[cpu_id] = (void *)1;
308 acpi_set_private(dev, (void*)(intptr_t)cpu_id);
309 device_set_desc(dev, "ACPI CPU");
310
311 return (0);
312 }
313
314 static int
315 acpi_cpu_attach(device_t dev)
316 {
317 ACPI_BUFFER buf;
318 ACPI_OBJECT arg, *obj;
319 ACPI_OBJECT_LIST arglist;
320 struct pcpu *pcpu_data;
321 struct acpi_cpu_softc *sc;
322 struct acpi_softc *acpi_sc;
323 ACPI_STATUS status;
324 u_int features;
325 int cpu_id, drv_count, i;
326 driver_t **drivers;
327 uint32_t cap_set[3];
328
329 /* UUID needed by _OSC evaluation */
330 static uint8_t cpu_oscuuid[16] = { 0x16, 0xA6, 0x77, 0x40, 0x0C, 0x29,
331 0xBE, 0x47, 0x9E, 0xBD, 0xD8, 0x70,
332 0x58, 0x71, 0x39, 0x53 };
333
334 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
335
336 sc = device_get_softc(dev);
337 sc->cpu_dev = dev;
338 sc->cpu_handle = acpi_get_handle(dev);
339 cpu_id = (int)(intptr_t)acpi_get_private(dev);
340 cpu_softc[cpu_id] = sc;
341 pcpu_data = pcpu_find(cpu_id);
342 pcpu_data->pc_device = dev;
343 sc->cpu_pcpu = pcpu_data;
344 cpu_smi_cmd = AcpiGbl_FADT.SmiCommand;
345 cpu_cst_cnt = AcpiGbl_FADT.CstControl;
346
347 if (acpi_get_type(dev) == ACPI_TYPE_PROCESSOR) {
348 buf.Pointer = NULL;
349 buf.Length = ACPI_ALLOCATE_BUFFER;
350 status = AcpiEvaluateObject(sc->cpu_handle, NULL, NULL, &buf);
351 if (ACPI_FAILURE(status)) {
352 device_printf(dev, "attach failed to get Processor obj - %s\n",
353 AcpiFormatException(status));
354 return (ENXIO);
355 }
356 obj = (ACPI_OBJECT *)buf.Pointer;
357 sc->cpu_p_blk = obj->Processor.PblkAddress;
358 sc->cpu_p_blk_len = obj->Processor.PblkLength;
359 sc->cpu_acpi_id = obj->Processor.ProcId;
360 AcpiOsFree(obj);
361 } else {
362 KASSERT(acpi_get_type(dev) == ACPI_TYPE_DEVICE,
363 ("Unexpected ACPI object"));
364 status = acpi_GetInteger(sc->cpu_handle, "_UID", &sc->cpu_acpi_id);
365 if (ACPI_FAILURE(status)) {
366 device_printf(dev, "Device object has bad value - %s\n",
367 AcpiFormatException(status));
368 return (ENXIO);
369 }
370 sc->cpu_p_blk = 0;
371 sc->cpu_p_blk_len = 0;
372 }
373 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "acpi_cpu%d: P_BLK at %#x/%d\n",
374 device_get_unit(dev), sc->cpu_p_blk, sc->cpu_p_blk_len));
375
376 /*
377 * If this is the first cpu we attach, create and initialize the generic
378 * resources that will be used by all acpi cpu devices.
379 */
380 if (device_get_unit(dev) == 0) {
381 /* Assume we won't be using generic Cx mode by default */
382 cpu_cx_generic = FALSE;
383
384 /* Install hw.acpi.cpu sysctl tree */
385 acpi_sc = acpi_device_get_parent_softc(dev);
386 sysctl_ctx_init(&cpu_sysctl_ctx);
387 cpu_sysctl_tree = SYSCTL_ADD_NODE(&cpu_sysctl_ctx,
388 SYSCTL_CHILDREN(acpi_sc->acpi_sysctl_tree), OID_AUTO, "cpu",
389 CTLFLAG_RD, 0, "node for CPU children");
390 }
391
392 /*
393 * Before calling any CPU methods, collect child driver feature hints
394 * and notify ACPI of them. We support unified SMP power control
395 * so advertise this ourselves. Note this is not the same as independent
396 * SMP control where each CPU can have different settings.
397 */
398 sc->cpu_features = ACPI_CAP_SMP_SAME | ACPI_CAP_SMP_SAME_C3 |
399 ACPI_CAP_C1_IO_HALT;
400
401 #if defined(__i386__) || defined(__amd64__)
402 /*
403 * Ask for MWAIT modes if not disabled and interrupts work
404 * reasonable with MWAIT.
405 */
406 if (!acpi_disabled("mwait") && cpu_mwait_usable())
407 sc->cpu_features |= ACPI_CAP_SMP_C1_NATIVE | ACPI_CAP_SMP_C3_NATIVE;
408 #endif
409
410 if (devclass_get_drivers(acpi_cpu_devclass, &drivers, &drv_count) == 0) {
411 for (i = 0; i < drv_count; i++) {
412 if (ACPI_GET_FEATURES(drivers[i], &features) == 0)
413 sc->cpu_features |= features;
414 }
415 free(drivers, M_TEMP);
416 }
417
418 /*
419 * CPU capabilities are specified in
420 * Intel Processor Vendor-Specific ACPI Interface Specification.
421 */
422 if (sc->cpu_features) {
423 cap_set[1] = sc->cpu_features;
424 status = acpi_EvaluateOSC(sc->cpu_handle, cpu_oscuuid, 1, 2, cap_set,
425 cap_set, false);
426 if (ACPI_SUCCESS(status)) {
427 if (cap_set[0] != 0)
428 device_printf(dev, "_OSC returned status %#x\n", cap_set[0]);
429 }
430 else {
431 arglist.Pointer = &arg;
432 arglist.Count = 1;
433 arg.Type = ACPI_TYPE_BUFFER;
434 arg.Buffer.Length = sizeof(cap_set);
435 arg.Buffer.Pointer = (uint8_t *)cap_set;
436 cap_set[0] = 1; /* revision */
437 cap_set[1] = 1; /* number of capabilities integers */
438 cap_set[2] = sc->cpu_features;
439 AcpiEvaluateObject(sc->cpu_handle, "_PDC", &arglist, NULL);
440 }
441 }
442
443 /* Probe for Cx state support. */
444 acpi_cpu_cx_probe(sc);
445
446 return (0);
447 }
448
449 static void
450 acpi_cpu_postattach(void *unused __unused)
451 {
452 device_t *devices;
453 int err;
454 int i, n;
455 int attached;
456
457 err = devclass_get_devices(acpi_cpu_devclass, &devices, &n);
458 if (err != 0) {
459 printf("devclass_get_devices(acpi_cpu_devclass) failed\n");
460 return;
461 }
462 attached = 0;
463 for (i = 0; i < n; i++)
464 if (device_is_attached(devices[i]) &&
465 device_get_driver(devices[i]) == &acpi_cpu_driver)
466 attached = 1;
467 for (i = 0; i < n; i++)
468 bus_generic_probe(devices[i]);
469 for (i = 0; i < n; i++)
470 bus_generic_attach(devices[i]);
471 free(devices, M_TEMP);
472
473 if (attached) {
474 #ifdef EARLY_AP_STARTUP
475 acpi_cpu_startup(NULL);
476 #else
477 /* Queue post cpu-probing task handler */
478 AcpiOsExecute(OSL_NOTIFY_HANDLER, acpi_cpu_startup, NULL);
479 #endif
480 }
481 }
482
483 SYSINIT(acpi_cpu, SI_SUB_CONFIGURE, SI_ORDER_MIDDLE,
484 acpi_cpu_postattach, NULL);
485
486 static void
487 disable_idle(struct acpi_cpu_softc *sc)
488 {
489 cpuset_t cpuset;
490
491 CPU_SETOF(sc->cpu_pcpu->pc_cpuid, &cpuset);
492 sc->cpu_disable_idle = TRUE;
493
494 /*
495 * Ensure that the CPU is not in idle state or in acpi_cpu_idle().
496 * Note that this code depends on the fact that the rendezvous IPI
497 * can not penetrate context where interrupts are disabled and acpi_cpu_idle
498 * is called and executed in such a context with interrupts being re-enabled
499 * right before return.
500 */
501 smp_rendezvous_cpus(cpuset, smp_no_rendezvous_barrier, NULL,
502 smp_no_rendezvous_barrier, NULL);
503 }
504
505 static void
506 enable_idle(struct acpi_cpu_softc *sc)
507 {
508
509 sc->cpu_disable_idle = FALSE;
510 }
511
512 #if defined(__i386__) || defined(__amd64__)
513 static int
514 is_idle_disabled(struct acpi_cpu_softc *sc)
515 {
516
517 return (sc->cpu_disable_idle);
518 }
519 #endif
520
521 /*
522 * Disable any entry to the idle function during suspend and re-enable it
523 * during resume.
524 */
525 static int
526 acpi_cpu_suspend(device_t dev)
527 {
528 int error;
529
530 error = bus_generic_suspend(dev);
531 if (error)
532 return (error);
533 disable_idle(device_get_softc(dev));
534 return (0);
535 }
536
537 static int
538 acpi_cpu_resume(device_t dev)
539 {
540
541 enable_idle(device_get_softc(dev));
542 return (bus_generic_resume(dev));
543 }
544
545 /*
546 * Find the processor associated with a given ACPI ID. By default,
547 * use the MADT to map ACPI IDs to APIC IDs and use that to locate a
548 * processor. Some systems have inconsistent ASL and MADT however.
549 * For these systems the cpu_unordered tunable can be set in which
550 * case we assume that Processor objects are listed in the same order
551 * in both the MADT and ASL.
552 */
553 static int
554 acpi_pcpu_get_id(device_t dev, uint32_t *acpi_id, uint32_t *cpu_id)
555 {
556 struct pcpu *pc;
557 uint32_t i, idx;
558
559 KASSERT(acpi_id != NULL, ("Null acpi_id"));
560 KASSERT(cpu_id != NULL, ("Null cpu_id"));
561 idx = device_get_unit(dev);
562
563 /*
564 * If pc_acpi_id for CPU 0 is not initialized (e.g. a non-APIC
565 * UP box) use the ACPI ID from the first processor we find.
566 */
567 if (idx == 0 && mp_ncpus == 1) {
568 pc = pcpu_find(0);
569 if (pc->pc_acpi_id == 0xffffffff)
570 pc->pc_acpi_id = *acpi_id;
571 *cpu_id = 0;
572 return (0);
573 }
574
575 CPU_FOREACH(i) {
576 pc = pcpu_find(i);
577 KASSERT(pc != NULL, ("no pcpu data for %d", i));
578 if (cpu_unordered) {
579 if (idx-- == 0) {
580 /*
581 * If pc_acpi_id doesn't match the ACPI ID from the
582 * ASL, prefer the MADT-derived value.
583 */
584 if (pc->pc_acpi_id != *acpi_id)
585 *acpi_id = pc->pc_acpi_id;
586 *cpu_id = pc->pc_cpuid;
587 return (0);
588 }
589 } else {
590 if (pc->pc_acpi_id == *acpi_id) {
591 if (bootverbose)
592 device_printf(dev,
593 "Processor %s (ACPI ID %u) -> APIC ID %d\n",
594 acpi_name(acpi_get_handle(dev)), *acpi_id,
595 pc->pc_cpuid);
596 *cpu_id = pc->pc_cpuid;
597 return (0);
598 }
599 }
600 }
601
602 if (bootverbose)
603 printf("ACPI: Processor %s (ACPI ID %u) ignored\n",
604 acpi_name(acpi_get_handle(dev)), *acpi_id);
605
606 return (ESRCH);
607 }
608
609 static struct resource_list *
610 acpi_cpu_get_rlist(device_t dev, device_t child)
611 {
612 struct acpi_cpu_device *ad;
613
614 ad = device_get_ivars(child);
615 if (ad == NULL)
616 return (NULL);
617 return (&ad->ad_rl);
618 }
619
620 static device_t
621 acpi_cpu_add_child(device_t dev, u_int order, const char *name, int unit)
622 {
623 struct acpi_cpu_device *ad;
624 device_t child;
625
626 if ((ad = malloc(sizeof(*ad), M_TEMP, M_NOWAIT | M_ZERO)) == NULL)
627 return (NULL);
628
629 resource_list_init(&ad->ad_rl);
630
631 child = device_add_child_ordered(dev, order, name, unit);
632 if (child != NULL)
633 device_set_ivars(child, ad);
634 else
635 free(ad, M_TEMP);
636 return (child);
637 }
638
639 static int
640 acpi_cpu_read_ivar(device_t dev, device_t child, int index, uintptr_t *result)
641 {
642 struct acpi_cpu_softc *sc;
643
644 sc = device_get_softc(dev);
645 switch (index) {
646 case ACPI_IVAR_HANDLE:
647 *result = (uintptr_t)sc->cpu_handle;
648 break;
649 case CPU_IVAR_PCPU:
650 *result = (uintptr_t)sc->cpu_pcpu;
651 break;
652 #if defined(__amd64__) || defined(__i386__)
653 case CPU_IVAR_NOMINAL_MHZ:
654 if (tsc_is_invariant) {
655 *result = (uintptr_t)(atomic_load_acq_64(&tsc_freq) / 1000000);
656 break;
657 }
658 /* FALLTHROUGH */
659 #endif
660 default:
661 return (ENOENT);
662 }
663 return (0);
664 }
665
666 static int
667 acpi_cpu_shutdown(device_t dev)
668 {
669 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
670
671 /* Allow children to shutdown first. */
672 bus_generic_shutdown(dev);
673
674 /*
675 * Disable any entry to the idle function.
676 */
677 disable_idle(device_get_softc(dev));
678
679 /*
680 * CPU devices are not truly detached and remain referenced,
681 * so their resources are not freed.
682 */
683
684 return_VALUE (0);
685 }
686
687 static void
688 acpi_cpu_cx_probe(struct acpi_cpu_softc *sc)
689 {
690 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
691
692 /* Use initial sleep value of 1 sec. to start with lowest idle state. */
693 sc->cpu_prev_sleep = 1000000;
694 sc->cpu_cx_lowest = 0;
695 sc->cpu_cx_lowest_lim = 0;
696
697 /*
698 * Check for the ACPI 2.0 _CST sleep states object. If we can't find
699 * any, we'll revert to generic FADT/P_BLK Cx control method which will
700 * be handled by acpi_cpu_startup. We need to defer to after having
701 * probed all the cpus in the system before probing for generic Cx
702 * states as we may already have found cpus with valid _CST packages
703 */
704 if (!cpu_cx_generic && acpi_cpu_cx_cst(sc) != 0) {
705 /*
706 * We were unable to find a _CST package for this cpu or there
707 * was an error parsing it. Switch back to generic mode.
708 */
709 cpu_cx_generic = TRUE;
710 if (bootverbose)
711 device_printf(sc->cpu_dev, "switching to generic Cx mode\n");
712 }
713
714 /*
715 * TODO: _CSD Package should be checked here.
716 */
717 }
718
719 static void
720 acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc)
721 {
722 ACPI_GENERIC_ADDRESS gas;
723 struct acpi_cx *cx_ptr;
724
725 sc->cpu_cx_count = 0;
726 cx_ptr = sc->cpu_cx_states;
727
728 /* Use initial sleep value of 1 sec. to start with lowest idle state. */
729 sc->cpu_prev_sleep = 1000000;
730
731 /* C1 has been required since just after ACPI 1.0 */
732 cx_ptr->type = ACPI_STATE_C1;
733 cx_ptr->trans_lat = 0;
734 cx_ptr++;
735 sc->cpu_non_c2 = sc->cpu_cx_count;
736 sc->cpu_non_c3 = sc->cpu_cx_count;
737 sc->cpu_cx_count++;
738
739 /*
740 * The spec says P_BLK must be 6 bytes long. However, some systems
741 * use it to indicate a fractional set of features present so we
742 * take 5 as C2. Some may also have a value of 7 to indicate
743 * another C3 but most use _CST for this (as required) and having
744 * "only" C1-C3 is not a hardship.
745 */
746 if (sc->cpu_p_blk_len < 5)
747 return;
748
749 /* Validate and allocate resources for C2 (P_LVL2). */
750 gas.SpaceId = ACPI_ADR_SPACE_SYSTEM_IO;
751 gas.BitWidth = 8;
752 if (AcpiGbl_FADT.C2Latency <= 100) {
753 gas.Address = sc->cpu_p_blk + 4;
754 cx_ptr->res_rid = 0;
755 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &cx_ptr->res_rid,
756 &gas, &cx_ptr->p_lvlx, RF_SHAREABLE);
757 if (cx_ptr->p_lvlx != NULL) {
758 cx_ptr->type = ACPI_STATE_C2;
759 cx_ptr->trans_lat = AcpiGbl_FADT.C2Latency;
760 cx_ptr++;
761 sc->cpu_non_c3 = sc->cpu_cx_count;
762 sc->cpu_cx_count++;
763 }
764 }
765 if (sc->cpu_p_blk_len < 6)
766 return;
767
768 /* Validate and allocate resources for C3 (P_LVL3). */
769 if (AcpiGbl_FADT.C3Latency <= 1000 && !(cpu_quirks & CPU_QUIRK_NO_C3)) {
770 gas.Address = sc->cpu_p_blk + 5;
771 cx_ptr->res_rid = 1;
772 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &cx_ptr->res_rid,
773 &gas, &cx_ptr->p_lvlx, RF_SHAREABLE);
774 if (cx_ptr->p_lvlx != NULL) {
775 cx_ptr->type = ACPI_STATE_C3;
776 cx_ptr->trans_lat = AcpiGbl_FADT.C3Latency;
777 cx_ptr++;
778 sc->cpu_cx_count++;
779 }
780 }
781 }
782
783 #if defined(__i386__) || defined(__amd64__)
784 static void
785 acpi_cpu_cx_cst_mwait(struct acpi_cx *cx_ptr, uint64_t address, int accsize)
786 {
787
788 cx_ptr->do_mwait = true;
789 cx_ptr->mwait_hint = address & 0xffffffff;
790 cx_ptr->mwait_hw_coord = (accsize & CST_FFH_MWAIT_HW_COORD) != 0;
791 cx_ptr->mwait_bm_avoidance = (accsize & CST_FFH_MWAIT_BM_AVOID) != 0;
792 }
793 #endif
794
795 static void
796 acpi_cpu_cx_cst_free_plvlx(device_t cpu_dev, struct acpi_cx *cx_ptr)
797 {
798
799 if (cx_ptr->p_lvlx == NULL)
800 return;
801 bus_release_resource(cpu_dev, cx_ptr->res_type, cx_ptr->res_rid,
802 cx_ptr->p_lvlx);
803 cx_ptr->p_lvlx = NULL;
804 }
805
806 /*
807 * Parse a _CST package and set up its Cx states. Since the _CST object
808 * can change dynamically, our notify handler may call this function
809 * to clean up and probe the new _CST package.
810 */
811 static int
812 acpi_cpu_cx_cst(struct acpi_cpu_softc *sc)
813 {
814 struct acpi_cx *cx_ptr;
815 ACPI_STATUS status;
816 ACPI_BUFFER buf;
817 ACPI_OBJECT *top;
818 ACPI_OBJECT *pkg;
819 uint32_t count;
820 int i;
821 #if defined(__i386__) || defined(__amd64__)
822 uint64_t address;
823 int vendor, class, accsize;
824 #endif
825
826 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
827
828 buf.Pointer = NULL;
829 buf.Length = ACPI_ALLOCATE_BUFFER;
830 status = AcpiEvaluateObject(sc->cpu_handle, "_CST", NULL, &buf);
831 if (ACPI_FAILURE(status))
832 return (ENXIO);
833
834 /* _CST is a package with a count and at least one Cx package. */
835 top = (ACPI_OBJECT *)buf.Pointer;
836 if (!ACPI_PKG_VALID(top, 2) || acpi_PkgInt32(top, 0, &count) != 0) {
837 device_printf(sc->cpu_dev, "invalid _CST package\n");
838 AcpiOsFree(buf.Pointer);
839 return (ENXIO);
840 }
841 if (count != top->Package.Count - 1) {
842 device_printf(sc->cpu_dev, "invalid _CST state count (%d != %d)\n",
843 count, top->Package.Count - 1);
844 count = top->Package.Count - 1;
845 }
846 if (count > MAX_CX_STATES) {
847 device_printf(sc->cpu_dev, "_CST has too many states (%d)\n", count);
848 count = MAX_CX_STATES;
849 }
850
851 sc->cpu_non_c2 = 0;
852 sc->cpu_non_c3 = 0;
853 sc->cpu_cx_count = 0;
854 cx_ptr = sc->cpu_cx_states;
855
856 /*
857 * C1 has been required since just after ACPI 1.0.
858 * Reserve the first slot for it.
859 */
860 cx_ptr->type = ACPI_STATE_C0;
861 cx_ptr++;
862 sc->cpu_cx_count++;
863
864 /* Set up all valid states. */
865 for (i = 0; i < count; i++) {
866 pkg = &top->Package.Elements[i + 1];
867 if (!ACPI_PKG_VALID(pkg, 4) ||
868 acpi_PkgInt32(pkg, 1, &cx_ptr->type) != 0 ||
869 acpi_PkgInt32(pkg, 2, &cx_ptr->trans_lat) != 0 ||
870 acpi_PkgInt32(pkg, 3, &cx_ptr->power) != 0) {
871
872 device_printf(sc->cpu_dev, "skipping invalid Cx state package\n");
873 continue;
874 }
875
876 /* Validate the state to see if we should use it. */
877 switch (cx_ptr->type) {
878 case ACPI_STATE_C1:
879 acpi_cpu_cx_cst_free_plvlx(sc->cpu_dev, cx_ptr);
880 #if defined(__i386__) || defined(__amd64__)
881 if (acpi_PkgFFH_IntelCpu(pkg, 0, &vendor, &class, &address,
882 &accsize) == 0 && vendor == CST_FFH_VENDOR_INTEL) {
883 if (class == CST_FFH_INTEL_CL_C1IO) {
884 /* C1 I/O then Halt */
885 cx_ptr->res_rid = sc->cpu_cx_count;
886 bus_set_resource(sc->cpu_dev, SYS_RES_IOPORT,
887 cx_ptr->res_rid, address, 1);
888 cx_ptr->p_lvlx = bus_alloc_resource_any(sc->cpu_dev,
889 SYS_RES_IOPORT, &cx_ptr->res_rid, RF_ACTIVE |
890 RF_SHAREABLE);
891 if (cx_ptr->p_lvlx == NULL) {
892 bus_delete_resource(sc->cpu_dev, SYS_RES_IOPORT,
893 cx_ptr->res_rid);
894 device_printf(sc->cpu_dev,
895 "C1 I/O failed to allocate port %d, "
896 "degrading to C1 Halt", (int)address);
897 }
898 } else if (class == CST_FFH_INTEL_CL_MWAIT) {
899 acpi_cpu_cx_cst_mwait(cx_ptr, address, accsize);
900 }
901 }
902 #endif
903 if (sc->cpu_cx_states[0].type == ACPI_STATE_C0) {
904 /* This is the first C1 state. Use the reserved slot. */
905 sc->cpu_cx_states[0] = *cx_ptr;
906 } else {
907 sc->cpu_non_c2 = sc->cpu_cx_count;
908 sc->cpu_non_c3 = sc->cpu_cx_count;
909 cx_ptr++;
910 sc->cpu_cx_count++;
911 }
912 continue;
913 case ACPI_STATE_C2:
914 sc->cpu_non_c3 = sc->cpu_cx_count;
915 break;
916 case ACPI_STATE_C3:
917 default:
918 if ((cpu_quirks & CPU_QUIRK_NO_C3) != 0) {
919 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
920 "acpi_cpu%d: C3[%d] not available.\n",
921 device_get_unit(sc->cpu_dev), i));
922 continue;
923 }
924 break;
925 }
926
927 /* Free up any previous register. */
928 acpi_cpu_cx_cst_free_plvlx(sc->cpu_dev, cx_ptr);
929
930 /* Allocate the control register for C2 or C3. */
931 #if defined(__i386__) || defined(__amd64__)
932 if (acpi_PkgFFH_IntelCpu(pkg, 0, &vendor, &class, &address,
933 &accsize) == 0 && vendor == CST_FFH_VENDOR_INTEL &&
934 class == CST_FFH_INTEL_CL_MWAIT) {
935 /* Native C State Instruction use (mwait) */
936 acpi_cpu_cx_cst_mwait(cx_ptr, address, accsize);
937 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
938 "acpi_cpu%d: Got C%d/mwait - %d latency\n",
939 device_get_unit(sc->cpu_dev), cx_ptr->type, cx_ptr->trans_lat));
940 cx_ptr++;
941 sc->cpu_cx_count++;
942 } else
943 #endif
944 {
945 cx_ptr->res_rid = sc->cpu_cx_count;
946 acpi_PkgGas(sc->cpu_dev, pkg, 0, &cx_ptr->res_type,
947 &cx_ptr->res_rid, &cx_ptr->p_lvlx, RF_SHAREABLE);
948 if (cx_ptr->p_lvlx) {
949 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
950 "acpi_cpu%d: Got C%d - %d latency\n",
951 device_get_unit(sc->cpu_dev), cx_ptr->type,
952 cx_ptr->trans_lat));
953 cx_ptr++;
954 sc->cpu_cx_count++;
955 }
956 }
957 }
958 AcpiOsFree(buf.Pointer);
959
960 /* If C1 state was not found, we need one now. */
961 cx_ptr = sc->cpu_cx_states;
962 if (cx_ptr->type == ACPI_STATE_C0) {
963 cx_ptr->type = ACPI_STATE_C1;
964 cx_ptr->trans_lat = 0;
965 }
966
967 return (0);
968 }
969
970 /*
971 * Call this *after* all CPUs have been attached.
972 */
973 static void
974 acpi_cpu_startup(void *arg)
975 {
976 struct acpi_cpu_softc *sc;
977 int i;
978
979 /* Get set of CPU devices */
980 devclass_get_devices(acpi_cpu_devclass, &cpu_devices, &cpu_ndevices);
981
982 /*
983 * Setup any quirks that might necessary now that we have probed
984 * all the CPUs
985 */
986 acpi_cpu_quirks();
987
988 if (cpu_cx_generic) {
989 /*
990 * We are using generic Cx mode, probe for available Cx states
991 * for all processors.
992 */
993 for (i = 0; i < cpu_ndevices; i++) {
994 sc = device_get_softc(cpu_devices[i]);
995 acpi_cpu_generic_cx_probe(sc);
996 }
997 } else {
998 /*
999 * We are using _CST mode, remove C3 state if necessary.
1000 * As we now know for sure that we will be using _CST mode
1001 * install our notify handler.
1002 */
1003 for (i = 0; i < cpu_ndevices; i++) {
1004 sc = device_get_softc(cpu_devices[i]);
1005 if (cpu_quirks & CPU_QUIRK_NO_C3) {
1006 sc->cpu_cx_count = min(sc->cpu_cx_count, sc->cpu_non_c3 + 1);
1007 }
1008 AcpiInstallNotifyHandler(sc->cpu_handle, ACPI_DEVICE_NOTIFY,
1009 acpi_cpu_notify, sc);
1010 }
1011 }
1012
1013 /* Perform Cx final initialization. */
1014 for (i = 0; i < cpu_ndevices; i++) {
1015 sc = device_get_softc(cpu_devices[i]);
1016 acpi_cpu_startup_cx(sc);
1017 }
1018
1019 /* Add a sysctl handler to handle global Cx lowest setting */
1020 SYSCTL_ADD_PROC(&cpu_sysctl_ctx, SYSCTL_CHILDREN(cpu_sysctl_tree),
1021 OID_AUTO, "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW,
1022 NULL, 0, acpi_cpu_global_cx_lowest_sysctl, "A",
1023 "Global lowest Cx sleep state to use");
1024
1025 /* Take over idling from cpu_idle_default(). */
1026 cpu_cx_lowest_lim = 0;
1027 for (i = 0; i < cpu_ndevices; i++) {
1028 sc = device_get_softc(cpu_devices[i]);
1029 enable_idle(sc);
1030 }
1031 #if defined(__i386__) || defined(__amd64__)
1032 cpu_idle_hook = acpi_cpu_idle;
1033 #endif
1034 }
1035
1036 static void
1037 acpi_cpu_cx_list(struct acpi_cpu_softc *sc)
1038 {
1039 struct sbuf sb;
1040 int i;
1041
1042 /*
1043 * Set up the list of Cx states
1044 */
1045 sbuf_new(&sb, sc->cpu_cx_supported, sizeof(sc->cpu_cx_supported),
1046 SBUF_FIXEDLEN);
1047 for (i = 0; i < sc->cpu_cx_count; i++)
1048 sbuf_printf(&sb, "C%d/%d/%d ", i + 1, sc->cpu_cx_states[i].type,
1049 sc->cpu_cx_states[i].trans_lat);
1050 sbuf_trim(&sb);
1051 sbuf_finish(&sb);
1052 }
1053
1054 static void
1055 acpi_cpu_startup_cx(struct acpi_cpu_softc *sc)
1056 {
1057 acpi_cpu_cx_list(sc);
1058
1059 SYSCTL_ADD_STRING(&sc->cpu_sysctl_ctx,
1060 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)),
1061 OID_AUTO, "cx_supported", CTLFLAG_RD,
1062 sc->cpu_cx_supported, 0,
1063 "Cx/microsecond values for supported Cx states");
1064 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx,
1065 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)),
1066 OID_AUTO, "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW,
1067 (void *)sc, 0, acpi_cpu_cx_lowest_sysctl, "A",
1068 "lowest Cx sleep state to use");
1069 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx,
1070 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)),
1071 OID_AUTO, "cx_usage", CTLTYPE_STRING | CTLFLAG_RD,
1072 (void *)sc, 0, acpi_cpu_usage_sysctl, "A",
1073 "percent usage for each Cx state");
1074 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx,
1075 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)),
1076 OID_AUTO, "cx_usage_counters", CTLTYPE_STRING | CTLFLAG_RD,
1077 (void *)sc, 0, acpi_cpu_usage_counters_sysctl, "A",
1078 "Cx sleep state counters");
1079 #if defined(__i386__) || defined(__amd64__)
1080 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx,
1081 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)),
1082 OID_AUTO, "cx_method", CTLTYPE_STRING | CTLFLAG_RD,
1083 (void *)sc, 0, acpi_cpu_method_sysctl, "A",
1084 "Cx entrance methods");
1085 #endif
1086
1087 /* Signal platform that we can handle _CST notification. */
1088 if (!cpu_cx_generic && cpu_cst_cnt != 0) {
1089 ACPI_LOCK(acpi);
1090 AcpiOsWritePort(cpu_smi_cmd, cpu_cst_cnt, 8);
1091 ACPI_UNLOCK(acpi);
1092 }
1093 }
1094
1095 #if defined(__i386__) || defined(__amd64__)
1096 /*
1097 * Idle the CPU in the lowest state possible. This function is called with
1098 * interrupts disabled. Note that once it re-enables interrupts, a task
1099 * switch can occur so do not access shared data (i.e. the softc) after
1100 * interrupts are re-enabled.
1101 */
1102 static void
1103 acpi_cpu_idle(sbintime_t sbt)
1104 {
1105 struct acpi_cpu_softc *sc;
1106 struct acpi_cx *cx_next;
1107 uint64_t cputicks;
1108 uint32_t start_time, end_time;
1109 ACPI_STATUS status;
1110 int bm_active, cx_next_idx, i, us;
1111
1112 /*
1113 * Look up our CPU id to get our softc. If it's NULL, we'll use C1
1114 * since there is no ACPI processor object for this CPU. This occurs
1115 * for logical CPUs in the HTT case.
1116 */
1117 sc = cpu_softc[PCPU_GET(cpuid)];
1118 if (sc == NULL) {
1119 acpi_cpu_c1();
1120 return;
1121 }
1122
1123 /* If disabled, take the safe path. */
1124 if (is_idle_disabled(sc)) {
1125 acpi_cpu_c1();
1126 return;
1127 }
1128
1129 /* Find the lowest state that has small enough latency. */
1130 us = sc->cpu_prev_sleep;
1131 if (sbt >= 0 && us > (sbt >> 12))
1132 us = (sbt >> 12);
1133 cx_next_idx = 0;
1134 if (cpu_disable_c2_sleep)
1135 i = min(sc->cpu_cx_lowest, sc->cpu_non_c2);
1136 else if (cpu_disable_c3_sleep)
1137 i = min(sc->cpu_cx_lowest, sc->cpu_non_c3);
1138 else
1139 i = sc->cpu_cx_lowest;
1140 for (; i >= 0; i--) {
1141 if (sc->cpu_cx_states[i].trans_lat * 3 <= us) {
1142 cx_next_idx = i;
1143 break;
1144 }
1145 }
1146
1147 /*
1148 * Check for bus master activity. If there was activity, clear
1149 * the bit and use the lowest non-C3 state. Note that the USB
1150 * driver polling for new devices keeps this bit set all the
1151 * time if USB is loaded.
1152 */
1153 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0 &&
1154 cx_next_idx > sc->cpu_non_c3) {
1155 status = AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active);
1156 if (ACPI_SUCCESS(status) && bm_active != 0) {
1157 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1);
1158 cx_next_idx = sc->cpu_non_c3;
1159 }
1160 }
1161
1162 /* Select the next state and update statistics. */
1163 cx_next = &sc->cpu_cx_states[cx_next_idx];
1164 sc->cpu_cx_stats[cx_next_idx]++;
1165 KASSERT(cx_next->type != ACPI_STATE_C0, ("acpi_cpu_idle: C0 sleep"));
1166
1167 /*
1168 * Execute HLT (or equivalent) and wait for an interrupt. We can't
1169 * precisely calculate the time spent in C1 since the place we wake up
1170 * is an ISR. Assume we slept no more then half of quantum, unless
1171 * we are called inside critical section, delaying context switch.
1172 */
1173 if (cx_next->type == ACPI_STATE_C1) {
1174 cputicks = cpu_ticks();
1175 if (cx_next->p_lvlx != NULL) {
1176 /* C1 I/O then Halt */
1177 CPU_GET_REG(cx_next->p_lvlx, 1);
1178 }
1179 if (cx_next->do_mwait)
1180 acpi_cpu_idle_mwait(cx_next->mwait_hint);
1181 else
1182 acpi_cpu_c1();
1183 end_time = ((cpu_ticks() - cputicks) << 20) / cpu_tickrate();
1184 if (curthread->td_critnest == 0)
1185 end_time = min(end_time, 500000 / hz);
1186 /* acpi_cpu_c1() returns with interrupts enabled. */
1187 if (cx_next->do_mwait)
1188 ACPI_ENABLE_IRQS();
1189 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + end_time) / 4;
1190 return;
1191 }
1192
1193 /*
1194 * For C3, disable bus master arbitration and enable bus master wake
1195 * if BM control is available, otherwise flush the CPU cache.
1196 */
1197 if (cx_next->type == ACPI_STATE_C3 || cx_next->mwait_bm_avoidance) {
1198 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) {
1199 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 1);
1200 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1);
1201 } else
1202 ACPI_FLUSH_CPU_CACHE();
1203 }
1204
1205 /*
1206 * Read from P_LVLx to enter C2(+), checking time spent asleep.
1207 * Use the ACPI timer for measuring sleep time. Since we need to
1208 * get the time very close to the CPU start/stop clock logic, this
1209 * is the only reliable time source.
1210 */
1211 if (cx_next->type == ACPI_STATE_C3) {
1212 AcpiGetTimer(&start_time);
1213 cputicks = 0;
1214 } else {
1215 start_time = 0;
1216 cputicks = cpu_ticks();
1217 }
1218 if (cx_next->do_mwait)
1219 acpi_cpu_idle_mwait(cx_next->mwait_hint);
1220 else
1221 CPU_GET_REG(cx_next->p_lvlx, 1);
1222
1223 /*
1224 * Read the end time twice. Since it may take an arbitrary time
1225 * to enter the idle state, the first read may be executed before
1226 * the processor has stopped. Doing it again provides enough
1227 * margin that we are certain to have a correct value.
1228 */
1229 AcpiGetTimer(&end_time);
1230 if (cx_next->type == ACPI_STATE_C3) {
1231 AcpiGetTimer(&end_time);
1232 AcpiGetTimerDuration(start_time, end_time, &end_time);
1233 } else
1234 end_time = ((cpu_ticks() - cputicks) << 20) / cpu_tickrate();
1235
1236 /* Enable bus master arbitration and disable bus master wakeup. */
1237 if ((cx_next->type == ACPI_STATE_C3 || cx_next->mwait_bm_avoidance) &&
1238 (cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) {
1239 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 0);
1240 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0);
1241 }
1242 ACPI_ENABLE_IRQS();
1243
1244 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + PM_USEC(end_time)) / 4;
1245 }
1246 #endif
1247
1248 /*
1249 * Re-evaluate the _CST object when we are notified that it changed.
1250 */
1251 static void
1252 acpi_cpu_notify(ACPI_HANDLE h, UINT32 notify, void *context)
1253 {
1254 struct acpi_cpu_softc *sc = (struct acpi_cpu_softc *)context;
1255
1256 if (notify != ACPI_NOTIFY_CX_STATES)
1257 return;
1258
1259 /*
1260 * C-state data for target CPU is going to be in flux while we execute
1261 * acpi_cpu_cx_cst, so disable entering acpi_cpu_idle.
1262 * Also, it may happen that multiple ACPI taskqueues may concurrently
1263 * execute notifications for the same CPU. ACPI_SERIAL is used to
1264 * protect against that.
1265 */
1266 ACPI_SERIAL_BEGIN(cpu);
1267 disable_idle(sc);
1268
1269 /* Update the list of Cx states. */
1270 acpi_cpu_cx_cst(sc);
1271 acpi_cpu_cx_list(sc);
1272 acpi_cpu_set_cx_lowest(sc);
1273
1274 enable_idle(sc);
1275 ACPI_SERIAL_END(cpu);
1276
1277 acpi_UserNotify("PROCESSOR", sc->cpu_handle, notify);
1278 }
1279
1280 static void
1281 acpi_cpu_quirks(void)
1282 {
1283 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
1284
1285 /*
1286 * Bus mastering arbitration control is needed to keep caches coherent
1287 * while sleeping in C3. If it's not present but a working flush cache
1288 * instruction is present, flush the caches before entering C3 instead.
1289 * Otherwise, just disable C3 completely.
1290 */
1291 if (AcpiGbl_FADT.Pm2ControlBlock == 0 ||
1292 AcpiGbl_FADT.Pm2ControlLength == 0) {
1293 if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD) &&
1294 (AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD_FLUSH) == 0) {
1295 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL;
1296 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1297 "acpi_cpu: no BM control, using flush cache method\n"));
1298 } else {
1299 cpu_quirks |= CPU_QUIRK_NO_C3;
1300 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1301 "acpi_cpu: no BM control, C3 not available\n"));
1302 }
1303 }
1304
1305 /*
1306 * If we are using generic Cx mode, C3 on multiple CPUs requires using
1307 * the expensive flush cache instruction.
1308 */
1309 if (cpu_cx_generic && mp_ncpus > 1) {
1310 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL;
1311 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1312 "acpi_cpu: SMP, using flush cache mode for C3\n"));
1313 }
1314
1315 /* Look for various quirks of the PIIX4 part. */
1316 acpi_cpu_quirks_piix4();
1317 }
1318
1319 static void
1320 acpi_cpu_quirks_piix4(void)
1321 {
1322 #ifdef __i386__
1323 device_t acpi_dev;
1324 uint32_t val;
1325 ACPI_STATUS status;
1326
1327 acpi_dev = pci_find_device(PCI_VENDOR_INTEL, PCI_DEVICE_82371AB_3);
1328 if (acpi_dev != NULL) {
1329 switch (pci_get_revid(acpi_dev)) {
1330 /*
1331 * Disable C3 support for all PIIX4 chipsets. Some of these parts
1332 * do not report the BMIDE status to the BM status register and
1333 * others have a livelock bug if Type-F DMA is enabled. Linux
1334 * works around the BMIDE bug by reading the BM status directly
1335 * but we take the simpler approach of disabling C3 for these
1336 * parts.
1337 *
1338 * See erratum #18 ("C3 Power State/BMIDE and Type-F DMA
1339 * Livelock") from the January 2002 PIIX4 specification update.
1340 * Applies to all PIIX4 models.
1341 *
1342 * Also, make sure that all interrupts cause a "Stop Break"
1343 * event to exit from C2 state.
1344 * Also, BRLD_EN_BM (ACPI_BITREG_BUS_MASTER_RLD in ACPI-speak)
1345 * should be set to zero, otherwise it causes C2 to short-sleep.
1346 * PIIX4 doesn't properly support C3 and bus master activity
1347 * need not break out of C2.
1348 */
1349 case PCI_REVISION_A_STEP:
1350 case PCI_REVISION_B_STEP:
1351 case PCI_REVISION_4E:
1352 case PCI_REVISION_4M:
1353 cpu_quirks |= CPU_QUIRK_NO_C3;
1354 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1355 "acpi_cpu: working around PIIX4 bug, disabling C3\n"));
1356
1357 val = pci_read_config(acpi_dev, PIIX4_DEVACTB_REG, 4);
1358 if ((val & PIIX4_STOP_BREAK_MASK) != PIIX4_STOP_BREAK_MASK) {
1359 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1360 "acpi_cpu: PIIX4: enabling IRQs to generate Stop Break\n"));
1361 val |= PIIX4_STOP_BREAK_MASK;
1362 pci_write_config(acpi_dev, PIIX4_DEVACTB_REG, val, 4);
1363 }
1364 status = AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_RLD, &val);
1365 if (ACPI_SUCCESS(status) && val != 0) {
1366 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1367 "acpi_cpu: PIIX4: reset BRLD_EN_BM\n"));
1368 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0);
1369 }
1370 break;
1371 default:
1372 break;
1373 }
1374 }
1375 #endif
1376 }
1377
1378 static int
1379 acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS)
1380 {
1381 struct acpi_cpu_softc *sc;
1382 struct sbuf sb;
1383 char buf[128];
1384 int i;
1385 uintmax_t fract, sum, whole;
1386
1387 sc = (struct acpi_cpu_softc *) arg1;
1388 sum = 0;
1389 for (i = 0; i < sc->cpu_cx_count; i++)
1390 sum += sc->cpu_cx_stats[i];
1391 sbuf_new(&sb, buf, sizeof(buf), SBUF_FIXEDLEN);
1392 for (i = 0; i < sc->cpu_cx_count; i++) {
1393 if (sum > 0) {
1394 whole = (uintmax_t)sc->cpu_cx_stats[i] * 100;
1395 fract = (whole % sum) * 100;
1396 sbuf_printf(&sb, "%u.%02u%% ", (u_int)(whole / sum),
1397 (u_int)(fract / sum));
1398 } else
1399 sbuf_printf(&sb, "0.00%% ");
1400 }
1401 sbuf_printf(&sb, "last %dus", sc->cpu_prev_sleep);
1402 sbuf_trim(&sb);
1403 sbuf_finish(&sb);
1404 sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
1405 sbuf_delete(&sb);
1406
1407 return (0);
1408 }
1409
1410 /*
1411 * XXX TODO: actually add support to count each entry/exit
1412 * from the Cx states.
1413 */
1414 static int
1415 acpi_cpu_usage_counters_sysctl(SYSCTL_HANDLER_ARGS)
1416 {
1417 struct acpi_cpu_softc *sc;
1418 struct sbuf sb;
1419 char buf[128];
1420 int i;
1421
1422 sc = (struct acpi_cpu_softc *) arg1;
1423
1424 /* Print out the raw counters */
1425 sbuf_new(&sb, buf, sizeof(buf), SBUF_FIXEDLEN);
1426
1427 for (i = 0; i < sc->cpu_cx_count; i++) {
1428 sbuf_printf(&sb, "%u ", sc->cpu_cx_stats[i]);
1429 }
1430
1431 sbuf_trim(&sb);
1432 sbuf_finish(&sb);
1433 sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
1434 sbuf_delete(&sb);
1435
1436 return (0);
1437 }
1438
1439 #if defined(__i386__) || defined(__amd64__)
1440 static int
1441 acpi_cpu_method_sysctl(SYSCTL_HANDLER_ARGS)
1442 {
1443 struct acpi_cpu_softc *sc;
1444 struct acpi_cx *cx;
1445 struct sbuf sb;
1446 char buf[128];
1447 int i;
1448
1449 sc = (struct acpi_cpu_softc *)arg1;
1450 sbuf_new(&sb, buf, sizeof(buf), SBUF_FIXEDLEN);
1451 for (i = 0; i < sc->cpu_cx_count; i++) {
1452 cx = &sc->cpu_cx_states[i];
1453 sbuf_printf(&sb, "C%d/", i + 1);
1454 if (cx->do_mwait) {
1455 sbuf_cat(&sb, "mwait");
1456 if (cx->mwait_hw_coord)
1457 sbuf_cat(&sb, "/hwc");
1458 if (cx->mwait_bm_avoidance)
1459 sbuf_cat(&sb, "/bma");
1460 } else if (cx->type == ACPI_STATE_C1) {
1461 sbuf_cat(&sb, "hlt");
1462 } else {
1463 sbuf_cat(&sb, "io");
1464 }
1465 if (cx->type == ACPI_STATE_C1 && cx->p_lvlx != NULL)
1466 sbuf_cat(&sb, "/iohlt");
1467 sbuf_putc(&sb, ' ');
1468 }
1469 sbuf_trim(&sb);
1470 sbuf_finish(&sb);
1471 sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
1472 sbuf_delete(&sb);
1473 return (0);
1474 }
1475 #endif
1476
1477 static int
1478 acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc)
1479 {
1480 int i;
1481
1482 ACPI_SERIAL_ASSERT(cpu);
1483 sc->cpu_cx_lowest = min(sc->cpu_cx_lowest_lim, sc->cpu_cx_count - 1);
1484
1485 /* If not disabling, cache the new lowest non-C3 state. */
1486 sc->cpu_non_c3 = 0;
1487 for (i = sc->cpu_cx_lowest; i >= 0; i--) {
1488 if (sc->cpu_cx_states[i].type < ACPI_STATE_C3) {
1489 sc->cpu_non_c3 = i;
1490 break;
1491 }
1492 }
1493
1494 /* Reset the statistics counters. */
1495 bzero(sc->cpu_cx_stats, sizeof(sc->cpu_cx_stats));
1496 return (0);
1497 }
1498
1499 static int
1500 acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS)
1501 {
1502 struct acpi_cpu_softc *sc;
1503 char state[8];
1504 int val, error;
1505
1506 sc = (struct acpi_cpu_softc *) arg1;
1507 snprintf(state, sizeof(state), "C%d", sc->cpu_cx_lowest_lim + 1);
1508 error = sysctl_handle_string(oidp, state, sizeof(state), req);
1509 if (error != 0 || req->newptr == NULL)
1510 return (error);
1511 if (strlen(state) < 2 || toupper(state[0]) != 'C')
1512 return (EINVAL);
1513 if (strcasecmp(state, "Cmax") == 0)
1514 val = MAX_CX_STATES;
1515 else {
1516 val = (int) strtol(state + 1, NULL, 10);
1517 if (val < 1 || val > MAX_CX_STATES)
1518 return (EINVAL);
1519 }
1520
1521 ACPI_SERIAL_BEGIN(cpu);
1522 sc->cpu_cx_lowest_lim = val - 1;
1523 acpi_cpu_set_cx_lowest(sc);
1524 ACPI_SERIAL_END(cpu);
1525
1526 return (0);
1527 }
1528
1529 static int
1530 acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS)
1531 {
1532 struct acpi_cpu_softc *sc;
1533 char state[8];
1534 int val, error, i;
1535
1536 snprintf(state, sizeof(state), "C%d", cpu_cx_lowest_lim + 1);
1537 error = sysctl_handle_string(oidp, state, sizeof(state), req);
1538 if (error != 0 || req->newptr == NULL)
1539 return (error);
1540 if (strlen(state) < 2 || toupper(state[0]) != 'C')
1541 return (EINVAL);
1542 if (strcasecmp(state, "Cmax") == 0)
1543 val = MAX_CX_STATES;
1544 else {
1545 val = (int) strtol(state + 1, NULL, 10);
1546 if (val < 1 || val > MAX_CX_STATES)
1547 return (EINVAL);
1548 }
1549
1550 /* Update the new lowest useable Cx state for all CPUs. */
1551 ACPI_SERIAL_BEGIN(cpu);
1552 cpu_cx_lowest_lim = val - 1;
1553 for (i = 0; i < cpu_ndevices; i++) {
1554 sc = device_get_softc(cpu_devices[i]);
1555 sc->cpu_cx_lowest_lim = cpu_cx_lowest_lim;
1556 acpi_cpu_set_cx_lowest(sc);
1557 }
1558 ACPI_SERIAL_END(cpu);
1559
1560 return (0);
1561 }
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