1 /*-
2 * Copyright (c) 2003-2005 Nate Lawson (SDG)
3 * Copyright (c) 2001 Michael Smith
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD: releng/9.0/sys/dev/acpica/acpi_cpu.c 223527 2011-06-25 02:49:47Z marcel $");
30
31 #include "opt_acpi.h"
32 #include <sys/param.h>
33 #include <sys/bus.h>
34 #include <sys/cpu.h>
35 #include <sys/kernel.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/pcpu.h>
39 #include <sys/power.h>
40 #include <sys/proc.h>
41 #include <sys/sbuf.h>
42 #include <sys/smp.h>
43
44 #include <dev/pci/pcivar.h>
45 #include <machine/atomic.h>
46 #include <machine/bus.h>
47 #if defined(__amd64__) || defined(__i386__)
48 #include <machine/clock.h>
49 #endif
50 #include <sys/rman.h>
51
52 #include <contrib/dev/acpica/include/acpi.h>
53 #include <contrib/dev/acpica/include/accommon.h>
54
55 #include <dev/acpica/acpivar.h>
56
57 /*
58 * Support for ACPI Processor devices, including C[1-3] sleep states.
59 */
60
61 /* Hooks for the ACPI CA debugging infrastructure */
62 #define _COMPONENT ACPI_PROCESSOR
63 ACPI_MODULE_NAME("PROCESSOR")
64
65 struct acpi_cx {
66 struct resource *p_lvlx; /* Register to read to enter state. */
67 uint32_t type; /* C1-3 (C4 and up treated as C3). */
68 uint32_t trans_lat; /* Transition latency (usec). */
69 uint32_t power; /* Power consumed (mW). */
70 int res_type; /* Resource type for p_lvlx. */
71 };
72 #define MAX_CX_STATES 8
73
74 struct acpi_cpu_softc {
75 device_t cpu_dev;
76 ACPI_HANDLE cpu_handle;
77 struct pcpu *cpu_pcpu;
78 uint32_t cpu_acpi_id; /* ACPI processor id */
79 uint32_t cpu_p_blk; /* ACPI P_BLK location */
80 uint32_t cpu_p_blk_len; /* P_BLK length (must be 6). */
81 struct acpi_cx cpu_cx_states[MAX_CX_STATES];
82 int cpu_cx_count; /* Number of valid Cx states. */
83 int cpu_prev_sleep;/* Last idle sleep duration. */
84 int cpu_features; /* Child driver supported features. */
85 /* Runtime state. */
86 int cpu_non_c3; /* Index of lowest non-C3 state. */
87 u_int cpu_cx_stats[MAX_CX_STATES];/* Cx usage history. */
88 /* Values for sysctl. */
89 struct sysctl_ctx_list cpu_sysctl_ctx;
90 struct sysctl_oid *cpu_sysctl_tree;
91 int cpu_cx_lowest;
92 char cpu_cx_supported[64];
93 int cpu_rid;
94 };
95
96 struct acpi_cpu_device {
97 struct resource_list ad_rl;
98 };
99
100 #define CPU_GET_REG(reg, width) \
101 (bus_space_read_ ## width(rman_get_bustag((reg)), \
102 rman_get_bushandle((reg)), 0))
103 #define CPU_SET_REG(reg, width, val) \
104 (bus_space_write_ ## width(rman_get_bustag((reg)), \
105 rman_get_bushandle((reg)), 0, (val)))
106
107 #define PM_USEC(x) ((x) >> 2) /* ~4 clocks per usec (3.57955 Mhz) */
108
109 #define ACPI_NOTIFY_CX_STATES 0x81 /* _CST changed. */
110
111 #define CPU_QUIRK_NO_C3 (1<<0) /* C3-type states are not usable. */
112 #define CPU_QUIRK_NO_BM_CTRL (1<<2) /* No bus mastering control. */
113
114 #define PCI_VENDOR_INTEL 0x8086
115 #define PCI_DEVICE_82371AB_3 0x7113 /* PIIX4 chipset for quirks. */
116 #define PCI_REVISION_A_STEP 0
117 #define PCI_REVISION_B_STEP 1
118 #define PCI_REVISION_4E 2
119 #define PCI_REVISION_4M 3
120 #define PIIX4_DEVACTB_REG 0x58
121 #define PIIX4_BRLD_EN_IRQ0 (1<<0)
122 #define PIIX4_BRLD_EN_IRQ (1<<1)
123 #define PIIX4_BRLD_EN_IRQ8 (1<<5)
124 #define PIIX4_STOP_BREAK_MASK (PIIX4_BRLD_EN_IRQ0 | PIIX4_BRLD_EN_IRQ | PIIX4_BRLD_EN_IRQ8)
125 #define PIIX4_PCNTRL_BST_EN (1<<10)
126
127 /* Platform hardware resource information. */
128 static uint32_t cpu_smi_cmd; /* Value to write to SMI_CMD. */
129 static uint8_t cpu_cst_cnt; /* Indicate we are _CST aware. */
130 static int cpu_quirks; /* Indicate any hardware bugs. */
131
132 /* Runtime state. */
133 static int cpu_disable_idle; /* Disable entry to idle function */
134 static int cpu_cx_count; /* Number of valid Cx states */
135
136 /* Values for sysctl. */
137 static struct sysctl_ctx_list cpu_sysctl_ctx;
138 static struct sysctl_oid *cpu_sysctl_tree;
139 static int cpu_cx_generic;
140 static int cpu_cx_lowest;
141
142 static device_t *cpu_devices;
143 static int cpu_ndevices;
144 static struct acpi_cpu_softc **cpu_softc;
145 ACPI_SERIAL_DECL(cpu, "ACPI CPU");
146
147 static int acpi_cpu_probe(device_t dev);
148 static int acpi_cpu_attach(device_t dev);
149 static int acpi_cpu_suspend(device_t dev);
150 static int acpi_cpu_resume(device_t dev);
151 static int acpi_pcpu_get_id(uint32_t idx, uint32_t *acpi_id,
152 uint32_t *cpu_id);
153 static struct resource_list *acpi_cpu_get_rlist(device_t dev, device_t child);
154 static device_t acpi_cpu_add_child(device_t dev, u_int order, const char *name,
155 int unit);
156 static int acpi_cpu_read_ivar(device_t dev, device_t child, int index,
157 uintptr_t *result);
158 static int acpi_cpu_shutdown(device_t dev);
159 static void acpi_cpu_cx_probe(struct acpi_cpu_softc *sc);
160 static void acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc);
161 static int acpi_cpu_cx_cst(struct acpi_cpu_softc *sc);
162 static void acpi_cpu_startup(void *arg);
163 static void acpi_cpu_startup_cx(struct acpi_cpu_softc *sc);
164 static void acpi_cpu_cx_list(struct acpi_cpu_softc *sc);
165 static void acpi_cpu_idle(void);
166 static void acpi_cpu_notify(ACPI_HANDLE h, UINT32 notify, void *context);
167 static int acpi_cpu_quirks(void);
168 static int acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS);
169 static int acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc, int val);
170 static int acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS);
171 static int acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS);
172
173 static device_method_t acpi_cpu_methods[] = {
174 /* Device interface */
175 DEVMETHOD(device_probe, acpi_cpu_probe),
176 DEVMETHOD(device_attach, acpi_cpu_attach),
177 DEVMETHOD(device_detach, bus_generic_detach),
178 DEVMETHOD(device_shutdown, acpi_cpu_shutdown),
179 DEVMETHOD(device_suspend, acpi_cpu_suspend),
180 DEVMETHOD(device_resume, acpi_cpu_resume),
181
182 /* Bus interface */
183 DEVMETHOD(bus_add_child, acpi_cpu_add_child),
184 DEVMETHOD(bus_read_ivar, acpi_cpu_read_ivar),
185 DEVMETHOD(bus_get_resource_list, acpi_cpu_get_rlist),
186 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
187 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
188 DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource),
189 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
190 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
191 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
192 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
193 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
194 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
195
196 {0, 0}
197 };
198
199 static driver_t acpi_cpu_driver = {
200 "cpu",
201 acpi_cpu_methods,
202 sizeof(struct acpi_cpu_softc),
203 };
204
205 static devclass_t acpi_cpu_devclass;
206 DRIVER_MODULE(cpu, acpi, acpi_cpu_driver, acpi_cpu_devclass, 0, 0);
207 MODULE_DEPEND(cpu, acpi, 1, 1, 1);
208
209 static int
210 acpi_cpu_probe(device_t dev)
211 {
212 int acpi_id, cpu_id;
213 ACPI_BUFFER buf;
214 ACPI_HANDLE handle;
215 ACPI_OBJECT *obj;
216 ACPI_STATUS status;
217
218 if (acpi_disabled("cpu") || acpi_get_type(dev) != ACPI_TYPE_PROCESSOR)
219 return (ENXIO);
220
221 handle = acpi_get_handle(dev);
222 if (cpu_softc == NULL)
223 cpu_softc = malloc(sizeof(struct acpi_cpu_softc *) *
224 (mp_maxid + 1), M_TEMP /* XXX */, M_WAITOK | M_ZERO);
225
226 /* Get our Processor object. */
227 buf.Pointer = NULL;
228 buf.Length = ACPI_ALLOCATE_BUFFER;
229 status = AcpiEvaluateObject(handle, NULL, NULL, &buf);
230 if (ACPI_FAILURE(status)) {
231 device_printf(dev, "probe failed to get Processor obj - %s\n",
232 AcpiFormatException(status));
233 return (ENXIO);
234 }
235 obj = (ACPI_OBJECT *)buf.Pointer;
236 if (obj->Type != ACPI_TYPE_PROCESSOR) {
237 device_printf(dev, "Processor object has bad type %d\n", obj->Type);
238 AcpiOsFree(obj);
239 return (ENXIO);
240 }
241
242 /*
243 * Find the processor associated with our unit. We could use the
244 * ProcId as a key, however, some boxes do not have the same values
245 * in their Processor object as the ProcId values in the MADT.
246 */
247 acpi_id = obj->Processor.ProcId;
248 AcpiOsFree(obj);
249 if (acpi_pcpu_get_id(device_get_unit(dev), &acpi_id, &cpu_id) != 0)
250 return (ENXIO);
251
252 /*
253 * Check if we already probed this processor. We scan the bus twice
254 * so it's possible we've already seen this one.
255 */
256 if (cpu_softc[cpu_id] != NULL)
257 return (ENXIO);
258
259 /* Mark this processor as in-use and save our derived id for attach. */
260 cpu_softc[cpu_id] = (void *)1;
261 acpi_set_private(dev, (void*)(intptr_t)cpu_id);
262 device_set_desc(dev, "ACPI CPU");
263
264 return (0);
265 }
266
267 static int
268 acpi_cpu_attach(device_t dev)
269 {
270 ACPI_BUFFER buf;
271 ACPI_OBJECT arg[4], *obj;
272 ACPI_OBJECT_LIST arglist;
273 struct pcpu *pcpu_data;
274 struct acpi_cpu_softc *sc;
275 struct acpi_softc *acpi_sc;
276 ACPI_STATUS status;
277 u_int features;
278 int cpu_id, drv_count, i;
279 driver_t **drivers;
280 uint32_t cap_set[3];
281
282 /* UUID needed by _OSC evaluation */
283 static uint8_t cpu_oscuuid[16] = { 0x16, 0xA6, 0x77, 0x40, 0x0C, 0x29,
284 0xBE, 0x47, 0x9E, 0xBD, 0xD8, 0x70,
285 0x58, 0x71, 0x39, 0x53 };
286
287 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
288
289 sc = device_get_softc(dev);
290 sc->cpu_dev = dev;
291 sc->cpu_handle = acpi_get_handle(dev);
292 cpu_id = (int)(intptr_t)acpi_get_private(dev);
293 cpu_softc[cpu_id] = sc;
294 pcpu_data = pcpu_find(cpu_id);
295 pcpu_data->pc_device = dev;
296 sc->cpu_pcpu = pcpu_data;
297 cpu_smi_cmd = AcpiGbl_FADT.SmiCommand;
298 cpu_cst_cnt = AcpiGbl_FADT.CstControl;
299
300 buf.Pointer = NULL;
301 buf.Length = ACPI_ALLOCATE_BUFFER;
302 status = AcpiEvaluateObject(sc->cpu_handle, NULL, NULL, &buf);
303 if (ACPI_FAILURE(status)) {
304 device_printf(dev, "attach failed to get Processor obj - %s\n",
305 AcpiFormatException(status));
306 return (ENXIO);
307 }
308 obj = (ACPI_OBJECT *)buf.Pointer;
309 sc->cpu_p_blk = obj->Processor.PblkAddress;
310 sc->cpu_p_blk_len = obj->Processor.PblkLength;
311 sc->cpu_acpi_id = obj->Processor.ProcId;
312 AcpiOsFree(obj);
313 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "acpi_cpu%d: P_BLK at %#x/%d\n",
314 device_get_unit(dev), sc->cpu_p_blk, sc->cpu_p_blk_len));
315
316 /*
317 * If this is the first cpu we attach, create and initialize the generic
318 * resources that will be used by all acpi cpu devices.
319 */
320 if (device_get_unit(dev) == 0) {
321 /* Assume we won't be using generic Cx mode by default */
322 cpu_cx_generic = FALSE;
323
324 /* Install hw.acpi.cpu sysctl tree */
325 acpi_sc = acpi_device_get_parent_softc(dev);
326 sysctl_ctx_init(&cpu_sysctl_ctx);
327 cpu_sysctl_tree = SYSCTL_ADD_NODE(&cpu_sysctl_ctx,
328 SYSCTL_CHILDREN(acpi_sc->acpi_sysctl_tree), OID_AUTO, "cpu",
329 CTLFLAG_RD, 0, "node for CPU children");
330
331 /* Queue post cpu-probing task handler */
332 AcpiOsExecute(OSL_NOTIFY_HANDLER, acpi_cpu_startup, NULL);
333 }
334
335 /*
336 * Before calling any CPU methods, collect child driver feature hints
337 * and notify ACPI of them. We support unified SMP power control
338 * so advertise this ourselves. Note this is not the same as independent
339 * SMP control where each CPU can have different settings.
340 */
341 sc->cpu_features = ACPI_CAP_SMP_SAME | ACPI_CAP_SMP_SAME_C3;
342 if (devclass_get_drivers(acpi_cpu_devclass, &drivers, &drv_count) == 0) {
343 for (i = 0; i < drv_count; i++) {
344 if (ACPI_GET_FEATURES(drivers[i], &features) == 0)
345 sc->cpu_features |= features;
346 }
347 free(drivers, M_TEMP);
348 }
349
350 /*
351 * CPU capabilities are specified in
352 * Intel Processor Vendor-Specific ACPI Interface Specification.
353 */
354 if (sc->cpu_features) {
355 arglist.Pointer = arg;
356 arglist.Count = 4;
357 arg[0].Type = ACPI_TYPE_BUFFER;
358 arg[0].Buffer.Length = sizeof(cpu_oscuuid);
359 arg[0].Buffer.Pointer = cpu_oscuuid; /* UUID */
360 arg[1].Type = ACPI_TYPE_INTEGER;
361 arg[1].Integer.Value = 1; /* revision */
362 arg[2].Type = ACPI_TYPE_INTEGER;
363 arg[2].Integer.Value = 1; /* count */
364 arg[3].Type = ACPI_TYPE_BUFFER;
365 arg[3].Buffer.Length = sizeof(cap_set); /* Capabilities buffer */
366 arg[3].Buffer.Pointer = (uint8_t *)cap_set;
367 cap_set[0] = 0; /* status */
368 cap_set[1] = sc->cpu_features;
369 status = AcpiEvaluateObject(sc->cpu_handle, "_OSC", &arglist, NULL);
370 if (ACPI_SUCCESS(status)) {
371 if (cap_set[0] != 0)
372 device_printf(dev, "_OSC returned status %#x\n", cap_set[0]);
373 }
374 else {
375 arglist.Pointer = arg;
376 arglist.Count = 1;
377 arg[0].Type = ACPI_TYPE_BUFFER;
378 arg[0].Buffer.Length = sizeof(cap_set);
379 arg[0].Buffer.Pointer = (uint8_t *)cap_set;
380 cap_set[0] = 1; /* revision */
381 cap_set[1] = 1; /* number of capabilities integers */
382 cap_set[2] = sc->cpu_features;
383 AcpiEvaluateObject(sc->cpu_handle, "_PDC", &arglist, NULL);
384 }
385 }
386
387 /* Probe for Cx state support. */
388 acpi_cpu_cx_probe(sc);
389
390 return (0);
391 }
392
393 static void
394 acpi_cpu_postattach(void *unused __unused)
395 {
396 device_t *devices;
397 int err;
398 int i, n;
399
400 err = devclass_get_devices(acpi_cpu_devclass, &devices, &n);
401 if (err != 0) {
402 printf("devclass_get_devices(acpi_cpu_devclass) failed\n");
403 return;
404 }
405 for (i = 0; i < n; i++)
406 bus_generic_probe(devices[i]);
407 for (i = 0; i < n; i++)
408 bus_generic_attach(devices[i]);
409 free(devices, M_TEMP);
410 }
411
412 SYSINIT(acpi_cpu, SI_SUB_CONFIGURE, SI_ORDER_MIDDLE,
413 acpi_cpu_postattach, NULL);
414
415 /*
416 * Disable any entry to the idle function during suspend and re-enable it
417 * during resume.
418 */
419 static int
420 acpi_cpu_suspend(device_t dev)
421 {
422 int error;
423
424 error = bus_generic_suspend(dev);
425 if (error)
426 return (error);
427 cpu_disable_idle = TRUE;
428 return (0);
429 }
430
431 static int
432 acpi_cpu_resume(device_t dev)
433 {
434
435 cpu_disable_idle = FALSE;
436 return (bus_generic_resume(dev));
437 }
438
439 /*
440 * Find the nth present CPU and return its pc_cpuid as well as set the
441 * pc_acpi_id from the most reliable source.
442 */
443 static int
444 acpi_pcpu_get_id(uint32_t idx, uint32_t *acpi_id, uint32_t *cpu_id)
445 {
446 struct pcpu *pcpu_data;
447 uint32_t i;
448
449 KASSERT(acpi_id != NULL, ("Null acpi_id"));
450 KASSERT(cpu_id != NULL, ("Null cpu_id"));
451 CPU_FOREACH(i) {
452 pcpu_data = pcpu_find(i);
453 KASSERT(pcpu_data != NULL, ("no pcpu data for %d", i));
454 if (idx-- == 0) {
455 /*
456 * If pc_acpi_id was not initialized (e.g., a non-APIC UP box)
457 * override it with the value from the ASL. Otherwise, if the
458 * two don't match, prefer the MADT-derived value. Finally,
459 * return the pc_cpuid to reference this processor.
460 */
461 if (pcpu_data->pc_acpi_id == 0xffffffff)
462 pcpu_data->pc_acpi_id = *acpi_id;
463 else if (pcpu_data->pc_acpi_id != *acpi_id)
464 *acpi_id = pcpu_data->pc_acpi_id;
465 *cpu_id = pcpu_data->pc_cpuid;
466 return (0);
467 }
468 }
469
470 return (ESRCH);
471 }
472
473 static struct resource_list *
474 acpi_cpu_get_rlist(device_t dev, device_t child)
475 {
476 struct acpi_cpu_device *ad;
477
478 ad = device_get_ivars(child);
479 if (ad == NULL)
480 return (NULL);
481 return (&ad->ad_rl);
482 }
483
484 static device_t
485 acpi_cpu_add_child(device_t dev, u_int order, const char *name, int unit)
486 {
487 struct acpi_cpu_device *ad;
488 device_t child;
489
490 if ((ad = malloc(sizeof(*ad), M_TEMP, M_NOWAIT | M_ZERO)) == NULL)
491 return (NULL);
492
493 resource_list_init(&ad->ad_rl);
494
495 child = device_add_child_ordered(dev, order, name, unit);
496 if (child != NULL)
497 device_set_ivars(child, ad);
498 else
499 free(ad, M_TEMP);
500 return (child);
501 }
502
503 static int
504 acpi_cpu_read_ivar(device_t dev, device_t child, int index, uintptr_t *result)
505 {
506 struct acpi_cpu_softc *sc;
507
508 sc = device_get_softc(dev);
509 switch (index) {
510 case ACPI_IVAR_HANDLE:
511 *result = (uintptr_t)sc->cpu_handle;
512 break;
513 case CPU_IVAR_PCPU:
514 *result = (uintptr_t)sc->cpu_pcpu;
515 break;
516 #if defined(__amd64__) || defined(__i386__)
517 case CPU_IVAR_NOMINAL_MHZ:
518 if (tsc_is_invariant) {
519 *result = (uintptr_t)(atomic_load_acq_64(&tsc_freq) / 1000000);
520 break;
521 }
522 /* FALLTHROUGH */
523 #endif
524 default:
525 return (ENOENT);
526 }
527 return (0);
528 }
529
530 static int
531 acpi_cpu_shutdown(device_t dev)
532 {
533 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
534
535 /* Allow children to shutdown first. */
536 bus_generic_shutdown(dev);
537
538 /*
539 * Disable any entry to the idle function. There is a small race where
540 * an idle thread have passed this check but not gone to sleep. This
541 * is ok since device_shutdown() does not free the softc, otherwise
542 * we'd have to be sure all threads were evicted before returning.
543 */
544 cpu_disable_idle = TRUE;
545
546 return_VALUE (0);
547 }
548
549 static void
550 acpi_cpu_cx_probe(struct acpi_cpu_softc *sc)
551 {
552 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
553
554 /* Use initial sleep value of 1 sec. to start with lowest idle state. */
555 sc->cpu_prev_sleep = 1000000;
556 sc->cpu_cx_lowest = 0;
557
558 /*
559 * Check for the ACPI 2.0 _CST sleep states object. If we can't find
560 * any, we'll revert to generic FADT/P_BLK Cx control method which will
561 * be handled by acpi_cpu_startup. We need to defer to after having
562 * probed all the cpus in the system before probing for generic Cx
563 * states as we may already have found cpus with valid _CST packages
564 */
565 if (!cpu_cx_generic && acpi_cpu_cx_cst(sc) != 0) {
566 /*
567 * We were unable to find a _CST package for this cpu or there
568 * was an error parsing it. Switch back to generic mode.
569 */
570 cpu_cx_generic = TRUE;
571 if (bootverbose)
572 device_printf(sc->cpu_dev, "switching to generic Cx mode\n");
573 }
574
575 /*
576 * TODO: _CSD Package should be checked here.
577 */
578 }
579
580 static void
581 acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc)
582 {
583 ACPI_GENERIC_ADDRESS gas;
584 struct acpi_cx *cx_ptr;
585
586 sc->cpu_cx_count = 0;
587 cx_ptr = sc->cpu_cx_states;
588
589 /* Use initial sleep value of 1 sec. to start with lowest idle state. */
590 sc->cpu_prev_sleep = 1000000;
591
592 /* C1 has been required since just after ACPI 1.0 */
593 cx_ptr->type = ACPI_STATE_C1;
594 cx_ptr->trans_lat = 0;
595 cx_ptr++;
596 sc->cpu_cx_count++;
597
598 /*
599 * The spec says P_BLK must be 6 bytes long. However, some systems
600 * use it to indicate a fractional set of features present so we
601 * take 5 as C2. Some may also have a value of 7 to indicate
602 * another C3 but most use _CST for this (as required) and having
603 * "only" C1-C3 is not a hardship.
604 */
605 if (sc->cpu_p_blk_len < 5)
606 return;
607
608 /* Validate and allocate resources for C2 (P_LVL2). */
609 gas.SpaceId = ACPI_ADR_SPACE_SYSTEM_IO;
610 gas.BitWidth = 8;
611 if (AcpiGbl_FADT.C2Latency <= 100) {
612 gas.Address = sc->cpu_p_blk + 4;
613 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &sc->cpu_rid,
614 &gas, &cx_ptr->p_lvlx, RF_SHAREABLE);
615 if (cx_ptr->p_lvlx != NULL) {
616 sc->cpu_rid++;
617 cx_ptr->type = ACPI_STATE_C2;
618 cx_ptr->trans_lat = AcpiGbl_FADT.C2Latency;
619 cx_ptr++;
620 sc->cpu_cx_count++;
621 }
622 }
623 if (sc->cpu_p_blk_len < 6)
624 return;
625
626 /* Validate and allocate resources for C3 (P_LVL3). */
627 if (AcpiGbl_FADT.C3Latency <= 1000 && !(cpu_quirks & CPU_QUIRK_NO_C3)) {
628 gas.Address = sc->cpu_p_blk + 5;
629 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &sc->cpu_rid, &gas,
630 &cx_ptr->p_lvlx, RF_SHAREABLE);
631 if (cx_ptr->p_lvlx != NULL) {
632 sc->cpu_rid++;
633 cx_ptr->type = ACPI_STATE_C3;
634 cx_ptr->trans_lat = AcpiGbl_FADT.C3Latency;
635 cx_ptr++;
636 sc->cpu_cx_count++;
637 }
638 }
639 }
640
641 /*
642 * Parse a _CST package and set up its Cx states. Since the _CST object
643 * can change dynamically, our notify handler may call this function
644 * to clean up and probe the new _CST package.
645 */
646 static int
647 acpi_cpu_cx_cst(struct acpi_cpu_softc *sc)
648 {
649 struct acpi_cx *cx_ptr;
650 ACPI_STATUS status;
651 ACPI_BUFFER buf;
652 ACPI_OBJECT *top;
653 ACPI_OBJECT *pkg;
654 uint32_t count;
655 int i;
656
657 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
658
659 buf.Pointer = NULL;
660 buf.Length = ACPI_ALLOCATE_BUFFER;
661 status = AcpiEvaluateObject(sc->cpu_handle, "_CST", NULL, &buf);
662 if (ACPI_FAILURE(status))
663 return (ENXIO);
664
665 /* _CST is a package with a count and at least one Cx package. */
666 top = (ACPI_OBJECT *)buf.Pointer;
667 if (!ACPI_PKG_VALID(top, 2) || acpi_PkgInt32(top, 0, &count) != 0) {
668 device_printf(sc->cpu_dev, "invalid _CST package\n");
669 AcpiOsFree(buf.Pointer);
670 return (ENXIO);
671 }
672 if (count != top->Package.Count - 1) {
673 device_printf(sc->cpu_dev, "invalid _CST state count (%d != %d)\n",
674 count, top->Package.Count - 1);
675 count = top->Package.Count - 1;
676 }
677 if (count > MAX_CX_STATES) {
678 device_printf(sc->cpu_dev, "_CST has too many states (%d)\n", count);
679 count = MAX_CX_STATES;
680 }
681
682 sc->cpu_non_c3 = 0;
683 sc->cpu_cx_count = 0;
684 cx_ptr = sc->cpu_cx_states;
685
686 /*
687 * C1 has been required since just after ACPI 1.0.
688 * Reserve the first slot for it.
689 */
690 cx_ptr->type = ACPI_STATE_C0;
691 cx_ptr++;
692 sc->cpu_cx_count++;
693
694 /* Set up all valid states. */
695 for (i = 0; i < count; i++) {
696 pkg = &top->Package.Elements[i + 1];
697 if (!ACPI_PKG_VALID(pkg, 4) ||
698 acpi_PkgInt32(pkg, 1, &cx_ptr->type) != 0 ||
699 acpi_PkgInt32(pkg, 2, &cx_ptr->trans_lat) != 0 ||
700 acpi_PkgInt32(pkg, 3, &cx_ptr->power) != 0) {
701
702 device_printf(sc->cpu_dev, "skipping invalid Cx state package\n");
703 continue;
704 }
705
706 /* Validate the state to see if we should use it. */
707 switch (cx_ptr->type) {
708 case ACPI_STATE_C1:
709 if (sc->cpu_cx_states[0].type == ACPI_STATE_C0) {
710 /* This is the first C1 state. Use the reserved slot. */
711 sc->cpu_cx_states[0] = *cx_ptr;
712 } else {
713 sc->cpu_non_c3 = i;
714 cx_ptr++;
715 sc->cpu_cx_count++;
716 }
717 continue;
718 case ACPI_STATE_C2:
719 sc->cpu_non_c3 = i;
720 break;
721 case ACPI_STATE_C3:
722 default:
723 if ((cpu_quirks & CPU_QUIRK_NO_C3) != 0) {
724 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
725 "acpi_cpu%d: C3[%d] not available.\n",
726 device_get_unit(sc->cpu_dev), i));
727 continue;
728 }
729 break;
730 }
731
732 #ifdef notyet
733 /* Free up any previous register. */
734 if (cx_ptr->p_lvlx != NULL) {
735 bus_release_resource(sc->cpu_dev, 0, 0, cx_ptr->p_lvlx);
736 cx_ptr->p_lvlx = NULL;
737 }
738 #endif
739
740 /* Allocate the control register for C2 or C3. */
741 acpi_PkgGas(sc->cpu_dev, pkg, 0, &cx_ptr->res_type, &sc->cpu_rid,
742 &cx_ptr->p_lvlx, RF_SHAREABLE);
743 if (cx_ptr->p_lvlx) {
744 sc->cpu_rid++;
745 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
746 "acpi_cpu%d: Got C%d - %d latency\n",
747 device_get_unit(sc->cpu_dev), cx_ptr->type,
748 cx_ptr->trans_lat));
749 cx_ptr++;
750 sc->cpu_cx_count++;
751 }
752 }
753 AcpiOsFree(buf.Pointer);
754
755 /* If C1 state was not found, we need one now. */
756 cx_ptr = sc->cpu_cx_states;
757 if (cx_ptr->type == ACPI_STATE_C0) {
758 cx_ptr->type = ACPI_STATE_C1;
759 cx_ptr->trans_lat = 0;
760 }
761
762 return (0);
763 }
764
765 /*
766 * Call this *after* all CPUs have been attached.
767 */
768 static void
769 acpi_cpu_startup(void *arg)
770 {
771 struct acpi_cpu_softc *sc;
772 int i;
773
774 /* Get set of CPU devices */
775 devclass_get_devices(acpi_cpu_devclass, &cpu_devices, &cpu_ndevices);
776
777 /*
778 * Setup any quirks that might necessary now that we have probed
779 * all the CPUs
780 */
781 acpi_cpu_quirks();
782
783 cpu_cx_count = 0;
784 if (cpu_cx_generic) {
785 /*
786 * We are using generic Cx mode, probe for available Cx states
787 * for all processors.
788 */
789 for (i = 0; i < cpu_ndevices; i++) {
790 sc = device_get_softc(cpu_devices[i]);
791 acpi_cpu_generic_cx_probe(sc);
792 if (sc->cpu_cx_count > cpu_cx_count)
793 cpu_cx_count = sc->cpu_cx_count;
794 }
795
796 /*
797 * Find the highest Cx state common to all CPUs
798 * in the system, taking quirks into account.
799 */
800 for (i = 0; i < cpu_ndevices; i++) {
801 sc = device_get_softc(cpu_devices[i]);
802 if (sc->cpu_cx_count < cpu_cx_count)
803 cpu_cx_count = sc->cpu_cx_count;
804 }
805 } else {
806 /*
807 * We are using _CST mode, remove C3 state if necessary.
808 * Update the largest Cx state supported in the global cpu_cx_count.
809 * It will be used in the global Cx sysctl handler.
810 * As we now know for sure that we will be using _CST mode
811 * install our notify handler.
812 */
813 for (i = 0; i < cpu_ndevices; i++) {
814 sc = device_get_softc(cpu_devices[i]);
815 if (cpu_quirks & CPU_QUIRK_NO_C3) {
816 sc->cpu_cx_count = sc->cpu_non_c3 + 1;
817 }
818 if (sc->cpu_cx_count > cpu_cx_count)
819 cpu_cx_count = sc->cpu_cx_count;
820 AcpiInstallNotifyHandler(sc->cpu_handle, ACPI_DEVICE_NOTIFY,
821 acpi_cpu_notify, sc);
822 }
823 }
824
825 /* Perform Cx final initialization. */
826 for (i = 0; i < cpu_ndevices; i++) {
827 sc = device_get_softc(cpu_devices[i]);
828 acpi_cpu_startup_cx(sc);
829 }
830
831 /* Add a sysctl handler to handle global Cx lowest setting */
832 SYSCTL_ADD_PROC(&cpu_sysctl_ctx, SYSCTL_CHILDREN(cpu_sysctl_tree),
833 OID_AUTO, "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW,
834 NULL, 0, acpi_cpu_global_cx_lowest_sysctl, "A",
835 "Global lowest Cx sleep state to use");
836
837 /* Take over idling from cpu_idle_default(). */
838 cpu_cx_lowest = 0;
839 cpu_disable_idle = FALSE;
840 cpu_idle_hook = acpi_cpu_idle;
841 }
842
843 static void
844 acpi_cpu_cx_list(struct acpi_cpu_softc *sc)
845 {
846 struct sbuf sb;
847 int i;
848
849 /*
850 * Set up the list of Cx states
851 */
852 sc->cpu_non_c3 = 0;
853 sbuf_new(&sb, sc->cpu_cx_supported, sizeof(sc->cpu_cx_supported),
854 SBUF_FIXEDLEN);
855 for (i = 0; i < sc->cpu_cx_count; i++) {
856 sbuf_printf(&sb, "C%d/%d ", i + 1, sc->cpu_cx_states[i].trans_lat);
857 if (sc->cpu_cx_states[i].type < ACPI_STATE_C3)
858 sc->cpu_non_c3 = i;
859 else
860 cpu_can_deep_sleep = 1;
861 }
862 sbuf_trim(&sb);
863 sbuf_finish(&sb);
864 }
865
866 static void
867 acpi_cpu_startup_cx(struct acpi_cpu_softc *sc)
868 {
869 acpi_cpu_cx_list(sc);
870
871 SYSCTL_ADD_STRING(&sc->cpu_sysctl_ctx,
872 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)),
873 OID_AUTO, "cx_supported", CTLFLAG_RD,
874 sc->cpu_cx_supported, 0,
875 "Cx/microsecond values for supported Cx states");
876 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx,
877 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)),
878 OID_AUTO, "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW,
879 (void *)sc, 0, acpi_cpu_cx_lowest_sysctl, "A",
880 "lowest Cx sleep state to use");
881 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx,
882 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)),
883 OID_AUTO, "cx_usage", CTLTYPE_STRING | CTLFLAG_RD,
884 (void *)sc, 0, acpi_cpu_usage_sysctl, "A",
885 "percent usage for each Cx state");
886
887 #ifdef notyet
888 /* Signal platform that we can handle _CST notification. */
889 if (!cpu_cx_generic && cpu_cst_cnt != 0) {
890 ACPI_LOCK(acpi);
891 AcpiOsWritePort(cpu_smi_cmd, cpu_cst_cnt, 8);
892 ACPI_UNLOCK(acpi);
893 }
894 #endif
895 }
896
897 /*
898 * Idle the CPU in the lowest state possible. This function is called with
899 * interrupts disabled. Note that once it re-enables interrupts, a task
900 * switch can occur so do not access shared data (i.e. the softc) after
901 * interrupts are re-enabled.
902 */
903 static void
904 acpi_cpu_idle()
905 {
906 struct acpi_cpu_softc *sc;
907 struct acpi_cx *cx_next;
908 uint32_t start_time, end_time;
909 int bm_active, cx_next_idx, i;
910
911 /* If disabled, return immediately. */
912 if (cpu_disable_idle) {
913 ACPI_ENABLE_IRQS();
914 return;
915 }
916
917 /*
918 * Look up our CPU id to get our softc. If it's NULL, we'll use C1
919 * since there is no ACPI processor object for this CPU. This occurs
920 * for logical CPUs in the HTT case.
921 */
922 sc = cpu_softc[PCPU_GET(cpuid)];
923 if (sc == NULL) {
924 acpi_cpu_c1();
925 return;
926 }
927
928 /* Find the lowest state that has small enough latency. */
929 cx_next_idx = 0;
930 if (cpu_disable_deep_sleep)
931 i = min(sc->cpu_cx_lowest, sc->cpu_non_c3);
932 else
933 i = sc->cpu_cx_lowest;
934 for (; i >= 0; i--) {
935 if (sc->cpu_cx_states[i].trans_lat * 3 <= sc->cpu_prev_sleep) {
936 cx_next_idx = i;
937 break;
938 }
939 }
940
941 /*
942 * Check for bus master activity. If there was activity, clear
943 * the bit and use the lowest non-C3 state. Note that the USB
944 * driver polling for new devices keeps this bit set all the
945 * time if USB is loaded.
946 */
947 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) {
948 AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active);
949 if (bm_active != 0) {
950 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1);
951 cx_next_idx = min(cx_next_idx, sc->cpu_non_c3);
952 }
953 }
954
955 /* Select the next state and update statistics. */
956 cx_next = &sc->cpu_cx_states[cx_next_idx];
957 sc->cpu_cx_stats[cx_next_idx]++;
958 KASSERT(cx_next->type != ACPI_STATE_C0, ("acpi_cpu_idle: C0 sleep"));
959
960 /*
961 * Execute HLT (or equivalent) and wait for an interrupt. We can't
962 * precisely calculate the time spent in C1 since the place we wake up
963 * is an ISR. Assume we slept no more then half of quantum, unless
964 * we are called inside critical section, delaying context switch.
965 */
966 if (cx_next->type == ACPI_STATE_C1) {
967 AcpiHwRead(&start_time, &AcpiGbl_FADT.XPmTimerBlock);
968 acpi_cpu_c1();
969 AcpiHwRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock);
970 end_time = PM_USEC(acpi_TimerDelta(end_time, start_time));
971 if (curthread->td_critnest == 0)
972 end_time = min(end_time, 500000 / hz);
973 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + end_time) / 4;
974 return;
975 }
976
977 /*
978 * For C3, disable bus master arbitration and enable bus master wake
979 * if BM control is available, otherwise flush the CPU cache.
980 */
981 if (cx_next->type == ACPI_STATE_C3) {
982 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) {
983 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 1);
984 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1);
985 } else
986 ACPI_FLUSH_CPU_CACHE();
987 }
988
989 /*
990 * Read from P_LVLx to enter C2(+), checking time spent asleep.
991 * Use the ACPI timer for measuring sleep time. Since we need to
992 * get the time very close to the CPU start/stop clock logic, this
993 * is the only reliable time source.
994 */
995 AcpiHwRead(&start_time, &AcpiGbl_FADT.XPmTimerBlock);
996 CPU_GET_REG(cx_next->p_lvlx, 1);
997
998 /*
999 * Read the end time twice. Since it may take an arbitrary time
1000 * to enter the idle state, the first read may be executed before
1001 * the processor has stopped. Doing it again provides enough
1002 * margin that we are certain to have a correct value.
1003 */
1004 AcpiHwRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock);
1005 AcpiHwRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock);
1006
1007 /* Enable bus master arbitration and disable bus master wakeup. */
1008 if (cx_next->type == ACPI_STATE_C3 &&
1009 (cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) {
1010 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 0);
1011 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0);
1012 }
1013 ACPI_ENABLE_IRQS();
1014
1015 /* Find the actual time asleep in microseconds. */
1016 end_time = acpi_TimerDelta(end_time, start_time);
1017 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + PM_USEC(end_time)) / 4;
1018 }
1019
1020 /*
1021 * Re-evaluate the _CST object when we are notified that it changed.
1022 *
1023 * XXX Re-evaluation disabled until locking is done.
1024 */
1025 static void
1026 acpi_cpu_notify(ACPI_HANDLE h, UINT32 notify, void *context)
1027 {
1028 struct acpi_cpu_softc *sc = (struct acpi_cpu_softc *)context;
1029 struct acpi_cpu_softc *isc;
1030 int i;
1031
1032 if (notify != ACPI_NOTIFY_CX_STATES)
1033 return;
1034
1035 /* Update the list of Cx states. */
1036 acpi_cpu_cx_cst(sc);
1037 acpi_cpu_cx_list(sc);
1038
1039 /* Update the new lowest useable Cx state for all CPUs. */
1040 ACPI_SERIAL_BEGIN(cpu);
1041 cpu_cx_count = 0;
1042 for (i = 0; i < cpu_ndevices; i++) {
1043 isc = device_get_softc(cpu_devices[i]);
1044 if (isc->cpu_cx_count > cpu_cx_count)
1045 cpu_cx_count = isc->cpu_cx_count;
1046 }
1047 if (sc->cpu_cx_lowest < cpu_cx_lowest)
1048 acpi_cpu_set_cx_lowest(sc, min(cpu_cx_lowest, sc->cpu_cx_count - 1));
1049 ACPI_SERIAL_END(cpu);
1050 }
1051
1052 static int
1053 acpi_cpu_quirks(void)
1054 {
1055 device_t acpi_dev;
1056 uint32_t val;
1057
1058 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
1059
1060 /*
1061 * Bus mastering arbitration control is needed to keep caches coherent
1062 * while sleeping in C3. If it's not present but a working flush cache
1063 * instruction is present, flush the caches before entering C3 instead.
1064 * Otherwise, just disable C3 completely.
1065 */
1066 if (AcpiGbl_FADT.Pm2ControlBlock == 0 ||
1067 AcpiGbl_FADT.Pm2ControlLength == 0) {
1068 if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD) &&
1069 (AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD_FLUSH) == 0) {
1070 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL;
1071 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1072 "acpi_cpu: no BM control, using flush cache method\n"));
1073 } else {
1074 cpu_quirks |= CPU_QUIRK_NO_C3;
1075 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1076 "acpi_cpu: no BM control, C3 not available\n"));
1077 }
1078 }
1079
1080 /*
1081 * If we are using generic Cx mode, C3 on multiple CPUs requires using
1082 * the expensive flush cache instruction.
1083 */
1084 if (cpu_cx_generic && mp_ncpus > 1) {
1085 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL;
1086 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1087 "acpi_cpu: SMP, using flush cache mode for C3\n"));
1088 }
1089
1090 /* Look for various quirks of the PIIX4 part. */
1091 acpi_dev = pci_find_device(PCI_VENDOR_INTEL, PCI_DEVICE_82371AB_3);
1092 if (acpi_dev != NULL) {
1093 switch (pci_get_revid(acpi_dev)) {
1094 /*
1095 * Disable C3 support for all PIIX4 chipsets. Some of these parts
1096 * do not report the BMIDE status to the BM status register and
1097 * others have a livelock bug if Type-F DMA is enabled. Linux
1098 * works around the BMIDE bug by reading the BM status directly
1099 * but we take the simpler approach of disabling C3 for these
1100 * parts.
1101 *
1102 * See erratum #18 ("C3 Power State/BMIDE and Type-F DMA
1103 * Livelock") from the January 2002 PIIX4 specification update.
1104 * Applies to all PIIX4 models.
1105 *
1106 * Also, make sure that all interrupts cause a "Stop Break"
1107 * event to exit from C2 state.
1108 * Also, BRLD_EN_BM (ACPI_BITREG_BUS_MASTER_RLD in ACPI-speak)
1109 * should be set to zero, otherwise it causes C2 to short-sleep.
1110 * PIIX4 doesn't properly support C3 and bus master activity
1111 * need not break out of C2.
1112 */
1113 case PCI_REVISION_A_STEP:
1114 case PCI_REVISION_B_STEP:
1115 case PCI_REVISION_4E:
1116 case PCI_REVISION_4M:
1117 cpu_quirks |= CPU_QUIRK_NO_C3;
1118 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1119 "acpi_cpu: working around PIIX4 bug, disabling C3\n"));
1120
1121 val = pci_read_config(acpi_dev, PIIX4_DEVACTB_REG, 4);
1122 if ((val & PIIX4_STOP_BREAK_MASK) != PIIX4_STOP_BREAK_MASK) {
1123 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1124 "acpi_cpu: PIIX4: enabling IRQs to generate Stop Break\n"));
1125 val |= PIIX4_STOP_BREAK_MASK;
1126 pci_write_config(acpi_dev, PIIX4_DEVACTB_REG, val, 4);
1127 }
1128 AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_RLD, &val);
1129 if (val) {
1130 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1131 "acpi_cpu: PIIX4: reset BRLD_EN_BM\n"));
1132 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0);
1133 }
1134 break;
1135 default:
1136 break;
1137 }
1138 }
1139
1140 return (0);
1141 }
1142
1143 static int
1144 acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS)
1145 {
1146 struct acpi_cpu_softc *sc;
1147 struct sbuf sb;
1148 char buf[128];
1149 int i;
1150 uintmax_t fract, sum, whole;
1151
1152 sc = (struct acpi_cpu_softc *) arg1;
1153 sum = 0;
1154 for (i = 0; i < sc->cpu_cx_count; i++)
1155 sum += sc->cpu_cx_stats[i];
1156 sbuf_new(&sb, buf, sizeof(buf), SBUF_FIXEDLEN);
1157 for (i = 0; i < sc->cpu_cx_count; i++) {
1158 if (sum > 0) {
1159 whole = (uintmax_t)sc->cpu_cx_stats[i] * 100;
1160 fract = (whole % sum) * 100;
1161 sbuf_printf(&sb, "%u.%02u%% ", (u_int)(whole / sum),
1162 (u_int)(fract / sum));
1163 } else
1164 sbuf_printf(&sb, "0.00%% ");
1165 }
1166 sbuf_printf(&sb, "last %dus", sc->cpu_prev_sleep);
1167 sbuf_trim(&sb);
1168 sbuf_finish(&sb);
1169 sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
1170 sbuf_delete(&sb);
1171
1172 return (0);
1173 }
1174
1175 static int
1176 acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc, int val)
1177 {
1178 int i;
1179
1180 ACPI_SERIAL_ASSERT(cpu);
1181 sc->cpu_cx_lowest = val;
1182
1183 /* If not disabling, cache the new lowest non-C3 state. */
1184 sc->cpu_non_c3 = 0;
1185 for (i = sc->cpu_cx_lowest; i >= 0; i--) {
1186 if (sc->cpu_cx_states[i].type < ACPI_STATE_C3) {
1187 sc->cpu_non_c3 = i;
1188 break;
1189 }
1190 }
1191
1192 /* Reset the statistics counters. */
1193 bzero(sc->cpu_cx_stats, sizeof(sc->cpu_cx_stats));
1194 return (0);
1195 }
1196
1197 static int
1198 acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS)
1199 {
1200 struct acpi_cpu_softc *sc;
1201 char state[8];
1202 int val, error;
1203
1204 sc = (struct acpi_cpu_softc *) arg1;
1205 snprintf(state, sizeof(state), "C%d", sc->cpu_cx_lowest + 1);
1206 error = sysctl_handle_string(oidp, state, sizeof(state), req);
1207 if (error != 0 || req->newptr == NULL)
1208 return (error);
1209 if (strlen(state) < 2 || toupper(state[0]) != 'C')
1210 return (EINVAL);
1211 val = (int) strtol(state + 1, NULL, 10) - 1;
1212 if (val < 0 || val > sc->cpu_cx_count - 1)
1213 return (EINVAL);
1214
1215 ACPI_SERIAL_BEGIN(cpu);
1216 acpi_cpu_set_cx_lowest(sc, val);
1217 ACPI_SERIAL_END(cpu);
1218
1219 return (0);
1220 }
1221
1222 static int
1223 acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS)
1224 {
1225 struct acpi_cpu_softc *sc;
1226 char state[8];
1227 int val, error, i;
1228
1229 snprintf(state, sizeof(state), "C%d", cpu_cx_lowest + 1);
1230 error = sysctl_handle_string(oidp, state, sizeof(state), req);
1231 if (error != 0 || req->newptr == NULL)
1232 return (error);
1233 if (strlen(state) < 2 || toupper(state[0]) != 'C')
1234 return (EINVAL);
1235 val = (int) strtol(state + 1, NULL, 10) - 1;
1236 if (val < 0 || val > cpu_cx_count - 1)
1237 return (EINVAL);
1238 cpu_cx_lowest = val;
1239
1240 /* Update the new lowest useable Cx state for all CPUs. */
1241 ACPI_SERIAL_BEGIN(cpu);
1242 for (i = 0; i < cpu_ndevices; i++) {
1243 sc = device_get_softc(cpu_devices[i]);
1244 acpi_cpu_set_cx_lowest(sc, min(val, sc->cpu_cx_count - 1));
1245 }
1246 ACPI_SERIAL_END(cpu);
1247
1248 return (0);
1249 }
Cache object: 0daf8af618402ad0f694bdfda2e7ce5b
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