1 /*-
2 * Copyright (c) 2005 Poul-Henning Kamp
3 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD: releng/10.4/sys/dev/acpica/acpi_hpet.c 274001 2014-11-03 03:17:58Z rpaulo $");
30
31 #include "opt_acpi.h"
32 #if defined(__amd64__) || defined(__ia64__)
33 #define DEV_APIC
34 #else
35 #include "opt_apic.h"
36 #endif
37 #include <sys/param.h>
38 #include <sys/conf.h>
39 #include <sys/bus.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <sys/proc.h>
43 #include <sys/rman.h>
44 #include <sys/mman.h>
45 #include <sys/time.h>
46 #include <sys/smp.h>
47 #include <sys/sysctl.h>
48 #include <sys/timeet.h>
49 #include <sys/timetc.h>
50
51 #include <contrib/dev/acpica/include/acpi.h>
52 #include <contrib/dev/acpica/include/accommon.h>
53
54 #include <dev/acpica/acpivar.h>
55 #include <dev/acpica/acpi_hpet.h>
56
57 #ifdef DEV_APIC
58 #include "pcib_if.h"
59 #endif
60
61 #define HPET_VENDID_AMD 0x4353
62 #define HPET_VENDID_AMD2 0x1022
63 #define HPET_VENDID_INTEL 0x8086
64 #define HPET_VENDID_NVIDIA 0x10de
65 #define HPET_VENDID_SW 0x1166
66
67 ACPI_SERIAL_DECL(hpet, "ACPI HPET support");
68
69 static devclass_t hpet_devclass;
70
71 /* ACPI CA debugging */
72 #define _COMPONENT ACPI_TIMER
73 ACPI_MODULE_NAME("HPET")
74
75 struct hpet_softc {
76 device_t dev;
77 int mem_rid;
78 int intr_rid;
79 int irq;
80 int useirq;
81 int legacy_route;
82 int per_cpu;
83 uint32_t allowed_irqs;
84 struct resource *mem_res;
85 struct resource *intr_res;
86 void *intr_handle;
87 ACPI_HANDLE handle;
88 uint64_t freq;
89 uint32_t caps;
90 struct timecounter tc;
91 struct hpet_timer {
92 struct eventtimer et;
93 struct hpet_softc *sc;
94 int num;
95 int mode;
96 int intr_rid;
97 int irq;
98 int pcpu_cpu;
99 int pcpu_misrouted;
100 int pcpu_master;
101 int pcpu_slaves[MAXCPU];
102 struct resource *intr_res;
103 void *intr_handle;
104 uint32_t caps;
105 uint32_t vectors;
106 uint32_t div;
107 uint32_t next;
108 char name[8];
109 } t[32];
110 int num_timers;
111 struct cdev *pdev;
112 int mmap_allow;
113 int mmap_allow_write;
114 };
115
116 static d_open_t hpet_open;
117 static d_mmap_t hpet_mmap;
118
119 static struct cdevsw hpet_cdevsw = {
120 .d_version = D_VERSION,
121 .d_name = "hpet",
122 .d_open = hpet_open,
123 .d_mmap = hpet_mmap,
124 };
125
126 static u_int hpet_get_timecount(struct timecounter *tc);
127 static void hpet_test(struct hpet_softc *sc);
128
129 static char *hpet_ids[] = { "PNP0103", NULL };
130
131 static u_int
132 hpet_get_timecount(struct timecounter *tc)
133 {
134 struct hpet_softc *sc;
135
136 sc = tc->tc_priv;
137 return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER));
138 }
139
140 static void
141 hpet_enable(struct hpet_softc *sc)
142 {
143 uint32_t val;
144
145 val = bus_read_4(sc->mem_res, HPET_CONFIG);
146 if (sc->legacy_route)
147 val |= HPET_CNF_LEG_RT;
148 else
149 val &= ~HPET_CNF_LEG_RT;
150 val |= HPET_CNF_ENABLE;
151 bus_write_4(sc->mem_res, HPET_CONFIG, val);
152 }
153
154 static void
155 hpet_disable(struct hpet_softc *sc)
156 {
157 uint32_t val;
158
159 val = bus_read_4(sc->mem_res, HPET_CONFIG);
160 val &= ~HPET_CNF_ENABLE;
161 bus_write_4(sc->mem_res, HPET_CONFIG, val);
162 }
163
164 static int
165 hpet_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
166 {
167 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv;
168 struct hpet_timer *t;
169 struct hpet_softc *sc = mt->sc;
170 uint32_t fdiv, now;
171
172 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]];
173 if (period != 0) {
174 t->mode = 1;
175 t->div = (sc->freq * period) >> 32;
176 } else {
177 t->mode = 2;
178 t->div = 0;
179 }
180 if (first != 0)
181 fdiv = (sc->freq * first) >> 32;
182 else
183 fdiv = t->div;
184 if (t->irq < 0)
185 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num);
186 t->caps |= HPET_TCNF_INT_ENB;
187 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
188 restart:
189 t->next = now + fdiv;
190 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) {
191 t->caps |= HPET_TCNF_TYPE;
192 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
193 t->caps | HPET_TCNF_VAL_SET);
194 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
195 t->next);
196 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
197 t->div);
198 } else {
199 t->caps &= ~HPET_TCNF_TYPE;
200 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
201 t->caps);
202 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
203 t->next);
204 }
205 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
206 if ((int32_t)(now - t->next + HPET_MIN_CYCLES) >= 0) {
207 fdiv *= 2;
208 goto restart;
209 }
210 return (0);
211 }
212
213 static int
214 hpet_stop(struct eventtimer *et)
215 {
216 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv;
217 struct hpet_timer *t;
218 struct hpet_softc *sc = mt->sc;
219
220 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]];
221 t->mode = 0;
222 t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE);
223 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps);
224 return (0);
225 }
226
227 static int
228 hpet_intr_single(void *arg)
229 {
230 struct hpet_timer *t = (struct hpet_timer *)arg;
231 struct hpet_timer *mt;
232 struct hpet_softc *sc = t->sc;
233 uint32_t now;
234
235 if (t->mode == 0)
236 return (FILTER_STRAY);
237 /* Check that per-CPU timer interrupt reached right CPU. */
238 if (t->pcpu_cpu >= 0 && t->pcpu_cpu != curcpu) {
239 if ((++t->pcpu_misrouted) % 32 == 0) {
240 printf("HPET interrupt routed to the wrong CPU"
241 " (timer %d CPU %d -> %d)!\n",
242 t->num, t->pcpu_cpu, curcpu);
243 }
244
245 /*
246 * Reload timer, hoping that next time may be more lucky
247 * (system will manage proper interrupt binding).
248 */
249 if ((t->mode == 1 && (t->caps & HPET_TCAP_PER_INT) == 0) ||
250 t->mode == 2) {
251 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER) +
252 sc->freq / 8;
253 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
254 t->next);
255 }
256 return (FILTER_HANDLED);
257 }
258 if (t->mode == 1 &&
259 (t->caps & HPET_TCAP_PER_INT) == 0) {
260 t->next += t->div;
261 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
262 if ((int32_t)((now + t->div / 2) - t->next) > 0)
263 t->next = now + t->div / 2;
264 bus_write_4(sc->mem_res,
265 HPET_TIMER_COMPARATOR(t->num), t->next);
266 } else if (t->mode == 2)
267 t->mode = 0;
268 mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master];
269 if (mt->et.et_active)
270 mt->et.et_event_cb(&mt->et, mt->et.et_arg);
271 return (FILTER_HANDLED);
272 }
273
274 static int
275 hpet_intr(void *arg)
276 {
277 struct hpet_softc *sc = (struct hpet_softc *)arg;
278 int i;
279 uint32_t val;
280
281 val = bus_read_4(sc->mem_res, HPET_ISR);
282 if (val) {
283 bus_write_4(sc->mem_res, HPET_ISR, val);
284 val &= sc->useirq;
285 for (i = 0; i < sc->num_timers; i++) {
286 if ((val & (1 << i)) == 0)
287 continue;
288 hpet_intr_single(&sc->t[i]);
289 }
290 return (FILTER_HANDLED);
291 }
292 return (FILTER_STRAY);
293 }
294
295 static ACPI_STATUS
296 hpet_find(ACPI_HANDLE handle, UINT32 level, void *context,
297 void **status)
298 {
299 char **ids;
300 uint32_t id = (uint32_t)(uintptr_t)context;
301 uint32_t uid = 0;
302
303 for (ids = hpet_ids; *ids != NULL; ids++) {
304 if (acpi_MatchHid(handle, *ids))
305 break;
306 }
307 if (*ids == NULL)
308 return (AE_OK);
309 if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &uid)) ||
310 id == uid)
311 *status = acpi_get_device(handle);
312 return (AE_OK);
313 }
314
315 /*
316 * Find an existing IRQ resource that matches the requested IRQ range
317 * and return its RID. If one is not found, use a new RID.
318 */
319 static int
320 hpet_find_irq_rid(device_t dev, u_long start, u_long end)
321 {
322 u_long irq;
323 int error, rid;
324
325 for (rid = 0;; rid++) {
326 error = bus_get_resource(dev, SYS_RES_IRQ, rid, &irq, NULL);
327 if (error != 0 || (start <= irq && irq <= end))
328 return (rid);
329 }
330 }
331
332 static int
333 hpet_open(struct cdev *cdev, int oflags, int devtype, struct thread *td)
334 {
335 struct hpet_softc *sc;
336
337 sc = cdev->si_drv1;
338 if (!sc->mmap_allow)
339 return (EPERM);
340 else
341 return (0);
342 }
343
344 static int
345 hpet_mmap(struct cdev *cdev, vm_ooffset_t offset, vm_paddr_t *paddr,
346 int nprot, vm_memattr_t *memattr)
347 {
348 struct hpet_softc *sc;
349
350 sc = cdev->si_drv1;
351 if (offset > rman_get_size(sc->mem_res))
352 return (EINVAL);
353 if (!sc->mmap_allow_write && (nprot & PROT_WRITE))
354 return (EPERM);
355 *paddr = rman_get_start(sc->mem_res) + offset;
356 *memattr = VM_MEMATTR_UNCACHEABLE;
357
358 return (0);
359 }
360
361 /* Discover the HPET via the ACPI table of the same name. */
362 static void
363 hpet_identify(driver_t *driver, device_t parent)
364 {
365 ACPI_TABLE_HPET *hpet;
366 ACPI_STATUS status;
367 device_t child;
368 int i;
369
370 /* Only one HPET device can be added. */
371 if (devclass_get_device(hpet_devclass, 0))
372 return;
373 for (i = 1; ; i++) {
374 /* Search for HPET table. */
375 status = AcpiGetTable(ACPI_SIG_HPET, i, (ACPI_TABLE_HEADER **)&hpet);
376 if (ACPI_FAILURE(status))
377 return;
378 /* Search for HPET device with same ID. */
379 child = NULL;
380 AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT,
381 100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence,
382 (void *)&child);
383 /* If found - let it be probed in normal way. */
384 if (child) {
385 if (bus_get_resource(child, SYS_RES_MEMORY, 0,
386 NULL, NULL) != 0)
387 bus_set_resource(child, SYS_RES_MEMORY, 0,
388 hpet->Address.Address, HPET_MEM_WIDTH);
389 continue;
390 }
391 /* If not - create it from table info. */
392 child = BUS_ADD_CHILD(parent, 2, "hpet", 0);
393 if (child == NULL) {
394 printf("%s: can't add child\n", __func__);
395 continue;
396 }
397 bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address,
398 HPET_MEM_WIDTH);
399 }
400 }
401
402 static int
403 hpet_probe(device_t dev)
404 {
405 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__);
406
407 if (acpi_disabled("hpet"))
408 return (ENXIO);
409 if (acpi_get_handle(dev) != NULL &&
410 ACPI_ID_PROBE(device_get_parent(dev), dev, hpet_ids) == NULL)
411 return (ENXIO);
412
413 device_set_desc(dev, "High Precision Event Timer");
414 return (0);
415 }
416
417 static int
418 hpet_attach(device_t dev)
419 {
420 struct hpet_softc *sc;
421 struct hpet_timer *t;
422 int i, j, num_msi, num_timers, num_percpu_et, num_percpu_t, cur_cpu;
423 int pcpu_master;
424 static int maxhpetet = 0;
425 uint32_t val, val2, cvectors, dvectors;
426 uint16_t vendor, rev;
427
428 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__);
429
430 sc = device_get_softc(dev);
431 sc->dev = dev;
432 sc->handle = acpi_get_handle(dev);
433
434 sc->mem_rid = 0;
435 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
436 RF_ACTIVE);
437 if (sc->mem_res == NULL)
438 return (ENOMEM);
439
440 /* Validate that we can access the whole region. */
441 if (rman_get_size(sc->mem_res) < HPET_MEM_WIDTH) {
442 device_printf(dev, "memory region width %ld too small\n",
443 rman_get_size(sc->mem_res));
444 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
445 return (ENXIO);
446 }
447
448 /* Be sure timer is enabled. */
449 hpet_enable(sc);
450
451 /* Read basic statistics about the timer. */
452 val = bus_read_4(sc->mem_res, HPET_PERIOD);
453 if (val == 0) {
454 device_printf(dev, "invalid period\n");
455 hpet_disable(sc);
456 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
457 return (ENXIO);
458 }
459
460 sc->freq = (1000000000000000LL + val / 2) / val;
461 sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES);
462 vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16;
463 rev = sc->caps & HPET_CAP_REV_ID;
464 num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8);
465 /*
466 * ATI/AMD violates IA-PC HPET (High Precision Event Timers)
467 * Specification and provides an off by one number
468 * of timers/comparators.
469 * Additionally, they use unregistered value in VENDOR_ID field.
470 */
471 if (vendor == HPET_VENDID_AMD && rev < 0x10 && num_timers > 0)
472 num_timers--;
473 sc->num_timers = num_timers;
474 if (bootverbose) {
475 device_printf(dev,
476 "vendor 0x%x, rev 0x%x, %jdHz%s, %d timers,%s\n",
477 vendor, rev, sc->freq,
478 (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "",
479 num_timers,
480 (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : "");
481 }
482 for (i = 0; i < num_timers; i++) {
483 t = &sc->t[i];
484 t->sc = sc;
485 t->num = i;
486 t->mode = 0;
487 t->intr_rid = -1;
488 t->irq = -1;
489 t->pcpu_cpu = -1;
490 t->pcpu_misrouted = 0;
491 t->pcpu_master = -1;
492 t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i));
493 t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4);
494 if (bootverbose) {
495 device_printf(dev,
496 " t%d: irqs 0x%08x (%d)%s%s%s\n", i,
497 t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9,
498 (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "",
499 (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "",
500 (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : "");
501 }
502 }
503 if (testenv("debug.acpi.hpet_test"))
504 hpet_test(sc);
505 /*
506 * Don't attach if the timer never increments. Since the spec
507 * requires it to be at least 10 MHz, it has to change in 1 us.
508 */
509 val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
510 DELAY(1);
511 val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
512 if (val == val2) {
513 device_printf(dev, "HPET never increments, disabling\n");
514 hpet_disable(sc);
515 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
516 return (ENXIO);
517 }
518 /* Announce first HPET as timecounter. */
519 if (device_get_unit(dev) == 0) {
520 sc->tc.tc_get_timecount = hpet_get_timecount,
521 sc->tc.tc_counter_mask = ~0u,
522 sc->tc.tc_name = "HPET",
523 sc->tc.tc_quality = 950,
524 sc->tc.tc_frequency = sc->freq;
525 sc->tc.tc_priv = sc;
526 tc_init(&sc->tc);
527 }
528 /* If not disabled - setup and announce event timers. */
529 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
530 "clock", &i) == 0 && i == 0)
531 return (0);
532
533 /* Check whether we can and want legacy routing. */
534 sc->legacy_route = 0;
535 resource_int_value(device_get_name(dev), device_get_unit(dev),
536 "legacy_route", &sc->legacy_route);
537 if ((sc->caps & HPET_CAP_LEG_RT) == 0)
538 sc->legacy_route = 0;
539 if (sc->legacy_route) {
540 sc->t[0].vectors = 0;
541 sc->t[1].vectors = 0;
542 }
543
544 /* Check what IRQs we want use. */
545 /* By default allow any PCI IRQs. */
546 sc->allowed_irqs = 0xffff0000;
547 /*
548 * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16
549 * Lower are also not always working for different reasons.
550 * SB800 fixed it, but seems do not implements level triggering
551 * properly, that makes it very unreliable - it freezes after any
552 * interrupt loss. Avoid legacy IRQs for AMD.
553 */
554 if (vendor == HPET_VENDID_AMD || vendor == HPET_VENDID_AMD2)
555 sc->allowed_irqs = 0x00000000;
556 /*
557 * NVidia MCP5x chipsets have number of unexplained interrupt
558 * problems. For some reason, using HPET interrupts breaks HDA sound.
559 */
560 if (vendor == HPET_VENDID_NVIDIA && rev <= 0x01)
561 sc->allowed_irqs = 0x00000000;
562 /*
563 * ServerWorks HT1000 reported to have problems with IRQs >= 16.
564 * Lower IRQs are working, but allowed mask is not set correctly.
565 * Legacy_route mode works fine.
566 */
567 if (vendor == HPET_VENDID_SW && rev <= 0x01)
568 sc->allowed_irqs = 0x00000000;
569 /*
570 * Neither QEMU nor VirtualBox report supported IRQs correctly.
571 * The only way to use HPET there is to specify IRQs manually
572 * and/or use legacy_route. Legacy_route mode works on both.
573 */
574 if (vm_guest)
575 sc->allowed_irqs = 0x00000000;
576 /* Let user override. */
577 resource_int_value(device_get_name(dev), device_get_unit(dev),
578 "allowed_irqs", &sc->allowed_irqs);
579
580 /* Get how much per-CPU timers we should try to provide. */
581 sc->per_cpu = 1;
582 resource_int_value(device_get_name(dev), device_get_unit(dev),
583 "per_cpu", &sc->per_cpu);
584
585 num_msi = 0;
586 sc->useirq = 0;
587 /* Find IRQ vectors for all timers. */
588 cvectors = sc->allowed_irqs & 0xffff0000;
589 dvectors = sc->allowed_irqs & 0x0000ffff;
590 if (sc->legacy_route)
591 dvectors &= 0x0000fefe;
592 for (i = 0; i < num_timers; i++) {
593 t = &sc->t[i];
594 if (sc->legacy_route && i < 2)
595 t->irq = (i == 0) ? 0 : 8;
596 #ifdef DEV_APIC
597 else if (t->caps & HPET_TCAP_FSB_INT_DEL) {
598 if ((j = PCIB_ALLOC_MSIX(
599 device_get_parent(device_get_parent(dev)), dev,
600 &t->irq))) {
601 device_printf(dev,
602 "Can't allocate interrupt for t%d.\n", j);
603 }
604 }
605 #endif
606 else if (dvectors & t->vectors) {
607 t->irq = ffs(dvectors & t->vectors) - 1;
608 dvectors &= ~(1 << t->irq);
609 }
610 if (t->irq >= 0) {
611 t->intr_rid = hpet_find_irq_rid(dev, t->irq, t->irq);
612 t->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ,
613 &t->intr_rid, t->irq, t->irq, 1, RF_ACTIVE);
614 if (t->intr_res == NULL) {
615 t->irq = -1;
616 device_printf(dev,
617 "Can't map interrupt for t%d.\n", i);
618 } else if (bus_setup_intr(dev, t->intr_res,
619 INTR_TYPE_CLK, hpet_intr_single, NULL, t,
620 &t->intr_handle) != 0) {
621 t->irq = -1;
622 device_printf(dev,
623 "Can't setup interrupt for t%d.\n", i);
624 } else {
625 bus_describe_intr(dev, t->intr_res,
626 t->intr_handle, "t%d", i);
627 num_msi++;
628 }
629 }
630 if (t->irq < 0 && (cvectors & t->vectors) != 0) {
631 cvectors &= t->vectors;
632 sc->useirq |= (1 << i);
633 }
634 }
635 if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0)
636 sc->legacy_route = 0;
637 if (sc->legacy_route)
638 hpet_enable(sc);
639 /* Group timers for per-CPU operation. */
640 num_percpu_et = min(num_msi / mp_ncpus, sc->per_cpu);
641 num_percpu_t = num_percpu_et * mp_ncpus;
642 pcpu_master = 0;
643 cur_cpu = CPU_FIRST();
644 for (i = 0; i < num_timers; i++) {
645 t = &sc->t[i];
646 if (t->irq >= 0 && num_percpu_t > 0) {
647 if (cur_cpu == CPU_FIRST())
648 pcpu_master = i;
649 t->pcpu_cpu = cur_cpu;
650 t->pcpu_master = pcpu_master;
651 sc->t[pcpu_master].
652 pcpu_slaves[cur_cpu] = i;
653 bus_bind_intr(dev, t->intr_res, cur_cpu);
654 cur_cpu = CPU_NEXT(cur_cpu);
655 num_percpu_t--;
656 } else if (t->irq >= 0)
657 bus_bind_intr(dev, t->intr_res, CPU_FIRST());
658 }
659 bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff);
660 sc->irq = -1;
661 /* If at least one timer needs legacy IRQ - set it up. */
662 if (sc->useirq) {
663 j = i = fls(cvectors) - 1;
664 while (j > 0 && (cvectors & (1 << (j - 1))) != 0)
665 j--;
666 sc->intr_rid = hpet_find_irq_rid(dev, j, i);
667 sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ,
668 &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE);
669 if (sc->intr_res == NULL)
670 device_printf(dev, "Can't map interrupt.\n");
671 else if (bus_setup_intr(dev, sc->intr_res, INTR_TYPE_CLK,
672 hpet_intr, NULL, sc, &sc->intr_handle) != 0) {
673 device_printf(dev, "Can't setup interrupt.\n");
674 } else {
675 sc->irq = rman_get_start(sc->intr_res);
676 /* Bind IRQ to BSP to avoid live migration. */
677 bus_bind_intr(dev, sc->intr_res, CPU_FIRST());
678 }
679 }
680 /* Program and announce event timers. */
681 for (i = 0; i < num_timers; i++) {
682 t = &sc->t[i];
683 t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE);
684 t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB);
685 t->caps &= ~(HPET_TCNF_INT_TYPE);
686 t->caps |= HPET_TCNF_32MODE;
687 if (t->irq >= 0 && sc->legacy_route && i < 2) {
688 /* Legacy route doesn't need more configuration. */
689 } else
690 #ifdef DEV_APIC
691 if ((t->caps & HPET_TCAP_FSB_INT_DEL) && t->irq >= 0) {
692 uint64_t addr;
693 uint32_t data;
694
695 if (PCIB_MAP_MSI(
696 device_get_parent(device_get_parent(dev)), dev,
697 t->irq, &addr, &data) == 0) {
698 bus_write_4(sc->mem_res,
699 HPET_TIMER_FSB_ADDR(i), addr);
700 bus_write_4(sc->mem_res,
701 HPET_TIMER_FSB_VAL(i), data);
702 t->caps |= HPET_TCNF_FSB_EN;
703 } else
704 t->irq = -2;
705 } else
706 #endif
707 if (t->irq >= 0)
708 t->caps |= (t->irq << 9);
709 else if (sc->irq >= 0 && (t->vectors & (1 << sc->irq)))
710 t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE;
711 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps);
712 /* Skip event timers without set up IRQ. */
713 if (t->irq < 0 &&
714 (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0))
715 continue;
716 /* Announce the reset. */
717 if (maxhpetet == 0)
718 t->et.et_name = "HPET";
719 else {
720 sprintf(t->name, "HPET%d", maxhpetet);
721 t->et.et_name = t->name;
722 }
723 t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
724 t->et.et_quality = 450;
725 if (t->pcpu_master >= 0) {
726 t->et.et_flags |= ET_FLAGS_PERCPU;
727 t->et.et_quality += 100;
728 } else if (mp_ncpus >= 8)
729 t->et.et_quality -= 100;
730 if ((t->caps & HPET_TCAP_PER_INT) == 0)
731 t->et.et_quality -= 10;
732 t->et.et_frequency = sc->freq;
733 t->et.et_min_period =
734 ((uint64_t)(HPET_MIN_CYCLES * 2) << 32) / sc->freq;
735 t->et.et_max_period = (0xfffffffeLLU << 32) / sc->freq;
736 t->et.et_start = hpet_start;
737 t->et.et_stop = hpet_stop;
738 t->et.et_priv = &sc->t[i];
739 if (t->pcpu_master < 0 || t->pcpu_master == i) {
740 et_register(&t->et);
741 maxhpetet++;
742 }
743 }
744
745 sc->pdev = make_dev(&hpet_cdevsw, 0, UID_ROOT, GID_WHEEL,
746 0600, "hpet%d", device_get_unit(dev));
747 if (sc->pdev) {
748 sc->pdev->si_drv1 = sc;
749 sc->mmap_allow = 1;
750 TUNABLE_INT_FETCH("hw.acpi.hpet.mmap_allow",
751 &sc->mmap_allow);
752 sc->mmap_allow_write = 1;
753 TUNABLE_INT_FETCH("hw.acpi.hpet.mmap_allow_write",
754 &sc->mmap_allow_write);
755 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
756 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
757 OID_AUTO, "mmap_allow",
758 CTLFLAG_RW, &sc->mmap_allow, 0,
759 "Allow userland to memory map HPET");
760 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
761 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
762 OID_AUTO, "mmap_allow_write",
763 CTLFLAG_RW, &sc->mmap_allow_write, 0,
764 "Allow userland write to the HPET register space");
765 } else
766 device_printf(dev, "could not create /dev/hpet%d\n",
767 device_get_unit(dev));
768
769 return (0);
770 }
771
772 static int
773 hpet_detach(device_t dev)
774 {
775 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__);
776
777 /* XXX Without a tc_remove() function, we can't detach. */
778 return (EBUSY);
779 }
780
781 static int
782 hpet_suspend(device_t dev)
783 {
784 // struct hpet_softc *sc;
785
786 /*
787 * Disable the timer during suspend. The timer will not lose
788 * its state in S1 or S2, but we are required to disable
789 * it.
790 */
791 // sc = device_get_softc(dev);
792 // hpet_disable(sc);
793
794 return (0);
795 }
796
797 static int
798 hpet_resume(device_t dev)
799 {
800 struct hpet_softc *sc;
801 struct hpet_timer *t;
802 int i;
803
804 /* Re-enable the timer after a resume to keep the clock advancing. */
805 sc = device_get_softc(dev);
806 hpet_enable(sc);
807 /* Restart event timers that were running on suspend. */
808 for (i = 0; i < sc->num_timers; i++) {
809 t = &sc->t[i];
810 #ifdef DEV_APIC
811 if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) {
812 uint64_t addr;
813 uint32_t data;
814
815 if (PCIB_MAP_MSI(
816 device_get_parent(device_get_parent(dev)), dev,
817 t->irq, &addr, &data) == 0) {
818 bus_write_4(sc->mem_res,
819 HPET_TIMER_FSB_ADDR(i), addr);
820 bus_write_4(sc->mem_res,
821 HPET_TIMER_FSB_VAL(i), data);
822 }
823 }
824 #endif
825 if (t->mode == 0)
826 continue;
827 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
828 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) {
829 t->caps |= HPET_TCNF_TYPE;
830 t->next += t->div;
831 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
832 t->caps | HPET_TCNF_VAL_SET);
833 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
834 t->next);
835 bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num));
836 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
837 t->div);
838 } else {
839 t->next += sc->freq / 1024;
840 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
841 t->next);
842 }
843 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num);
844 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps);
845 }
846 return (0);
847 }
848
849 /* Print some basic latency/rate information to assist in debugging. */
850 static void
851 hpet_test(struct hpet_softc *sc)
852 {
853 int i;
854 uint32_t u1, u2;
855 struct bintime b0, b1, b2;
856 struct timespec ts;
857
858 binuptime(&b0);
859 binuptime(&b0);
860 binuptime(&b1);
861 u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
862 for (i = 1; i < 1000; i++)
863 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
864 binuptime(&b2);
865 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
866
867 bintime_sub(&b2, &b1);
868 bintime_sub(&b1, &b0);
869 bintime_sub(&b2, &b1);
870 bintime2timespec(&b2, &ts);
871
872 device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n",
873 (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1);
874
875 device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000);
876 }
877
878 #ifdef DEV_APIC
879 static int
880 hpet_remap_intr(device_t dev, device_t child, u_int irq)
881 {
882 struct hpet_softc *sc = device_get_softc(dev);
883 struct hpet_timer *t;
884 uint64_t addr;
885 uint32_t data;
886 int error, i;
887
888 for (i = 0; i < sc->num_timers; i++) {
889 t = &sc->t[i];
890 if (t->irq != irq)
891 continue;
892 error = PCIB_MAP_MSI(
893 device_get_parent(device_get_parent(dev)), dev,
894 irq, &addr, &data);
895 if (error)
896 return (error);
897 hpet_disable(sc); /* Stop timer to avoid interrupt loss. */
898 bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr);
899 bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data);
900 hpet_enable(sc);
901 return (0);
902 }
903 return (ENOENT);
904 }
905 #endif
906
907 static device_method_t hpet_methods[] = {
908 /* Device interface */
909 DEVMETHOD(device_identify, hpet_identify),
910 DEVMETHOD(device_probe, hpet_probe),
911 DEVMETHOD(device_attach, hpet_attach),
912 DEVMETHOD(device_detach, hpet_detach),
913 DEVMETHOD(device_suspend, hpet_suspend),
914 DEVMETHOD(device_resume, hpet_resume),
915
916 #ifdef DEV_APIC
917 DEVMETHOD(bus_remap_intr, hpet_remap_intr),
918 #endif
919
920 DEVMETHOD_END
921 };
922
923 static driver_t hpet_driver = {
924 "hpet",
925 hpet_methods,
926 sizeof(struct hpet_softc),
927 };
928
929 DRIVER_MODULE(hpet, acpi, hpet_driver, hpet_devclass, 0, 0);
930 MODULE_DEPEND(hpet, acpi, 1, 1, 1);
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