1 /*-
2 * Copyright (c) 2005 Poul-Henning Kamp
3 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD: releng/11.1/sys/dev/acpica/acpi_hpet.c 305866 2016-09-16 10:04:28Z kib $");
30
31 #include "opt_acpi.h"
32 #include "opt_compat.h"
33
34 #if defined(__amd64__)
35 #define DEV_APIC
36 #else
37 #include "opt_apic.h"
38 #endif
39 #include <sys/param.h>
40 #include <sys/conf.h>
41 #include <sys/bus.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/proc.h>
45 #include <sys/rman.h>
46 #include <sys/mman.h>
47 #include <sys/time.h>
48 #include <sys/smp.h>
49 #include <sys/sysctl.h>
50 #include <sys/timeet.h>
51 #include <sys/timetc.h>
52 #include <sys/vdso.h>
53
54 #include <contrib/dev/acpica/include/acpi.h>
55 #include <contrib/dev/acpica/include/accommon.h>
56
57 #include <dev/acpica/acpivar.h>
58 #include <dev/acpica/acpi_hpet.h>
59
60 #ifdef DEV_APIC
61 #include "pcib_if.h"
62 #endif
63
64 #define HPET_VENDID_AMD 0x4353
65 #define HPET_VENDID_AMD2 0x1022
66 #define HPET_VENDID_INTEL 0x8086
67 #define HPET_VENDID_NVIDIA 0x10de
68 #define HPET_VENDID_SW 0x1166
69
70 ACPI_SERIAL_DECL(hpet, "ACPI HPET support");
71
72 static devclass_t hpet_devclass;
73
74 /* ACPI CA debugging */
75 #define _COMPONENT ACPI_TIMER
76 ACPI_MODULE_NAME("HPET")
77
78 struct hpet_softc {
79 device_t dev;
80 int mem_rid;
81 int intr_rid;
82 int irq;
83 int useirq;
84 int legacy_route;
85 int per_cpu;
86 uint32_t allowed_irqs;
87 struct resource *mem_res;
88 struct resource *intr_res;
89 void *intr_handle;
90 ACPI_HANDLE handle;
91 uint32_t acpi_uid;
92 uint64_t freq;
93 uint32_t caps;
94 struct timecounter tc;
95 struct hpet_timer {
96 struct eventtimer et;
97 struct hpet_softc *sc;
98 int num;
99 int mode;
100 int intr_rid;
101 int irq;
102 int pcpu_cpu;
103 int pcpu_misrouted;
104 int pcpu_master;
105 int pcpu_slaves[MAXCPU];
106 struct resource *intr_res;
107 void *intr_handle;
108 uint32_t caps;
109 uint32_t vectors;
110 uint32_t div;
111 uint32_t next;
112 char name[8];
113 } t[32];
114 int num_timers;
115 struct cdev *pdev;
116 int mmap_allow;
117 int mmap_allow_write;
118 };
119
120 static d_open_t hpet_open;
121 static d_mmap_t hpet_mmap;
122
123 static struct cdevsw hpet_cdevsw = {
124 .d_version = D_VERSION,
125 .d_name = "hpet",
126 .d_open = hpet_open,
127 .d_mmap = hpet_mmap,
128 };
129
130 static u_int hpet_get_timecount(struct timecounter *tc);
131 static void hpet_test(struct hpet_softc *sc);
132
133 static char *hpet_ids[] = { "PNP0103", NULL };
134
135 /* Knob to disable acpi_hpet device */
136 bool acpi_hpet_disabled = false;
137
138 static u_int
139 hpet_get_timecount(struct timecounter *tc)
140 {
141 struct hpet_softc *sc;
142
143 sc = tc->tc_priv;
144 return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER));
145 }
146
147 uint32_t
148 hpet_vdso_timehands(struct vdso_timehands *vdso_th, struct timecounter *tc)
149 {
150 struct hpet_softc *sc;
151
152 sc = tc->tc_priv;
153 vdso_th->th_algo = VDSO_TH_ALGO_X86_HPET;
154 vdso_th->th_x86_shift = 0;
155 vdso_th->th_x86_hpet_idx = device_get_unit(sc->dev);
156 bzero(vdso_th->th_res, sizeof(vdso_th->th_res));
157 return (sc->mmap_allow != 0);
158 }
159
160 #ifdef COMPAT_FREEBSD32
161 uint32_t
162 hpet_vdso_timehands32(struct vdso_timehands32 *vdso_th32,
163 struct timecounter *tc)
164 {
165 struct hpet_softc *sc;
166
167 sc = tc->tc_priv;
168 vdso_th32->th_algo = VDSO_TH_ALGO_X86_HPET;
169 vdso_th32->th_x86_shift = 0;
170 vdso_th32->th_x86_hpet_idx = device_get_unit(sc->dev);
171 bzero(vdso_th32->th_res, sizeof(vdso_th32->th_res));
172 return (sc->mmap_allow != 0);
173 }
174 #endif
175
176 static void
177 hpet_enable(struct hpet_softc *sc)
178 {
179 uint32_t val;
180
181 val = bus_read_4(sc->mem_res, HPET_CONFIG);
182 if (sc->legacy_route)
183 val |= HPET_CNF_LEG_RT;
184 else
185 val &= ~HPET_CNF_LEG_RT;
186 val |= HPET_CNF_ENABLE;
187 bus_write_4(sc->mem_res, HPET_CONFIG, val);
188 }
189
190 static void
191 hpet_disable(struct hpet_softc *sc)
192 {
193 uint32_t val;
194
195 val = bus_read_4(sc->mem_res, HPET_CONFIG);
196 val &= ~HPET_CNF_ENABLE;
197 bus_write_4(sc->mem_res, HPET_CONFIG, val);
198 }
199
200 static int
201 hpet_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
202 {
203 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv;
204 struct hpet_timer *t;
205 struct hpet_softc *sc = mt->sc;
206 uint32_t fdiv, now;
207
208 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]];
209 if (period != 0) {
210 t->mode = 1;
211 t->div = (sc->freq * period) >> 32;
212 } else {
213 t->mode = 2;
214 t->div = 0;
215 }
216 if (first != 0)
217 fdiv = (sc->freq * first) >> 32;
218 else
219 fdiv = t->div;
220 if (t->irq < 0)
221 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num);
222 t->caps |= HPET_TCNF_INT_ENB;
223 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
224 restart:
225 t->next = now + fdiv;
226 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) {
227 t->caps |= HPET_TCNF_TYPE;
228 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
229 t->caps | HPET_TCNF_VAL_SET);
230 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
231 t->next);
232 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
233 t->div);
234 } else {
235 t->caps &= ~HPET_TCNF_TYPE;
236 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
237 t->caps);
238 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
239 t->next);
240 }
241 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
242 if ((int32_t)(now - t->next + HPET_MIN_CYCLES) >= 0) {
243 fdiv *= 2;
244 goto restart;
245 }
246 return (0);
247 }
248
249 static int
250 hpet_stop(struct eventtimer *et)
251 {
252 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv;
253 struct hpet_timer *t;
254 struct hpet_softc *sc = mt->sc;
255
256 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]];
257 t->mode = 0;
258 t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE);
259 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps);
260 return (0);
261 }
262
263 static int
264 hpet_intr_single(void *arg)
265 {
266 struct hpet_timer *t = (struct hpet_timer *)arg;
267 struct hpet_timer *mt;
268 struct hpet_softc *sc = t->sc;
269 uint32_t now;
270
271 if (t->mode == 0)
272 return (FILTER_STRAY);
273 /* Check that per-CPU timer interrupt reached right CPU. */
274 if (t->pcpu_cpu >= 0 && t->pcpu_cpu != curcpu) {
275 if ((++t->pcpu_misrouted) % 32 == 0) {
276 printf("HPET interrupt routed to the wrong CPU"
277 " (timer %d CPU %d -> %d)!\n",
278 t->num, t->pcpu_cpu, curcpu);
279 }
280
281 /*
282 * Reload timer, hoping that next time may be more lucky
283 * (system will manage proper interrupt binding).
284 */
285 if ((t->mode == 1 && (t->caps & HPET_TCAP_PER_INT) == 0) ||
286 t->mode == 2) {
287 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER) +
288 sc->freq / 8;
289 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
290 t->next);
291 }
292 return (FILTER_HANDLED);
293 }
294 if (t->mode == 1 &&
295 (t->caps & HPET_TCAP_PER_INT) == 0) {
296 t->next += t->div;
297 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
298 if ((int32_t)((now + t->div / 2) - t->next) > 0)
299 t->next = now + t->div / 2;
300 bus_write_4(sc->mem_res,
301 HPET_TIMER_COMPARATOR(t->num), t->next);
302 } else if (t->mode == 2)
303 t->mode = 0;
304 mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master];
305 if (mt->et.et_active)
306 mt->et.et_event_cb(&mt->et, mt->et.et_arg);
307 return (FILTER_HANDLED);
308 }
309
310 static int
311 hpet_intr(void *arg)
312 {
313 struct hpet_softc *sc = (struct hpet_softc *)arg;
314 int i;
315 uint32_t val;
316
317 val = bus_read_4(sc->mem_res, HPET_ISR);
318 if (val) {
319 bus_write_4(sc->mem_res, HPET_ISR, val);
320 val &= sc->useirq;
321 for (i = 0; i < sc->num_timers; i++) {
322 if ((val & (1 << i)) == 0)
323 continue;
324 hpet_intr_single(&sc->t[i]);
325 }
326 return (FILTER_HANDLED);
327 }
328 return (FILTER_STRAY);
329 }
330
331 uint32_t
332 hpet_get_uid(device_t dev)
333 {
334 struct hpet_softc *sc;
335
336 sc = device_get_softc(dev);
337 return (sc->acpi_uid);
338 }
339
340 static ACPI_STATUS
341 hpet_find(ACPI_HANDLE handle, UINT32 level, void *context,
342 void **status)
343 {
344 char **ids;
345 uint32_t id = (uint32_t)(uintptr_t)context;
346 uint32_t uid = 0;
347
348 for (ids = hpet_ids; *ids != NULL; ids++) {
349 if (acpi_MatchHid(handle, *ids))
350 break;
351 }
352 if (*ids == NULL)
353 return (AE_OK);
354 if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &uid)) ||
355 id == uid)
356 *status = acpi_get_device(handle);
357 return (AE_OK);
358 }
359
360 /*
361 * Find an existing IRQ resource that matches the requested IRQ range
362 * and return its RID. If one is not found, use a new RID.
363 */
364 static int
365 hpet_find_irq_rid(device_t dev, u_long start, u_long end)
366 {
367 rman_res_t irq;
368 int error, rid;
369
370 for (rid = 0;; rid++) {
371 error = bus_get_resource(dev, SYS_RES_IRQ, rid, &irq, NULL);
372 if (error != 0 || (start <= irq && irq <= end))
373 return (rid);
374 }
375 }
376
377 static int
378 hpet_open(struct cdev *cdev, int oflags, int devtype, struct thread *td)
379 {
380 struct hpet_softc *sc;
381
382 sc = cdev->si_drv1;
383 if (!sc->mmap_allow)
384 return (EPERM);
385 else
386 return (0);
387 }
388
389 static int
390 hpet_mmap(struct cdev *cdev, vm_ooffset_t offset, vm_paddr_t *paddr,
391 int nprot, vm_memattr_t *memattr)
392 {
393 struct hpet_softc *sc;
394
395 sc = cdev->si_drv1;
396 if (offset > rman_get_size(sc->mem_res))
397 return (EINVAL);
398 if (!sc->mmap_allow_write && (nprot & PROT_WRITE))
399 return (EPERM);
400 *paddr = rman_get_start(sc->mem_res) + offset;
401 *memattr = VM_MEMATTR_UNCACHEABLE;
402
403 return (0);
404 }
405
406 /* Discover the HPET via the ACPI table of the same name. */
407 static void
408 hpet_identify(driver_t *driver, device_t parent)
409 {
410 ACPI_TABLE_HPET *hpet;
411 ACPI_STATUS status;
412 device_t child;
413 int i;
414
415 /* Only one HPET device can be added. */
416 if (devclass_get_device(hpet_devclass, 0))
417 return;
418 for (i = 1; ; i++) {
419 /* Search for HPET table. */
420 status = AcpiGetTable(ACPI_SIG_HPET, i, (ACPI_TABLE_HEADER **)&hpet);
421 if (ACPI_FAILURE(status))
422 return;
423 /* Search for HPET device with same ID. */
424 child = NULL;
425 AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT,
426 100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence,
427 (void *)&child);
428 /* If found - let it be probed in normal way. */
429 if (child) {
430 if (bus_get_resource(child, SYS_RES_MEMORY, 0,
431 NULL, NULL) != 0)
432 bus_set_resource(child, SYS_RES_MEMORY, 0,
433 hpet->Address.Address, HPET_MEM_WIDTH);
434 continue;
435 }
436 /* If not - create it from table info. */
437 child = BUS_ADD_CHILD(parent, 2, "hpet", 0);
438 if (child == NULL) {
439 printf("%s: can't add child\n", __func__);
440 continue;
441 }
442 bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address,
443 HPET_MEM_WIDTH);
444 }
445 }
446
447 static int
448 hpet_probe(device_t dev)
449 {
450 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__);
451
452 if (acpi_disabled("hpet") || acpi_hpet_disabled)
453 return (ENXIO);
454 if (acpi_get_handle(dev) != NULL &&
455 ACPI_ID_PROBE(device_get_parent(dev), dev, hpet_ids) == NULL)
456 return (ENXIO);
457
458 device_set_desc(dev, "High Precision Event Timer");
459 return (0);
460 }
461
462 static int
463 hpet_attach(device_t dev)
464 {
465 struct hpet_softc *sc;
466 struct hpet_timer *t;
467 struct make_dev_args mda;
468 int i, j, num_msi, num_timers, num_percpu_et, num_percpu_t, cur_cpu;
469 int pcpu_master, error;
470 static int maxhpetet = 0;
471 uint32_t val, val2, cvectors, dvectors;
472 uint16_t vendor, rev;
473
474 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__);
475
476 sc = device_get_softc(dev);
477 sc->dev = dev;
478 sc->handle = acpi_get_handle(dev);
479
480 sc->mem_rid = 0;
481 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
482 RF_ACTIVE);
483 if (sc->mem_res == NULL)
484 return (ENOMEM);
485
486 /* Validate that we can access the whole region. */
487 if (rman_get_size(sc->mem_res) < HPET_MEM_WIDTH) {
488 device_printf(dev, "memory region width %jd too small\n",
489 rman_get_size(sc->mem_res));
490 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
491 return (ENXIO);
492 }
493
494 /* Be sure timer is enabled. */
495 hpet_enable(sc);
496
497 /* Read basic statistics about the timer. */
498 val = bus_read_4(sc->mem_res, HPET_PERIOD);
499 if (val == 0) {
500 device_printf(dev, "invalid period\n");
501 hpet_disable(sc);
502 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
503 return (ENXIO);
504 }
505
506 sc->freq = (1000000000000000LL + val / 2) / val;
507 sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES);
508 vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16;
509 rev = sc->caps & HPET_CAP_REV_ID;
510 num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8);
511 /*
512 * ATI/AMD violates IA-PC HPET (High Precision Event Timers)
513 * Specification and provides an off by one number
514 * of timers/comparators.
515 * Additionally, they use unregistered value in VENDOR_ID field.
516 */
517 if (vendor == HPET_VENDID_AMD && rev < 0x10 && num_timers > 0)
518 num_timers--;
519 sc->num_timers = num_timers;
520 if (bootverbose) {
521 device_printf(dev,
522 "vendor 0x%x, rev 0x%x, %jdHz%s, %d timers,%s\n",
523 vendor, rev, sc->freq,
524 (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "",
525 num_timers,
526 (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : "");
527 }
528 for (i = 0; i < num_timers; i++) {
529 t = &sc->t[i];
530 t->sc = sc;
531 t->num = i;
532 t->mode = 0;
533 t->intr_rid = -1;
534 t->irq = -1;
535 t->pcpu_cpu = -1;
536 t->pcpu_misrouted = 0;
537 t->pcpu_master = -1;
538 t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i));
539 t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4);
540 if (bootverbose) {
541 device_printf(dev,
542 " t%d: irqs 0x%08x (%d)%s%s%s\n", i,
543 t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9,
544 (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "",
545 (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "",
546 (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : "");
547 }
548 }
549 if (testenv("debug.acpi.hpet_test"))
550 hpet_test(sc);
551 /*
552 * Don't attach if the timer never increments. Since the spec
553 * requires it to be at least 10 MHz, it has to change in 1 us.
554 */
555 val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
556 DELAY(1);
557 val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
558 if (val == val2) {
559 device_printf(dev, "HPET never increments, disabling\n");
560 hpet_disable(sc);
561 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
562 return (ENXIO);
563 }
564 /* Announce first HPET as timecounter. */
565 if (device_get_unit(dev) == 0) {
566 sc->tc.tc_get_timecount = hpet_get_timecount,
567 sc->tc.tc_counter_mask = ~0u,
568 sc->tc.tc_name = "HPET",
569 sc->tc.tc_quality = 950,
570 sc->tc.tc_frequency = sc->freq;
571 sc->tc.tc_priv = sc;
572 sc->tc.tc_fill_vdso_timehands = hpet_vdso_timehands;
573 #ifdef COMPAT_FREEBSD32
574 sc->tc.tc_fill_vdso_timehands32 = hpet_vdso_timehands32;
575 #endif
576 tc_init(&sc->tc);
577 }
578 /* If not disabled - setup and announce event timers. */
579 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
580 "clock", &i) == 0 && i == 0)
581 return (0);
582
583 /* Check whether we can and want legacy routing. */
584 sc->legacy_route = 0;
585 resource_int_value(device_get_name(dev), device_get_unit(dev),
586 "legacy_route", &sc->legacy_route);
587 if ((sc->caps & HPET_CAP_LEG_RT) == 0)
588 sc->legacy_route = 0;
589 if (sc->legacy_route) {
590 sc->t[0].vectors = 0;
591 sc->t[1].vectors = 0;
592 }
593
594 /* Check what IRQs we want use. */
595 /* By default allow any PCI IRQs. */
596 sc->allowed_irqs = 0xffff0000;
597 /*
598 * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16
599 * Lower are also not always working for different reasons.
600 * SB800 fixed it, but seems do not implements level triggering
601 * properly, that makes it very unreliable - it freezes after any
602 * interrupt loss. Avoid legacy IRQs for AMD.
603 */
604 if (vendor == HPET_VENDID_AMD || vendor == HPET_VENDID_AMD2)
605 sc->allowed_irqs = 0x00000000;
606 /*
607 * NVidia MCP5x chipsets have number of unexplained interrupt
608 * problems. For some reason, using HPET interrupts breaks HDA sound.
609 */
610 if (vendor == HPET_VENDID_NVIDIA && rev <= 0x01)
611 sc->allowed_irqs = 0x00000000;
612 /*
613 * ServerWorks HT1000 reported to have problems with IRQs >= 16.
614 * Lower IRQs are working, but allowed mask is not set correctly.
615 * Legacy_route mode works fine.
616 */
617 if (vendor == HPET_VENDID_SW && rev <= 0x01)
618 sc->allowed_irqs = 0x00000000;
619 /*
620 * Neither QEMU nor VirtualBox report supported IRQs correctly.
621 * The only way to use HPET there is to specify IRQs manually
622 * and/or use legacy_route. Legacy_route mode works on both.
623 */
624 if (vm_guest)
625 sc->allowed_irqs = 0x00000000;
626 /* Let user override. */
627 resource_int_value(device_get_name(dev), device_get_unit(dev),
628 "allowed_irqs", &sc->allowed_irqs);
629
630 /* Get how much per-CPU timers we should try to provide. */
631 sc->per_cpu = 1;
632 resource_int_value(device_get_name(dev), device_get_unit(dev),
633 "per_cpu", &sc->per_cpu);
634
635 num_msi = 0;
636 sc->useirq = 0;
637 /* Find IRQ vectors for all timers. */
638 cvectors = sc->allowed_irqs & 0xffff0000;
639 dvectors = sc->allowed_irqs & 0x0000ffff;
640 if (sc->legacy_route)
641 dvectors &= 0x0000fefe;
642 for (i = 0; i < num_timers; i++) {
643 t = &sc->t[i];
644 if (sc->legacy_route && i < 2)
645 t->irq = (i == 0) ? 0 : 8;
646 #ifdef DEV_APIC
647 else if (t->caps & HPET_TCAP_FSB_INT_DEL) {
648 if ((j = PCIB_ALLOC_MSIX(
649 device_get_parent(device_get_parent(dev)), dev,
650 &t->irq))) {
651 device_printf(dev,
652 "Can't allocate interrupt for t%d: %d\n",
653 i, j);
654 }
655 }
656 #endif
657 else if (dvectors & t->vectors) {
658 t->irq = ffs(dvectors & t->vectors) - 1;
659 dvectors &= ~(1 << t->irq);
660 }
661 if (t->irq >= 0) {
662 t->intr_rid = hpet_find_irq_rid(dev, t->irq, t->irq);
663 t->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ,
664 &t->intr_rid, t->irq, t->irq, 1, RF_ACTIVE);
665 if (t->intr_res == NULL) {
666 t->irq = -1;
667 device_printf(dev,
668 "Can't map interrupt for t%d.\n", i);
669 } else if (bus_setup_intr(dev, t->intr_res,
670 INTR_TYPE_CLK, hpet_intr_single, NULL, t,
671 &t->intr_handle) != 0) {
672 t->irq = -1;
673 device_printf(dev,
674 "Can't setup interrupt for t%d.\n", i);
675 } else {
676 bus_describe_intr(dev, t->intr_res,
677 t->intr_handle, "t%d", i);
678 num_msi++;
679 }
680 }
681 if (t->irq < 0 && (cvectors & t->vectors) != 0) {
682 cvectors &= t->vectors;
683 sc->useirq |= (1 << i);
684 }
685 }
686 if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0)
687 sc->legacy_route = 0;
688 if (sc->legacy_route)
689 hpet_enable(sc);
690 /* Group timers for per-CPU operation. */
691 num_percpu_et = min(num_msi / mp_ncpus, sc->per_cpu);
692 num_percpu_t = num_percpu_et * mp_ncpus;
693 pcpu_master = 0;
694 cur_cpu = CPU_FIRST();
695 for (i = 0; i < num_timers; i++) {
696 t = &sc->t[i];
697 if (t->irq >= 0 && num_percpu_t > 0) {
698 if (cur_cpu == CPU_FIRST())
699 pcpu_master = i;
700 t->pcpu_cpu = cur_cpu;
701 t->pcpu_master = pcpu_master;
702 sc->t[pcpu_master].
703 pcpu_slaves[cur_cpu] = i;
704 bus_bind_intr(dev, t->intr_res, cur_cpu);
705 cur_cpu = CPU_NEXT(cur_cpu);
706 num_percpu_t--;
707 } else if (t->irq >= 0)
708 bus_bind_intr(dev, t->intr_res, CPU_FIRST());
709 }
710 bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff);
711 sc->irq = -1;
712 /* If at least one timer needs legacy IRQ - set it up. */
713 if (sc->useirq) {
714 j = i = fls(cvectors) - 1;
715 while (j > 0 && (cvectors & (1 << (j - 1))) != 0)
716 j--;
717 sc->intr_rid = hpet_find_irq_rid(dev, j, i);
718 sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ,
719 &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE);
720 if (sc->intr_res == NULL)
721 device_printf(dev, "Can't map interrupt.\n");
722 else if (bus_setup_intr(dev, sc->intr_res, INTR_TYPE_CLK,
723 hpet_intr, NULL, sc, &sc->intr_handle) != 0) {
724 device_printf(dev, "Can't setup interrupt.\n");
725 } else {
726 sc->irq = rman_get_start(sc->intr_res);
727 /* Bind IRQ to BSP to avoid live migration. */
728 bus_bind_intr(dev, sc->intr_res, CPU_FIRST());
729 }
730 }
731 /* Program and announce event timers. */
732 for (i = 0; i < num_timers; i++) {
733 t = &sc->t[i];
734 t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE);
735 t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB);
736 t->caps &= ~(HPET_TCNF_INT_TYPE);
737 t->caps |= HPET_TCNF_32MODE;
738 if (t->irq >= 0 && sc->legacy_route && i < 2) {
739 /* Legacy route doesn't need more configuration. */
740 } else
741 #ifdef DEV_APIC
742 if ((t->caps & HPET_TCAP_FSB_INT_DEL) && t->irq >= 0) {
743 uint64_t addr;
744 uint32_t data;
745
746 if (PCIB_MAP_MSI(
747 device_get_parent(device_get_parent(dev)), dev,
748 t->irq, &addr, &data) == 0) {
749 bus_write_4(sc->mem_res,
750 HPET_TIMER_FSB_ADDR(i), addr);
751 bus_write_4(sc->mem_res,
752 HPET_TIMER_FSB_VAL(i), data);
753 t->caps |= HPET_TCNF_FSB_EN;
754 } else
755 t->irq = -2;
756 } else
757 #endif
758 if (t->irq >= 0)
759 t->caps |= (t->irq << 9);
760 else if (sc->irq >= 0 && (t->vectors & (1 << sc->irq)))
761 t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE;
762 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps);
763 /* Skip event timers without set up IRQ. */
764 if (t->irq < 0 &&
765 (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0))
766 continue;
767 /* Announce the reset. */
768 if (maxhpetet == 0)
769 t->et.et_name = "HPET";
770 else {
771 sprintf(t->name, "HPET%d", maxhpetet);
772 t->et.et_name = t->name;
773 }
774 t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
775 t->et.et_quality = 450;
776 if (t->pcpu_master >= 0) {
777 t->et.et_flags |= ET_FLAGS_PERCPU;
778 t->et.et_quality += 100;
779 } else if (mp_ncpus >= 8)
780 t->et.et_quality -= 100;
781 if ((t->caps & HPET_TCAP_PER_INT) == 0)
782 t->et.et_quality -= 10;
783 t->et.et_frequency = sc->freq;
784 t->et.et_min_period =
785 ((uint64_t)(HPET_MIN_CYCLES * 2) << 32) / sc->freq;
786 t->et.et_max_period = (0xfffffffeLLU << 32) / sc->freq;
787 t->et.et_start = hpet_start;
788 t->et.et_stop = hpet_stop;
789 t->et.et_priv = &sc->t[i];
790 if (t->pcpu_master < 0 || t->pcpu_master == i) {
791 et_register(&t->et);
792 maxhpetet++;
793 }
794 }
795 acpi_GetInteger(sc->handle, "_UID", &sc->acpi_uid);
796
797 make_dev_args_init(&mda);
798 mda.mda_devsw = &hpet_cdevsw;
799 mda.mda_uid = UID_ROOT;
800 mda.mda_gid = GID_WHEEL;
801 mda.mda_mode = 0644;
802 mda.mda_si_drv1 = sc;
803 error = make_dev_s(&mda, &sc->pdev, "hpet%d", device_get_unit(dev));
804 if (error == 0) {
805 sc->mmap_allow = 1;
806 TUNABLE_INT_FETCH("hw.acpi.hpet.mmap_allow",
807 &sc->mmap_allow);
808 sc->mmap_allow_write = 0;
809 TUNABLE_INT_FETCH("hw.acpi.hpet.mmap_allow_write",
810 &sc->mmap_allow_write);
811 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
812 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
813 OID_AUTO, "mmap_allow",
814 CTLFLAG_RW, &sc->mmap_allow, 0,
815 "Allow userland to memory map HPET");
816 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
817 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
818 OID_AUTO, "mmap_allow_write",
819 CTLFLAG_RW, &sc->mmap_allow_write, 0,
820 "Allow userland write to the HPET register space");
821 } else {
822 device_printf(dev, "could not create /dev/hpet%d, error %d\n",
823 device_get_unit(dev), error);
824 }
825
826 return (0);
827 }
828
829 static int
830 hpet_detach(device_t dev)
831 {
832 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__);
833
834 /* XXX Without a tc_remove() function, we can't detach. */
835 return (EBUSY);
836 }
837
838 static int
839 hpet_suspend(device_t dev)
840 {
841 // struct hpet_softc *sc;
842
843 /*
844 * Disable the timer during suspend. The timer will not lose
845 * its state in S1 or S2, but we are required to disable
846 * it.
847 */
848 // sc = device_get_softc(dev);
849 // hpet_disable(sc);
850
851 return (0);
852 }
853
854 static int
855 hpet_resume(device_t dev)
856 {
857 struct hpet_softc *sc;
858 struct hpet_timer *t;
859 int i;
860
861 /* Re-enable the timer after a resume to keep the clock advancing. */
862 sc = device_get_softc(dev);
863 hpet_enable(sc);
864 /* Restart event timers that were running on suspend. */
865 for (i = 0; i < sc->num_timers; i++) {
866 t = &sc->t[i];
867 #ifdef DEV_APIC
868 if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) {
869 uint64_t addr;
870 uint32_t data;
871
872 if (PCIB_MAP_MSI(
873 device_get_parent(device_get_parent(dev)), dev,
874 t->irq, &addr, &data) == 0) {
875 bus_write_4(sc->mem_res,
876 HPET_TIMER_FSB_ADDR(i), addr);
877 bus_write_4(sc->mem_res,
878 HPET_TIMER_FSB_VAL(i), data);
879 }
880 }
881 #endif
882 if (t->mode == 0)
883 continue;
884 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
885 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) {
886 t->caps |= HPET_TCNF_TYPE;
887 t->next += t->div;
888 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
889 t->caps | HPET_TCNF_VAL_SET);
890 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
891 t->next);
892 bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num));
893 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
894 t->div);
895 } else {
896 t->next += sc->freq / 1024;
897 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
898 t->next);
899 }
900 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num);
901 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps);
902 }
903 return (0);
904 }
905
906 /* Print some basic latency/rate information to assist in debugging. */
907 static void
908 hpet_test(struct hpet_softc *sc)
909 {
910 int i;
911 uint32_t u1, u2;
912 struct bintime b0, b1, b2;
913 struct timespec ts;
914
915 binuptime(&b0);
916 binuptime(&b0);
917 binuptime(&b1);
918 u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
919 for (i = 1; i < 1000; i++)
920 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
921 binuptime(&b2);
922 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
923
924 bintime_sub(&b2, &b1);
925 bintime_sub(&b1, &b0);
926 bintime_sub(&b2, &b1);
927 bintime2timespec(&b2, &ts);
928
929 device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n",
930 (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1);
931
932 device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000);
933 }
934
935 #ifdef DEV_APIC
936 static int
937 hpet_remap_intr(device_t dev, device_t child, u_int irq)
938 {
939 struct hpet_softc *sc = device_get_softc(dev);
940 struct hpet_timer *t;
941 uint64_t addr;
942 uint32_t data;
943 int error, i;
944
945 for (i = 0; i < sc->num_timers; i++) {
946 t = &sc->t[i];
947 if (t->irq != irq)
948 continue;
949 error = PCIB_MAP_MSI(
950 device_get_parent(device_get_parent(dev)), dev,
951 irq, &addr, &data);
952 if (error)
953 return (error);
954 hpet_disable(sc); /* Stop timer to avoid interrupt loss. */
955 bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr);
956 bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data);
957 hpet_enable(sc);
958 return (0);
959 }
960 return (ENOENT);
961 }
962 #endif
963
964 static device_method_t hpet_methods[] = {
965 /* Device interface */
966 DEVMETHOD(device_identify, hpet_identify),
967 DEVMETHOD(device_probe, hpet_probe),
968 DEVMETHOD(device_attach, hpet_attach),
969 DEVMETHOD(device_detach, hpet_detach),
970 DEVMETHOD(device_suspend, hpet_suspend),
971 DEVMETHOD(device_resume, hpet_resume),
972
973 #ifdef DEV_APIC
974 DEVMETHOD(bus_remap_intr, hpet_remap_intr),
975 #endif
976
977 DEVMETHOD_END
978 };
979
980 static driver_t hpet_driver = {
981 "hpet",
982 hpet_methods,
983 sizeof(struct hpet_softc),
984 };
985
986 DRIVER_MODULE(hpet, acpi, hpet_driver, hpet_devclass, 0, 0);
987 MODULE_DEPEND(hpet, acpi, 1, 1, 1);
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