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sys/dev/acpica/acpi_hpet.c
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1 /*- 2 * Copyright (c) 2005 Poul-Henning Kamp 3 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include "opt_acpi.h" 32 #include "opt_compat.h" 33 34 #if defined(__amd64__) 35 #define DEV_APIC 36 #else 37 #include "opt_apic.h" 38 #endif 39 #include <sys/param.h> 40 #include <sys/conf.h> 41 #include <sys/bus.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/proc.h> 45 #include <sys/rman.h> 46 #include <sys/mman.h> 47 #include <sys/time.h> 48 #include <sys/smp.h> 49 #include <sys/sysctl.h> 50 #include <sys/timeet.h> 51 #include <sys/timetc.h> 52 #include <sys/vdso.h> 53 54 #include <contrib/dev/acpica/include/acpi.h> 55 #include <contrib/dev/acpica/include/accommon.h> 56 57 #include <dev/acpica/acpivar.h> 58 #include <dev/acpica/acpi_hpet.h> 59 60 #ifdef DEV_APIC 61 #include "pcib_if.h" 62 #endif 63 64 #define HPET_VENDID_AMD 0x4353 65 #define HPET_VENDID_AMD2 0x1022 66 #define HPET_VENDID_INTEL 0x8086 67 #define HPET_VENDID_NVIDIA 0x10de 68 #define HPET_VENDID_SW 0x1166 69 70 ACPI_SERIAL_DECL(hpet, "ACPI HPET support"); 71 72 static devclass_t hpet_devclass; 73 74 /* ACPI CA debugging */ 75 #define _COMPONENT ACPI_TIMER 76 ACPI_MODULE_NAME("HPET") 77 78 struct hpet_softc { 79 device_t dev; 80 int mem_rid; 81 int intr_rid; 82 int irq; 83 int useirq; 84 int legacy_route; 85 int per_cpu; 86 uint32_t allowed_irqs; 87 struct resource *mem_res; 88 struct resource *intr_res; 89 void *intr_handle; 90 ACPI_HANDLE handle; 91 uint32_t acpi_uid; 92 uint64_t freq; 93 uint32_t caps; 94 struct timecounter tc; 95 struct hpet_timer { 96 struct eventtimer et; 97 struct hpet_softc *sc; 98 int num; 99 int mode; 100 #define TIMER_STOPPED 0 101 #define TIMER_PERIODIC 1 102 #define TIMER_ONESHOT 2 103 int intr_rid; 104 int irq; 105 int pcpu_cpu; 106 int pcpu_misrouted; 107 int pcpu_master; 108 int pcpu_slaves[MAXCPU]; 109 struct resource *intr_res; 110 void *intr_handle; 111 uint32_t caps; 112 uint32_t vectors; 113 uint32_t div; 114 uint32_t next; 115 char name[8]; 116 } t[32]; 117 int num_timers; 118 struct cdev *pdev; 119 int mmap_allow; 120 int mmap_allow_write; 121 }; 122 123 static d_open_t hpet_open; 124 static d_mmap_t hpet_mmap; 125 126 static struct cdevsw hpet_cdevsw = { 127 .d_version = D_VERSION, 128 .d_name = "hpet", 129 .d_open = hpet_open, 130 .d_mmap = hpet_mmap, 131 }; 132 133 static u_int hpet_get_timecount(struct timecounter *tc); 134 static void hpet_test(struct hpet_softc *sc); 135 136 static char *hpet_ids[] = { "PNP0103", NULL }; 137 138 /* Knob to disable acpi_hpet device */ 139 bool acpi_hpet_disabled = false; 140 141 static u_int 142 hpet_get_timecount(struct timecounter *tc) 143 { 144 struct hpet_softc *sc; 145 146 sc = tc->tc_priv; 147 return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER)); 148 } 149 150 uint32_t 151 hpet_vdso_timehands(struct vdso_timehands *vdso_th, struct timecounter *tc) 152 { 153 struct hpet_softc *sc; 154 155 sc = tc->tc_priv; 156 vdso_th->th_algo = VDSO_TH_ALGO_X86_HPET; 157 vdso_th->th_x86_shift = 0; 158 vdso_th->th_x86_hpet_idx = device_get_unit(sc->dev); 159 bzero(vdso_th->th_res, sizeof(vdso_th->th_res)); 160 return (sc->mmap_allow != 0); 161 } 162 163 #ifdef COMPAT_FREEBSD32 164 uint32_t 165 hpet_vdso_timehands32(struct vdso_timehands32 *vdso_th32, 166 struct timecounter *tc) 167 { 168 struct hpet_softc *sc; 169 170 sc = tc->tc_priv; 171 vdso_th32->th_algo = VDSO_TH_ALGO_X86_HPET; 172 vdso_th32->th_x86_shift = 0; 173 vdso_th32->th_x86_hpet_idx = device_get_unit(sc->dev); 174 bzero(vdso_th32->th_res, sizeof(vdso_th32->th_res)); 175 return (sc->mmap_allow != 0); 176 } 177 #endif 178 179 static void 180 hpet_enable(struct hpet_softc *sc) 181 { 182 uint32_t val; 183 184 val = bus_read_4(sc->mem_res, HPET_CONFIG); 185 if (sc->legacy_route) 186 val |= HPET_CNF_LEG_RT; 187 else 188 val &= ~HPET_CNF_LEG_RT; 189 val |= HPET_CNF_ENABLE; 190 bus_write_4(sc->mem_res, HPET_CONFIG, val); 191 } 192 193 static void 194 hpet_disable(struct hpet_softc *sc) 195 { 196 uint32_t val; 197 198 val = bus_read_4(sc->mem_res, HPET_CONFIG); 199 val &= ~HPET_CNF_ENABLE; 200 bus_write_4(sc->mem_res, HPET_CONFIG, val); 201 } 202 203 static int 204 hpet_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 205 { 206 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 207 struct hpet_timer *t; 208 struct hpet_softc *sc = mt->sc; 209 uint32_t fdiv, now; 210 211 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 212 if (period != 0) { 213 t->mode = TIMER_PERIODIC; 214 t->div = (sc->freq * period) >> 32; 215 } else { 216 t->mode = TIMER_ONESHOT; 217 t->div = 0; 218 } 219 if (first != 0) 220 fdiv = (sc->freq * first) >> 32; 221 else 222 fdiv = t->div; 223 if (t->irq < 0) 224 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 225 t->caps |= HPET_TCNF_INT_ENB; 226 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 227 restart: 228 t->next = now + fdiv; 229 if (t->mode == TIMER_PERIODIC && (t->caps & HPET_TCAP_PER_INT)) { 230 t->caps |= HPET_TCNF_TYPE; 231 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 232 t->caps | HPET_TCNF_VAL_SET); 233 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 234 t->next); 235 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 236 t->div); 237 } else { 238 t->caps &= ~HPET_TCNF_TYPE; 239 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 240 t->caps); 241 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 242 t->next); 243 } 244 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 245 if ((int32_t)(now - t->next + HPET_MIN_CYCLES) >= 0) { 246 fdiv *= 2; 247 goto restart; 248 } 249 return (0); 250 } 251 252 static int 253 hpet_stop(struct eventtimer *et) 254 { 255 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 256 struct hpet_timer *t; 257 struct hpet_softc *sc = mt->sc; 258 259 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 260 t->mode = TIMER_STOPPED; 261 t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE); 262 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 263 return (0); 264 } 265 266 static int 267 hpet_intr_single(void *arg) 268 { 269 struct hpet_timer *t = (struct hpet_timer *)arg; 270 struct hpet_timer *mt; 271 struct hpet_softc *sc = t->sc; 272 uint32_t now; 273 274 if (t->mode == TIMER_STOPPED) 275 return (FILTER_STRAY); 276 /* Check that per-CPU timer interrupt reached right CPU. */ 277 if (t->pcpu_cpu >= 0 && t->pcpu_cpu != curcpu) { 278 if ((++t->pcpu_misrouted) % 32 == 0) { 279 printf("HPET interrupt routed to the wrong CPU" 280 " (timer %d CPU %d -> %d)!\n", 281 t->num, t->pcpu_cpu, curcpu); 282 } 283 284 /* 285 * Reload timer, hoping that next time may be more lucky 286 * (system will manage proper interrupt binding). 287 */ 288 if ((t->mode == TIMER_PERIODIC && 289 (t->caps & HPET_TCAP_PER_INT) == 0) || 290 t->mode == TIMER_ONESHOT) { 291 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER) + 292 sc->freq / 8; 293 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 294 t->next); 295 } 296 return (FILTER_HANDLED); 297 } 298 if (t->mode == TIMER_PERIODIC && 299 (t->caps & HPET_TCAP_PER_INT) == 0) { 300 t->next += t->div; 301 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 302 if ((int32_t)((now + t->div / 2) - t->next) > 0) 303 t->next = now + t->div / 2; 304 bus_write_4(sc->mem_res, 305 HPET_TIMER_COMPARATOR(t->num), t->next); 306 } else if (t->mode == TIMER_ONESHOT) 307 t->mode = TIMER_STOPPED; 308 mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master]; 309 if (mt->et.et_active) 310 mt->et.et_event_cb(&mt->et, mt->et.et_arg); 311 return (FILTER_HANDLED); 312 } 313 314 static int 315 hpet_intr(void *arg) 316 { 317 struct hpet_softc *sc = (struct hpet_softc *)arg; 318 int i; 319 uint32_t val; 320 321 val = bus_read_4(sc->mem_res, HPET_ISR); 322 if (val) { 323 bus_write_4(sc->mem_res, HPET_ISR, val); 324 val &= sc->useirq; 325 for (i = 0; i < sc->num_timers; i++) { 326 if ((val & (1 << i)) == 0) 327 continue; 328 hpet_intr_single(&sc->t[i]); 329 } 330 return (FILTER_HANDLED); 331 } 332 return (FILTER_STRAY); 333 } 334 335 uint32_t 336 hpet_get_uid(device_t dev) 337 { 338 struct hpet_softc *sc; 339 340 sc = device_get_softc(dev); 341 return (sc->acpi_uid); 342 } 343 344 static ACPI_STATUS 345 hpet_find(ACPI_HANDLE handle, UINT32 level, void *context, 346 void **status) 347 { 348 char **ids; 349 uint32_t id = (uint32_t)(uintptr_t)context; 350 uint32_t uid = 0; 351 352 for (ids = hpet_ids; *ids != NULL; ids++) { 353 if (acpi_MatchHid(handle, *ids)) 354 break; 355 } 356 if (*ids == NULL) 357 return (AE_OK); 358 if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &uid)) || 359 id == uid) 360 *status = acpi_get_device(handle); 361 return (AE_OK); 362 } 363 364 /* 365 * Find an existing IRQ resource that matches the requested IRQ range 366 * and return its RID. If one is not found, use a new RID. 367 */ 368 static int 369 hpet_find_irq_rid(device_t dev, u_long start, u_long end) 370 { 371 rman_res_t irq; 372 int error, rid; 373 374 for (rid = 0;; rid++) { 375 error = bus_get_resource(dev, SYS_RES_IRQ, rid, &irq, NULL); 376 if (error != 0 || (start <= irq && irq <= end)) 377 return (rid); 378 } 379 } 380 381 static int 382 hpet_open(struct cdev *cdev, int oflags, int devtype, struct thread *td) 383 { 384 struct hpet_softc *sc; 385 386 sc = cdev->si_drv1; 387 if (!sc->mmap_allow) 388 return (EPERM); 389 else 390 return (0); 391 } 392 393 static int 394 hpet_mmap(struct cdev *cdev, vm_ooffset_t offset, vm_paddr_t *paddr, 395 int nprot, vm_memattr_t *memattr) 396 { 397 struct hpet_softc *sc; 398 399 sc = cdev->si_drv1; 400 if (offset > rman_get_size(sc->mem_res)) 401 return (EINVAL); 402 if (!sc->mmap_allow_write && (nprot & PROT_WRITE)) 403 return (EPERM); 404 *paddr = rman_get_start(sc->mem_res) + offset; 405 *memattr = VM_MEMATTR_UNCACHEABLE; 406 407 return (0); 408 } 409 410 /* Discover the HPET via the ACPI table of the same name. */ 411 static void 412 hpet_identify(driver_t *driver, device_t parent) 413 { 414 ACPI_TABLE_HPET *hpet; 415 ACPI_STATUS status; 416 device_t child; 417 int i; 418 419 /* Only one HPET device can be added. */ 420 if (devclass_get_device(hpet_devclass, 0)) 421 return; 422 for (i = 1; ; i++) { 423 /* Search for HPET table. */ 424 status = AcpiGetTable(ACPI_SIG_HPET, i, (ACPI_TABLE_HEADER **)&hpet); 425 if (ACPI_FAILURE(status)) 426 return; 427 /* Search for HPET device with same ID. */ 428 child = NULL; 429 AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT, 430 100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence, 431 (void *)&child); 432 /* If found - let it be probed in normal way. */ 433 if (child) { 434 if (bus_get_resource(child, SYS_RES_MEMORY, 0, 435 NULL, NULL) != 0) 436 bus_set_resource(child, SYS_RES_MEMORY, 0, 437 hpet->Address.Address, HPET_MEM_WIDTH); 438 continue; 439 } 440 /* If not - create it from table info. */ 441 child = BUS_ADD_CHILD(parent, 2, "hpet", 0); 442 if (child == NULL) { 443 printf("%s: can't add child\n", __func__); 444 continue; 445 } 446 bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address, 447 HPET_MEM_WIDTH); 448 } 449 } 450 451 static int 452 hpet_probe(device_t dev) 453 { 454 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 455 456 if (acpi_disabled("hpet") || acpi_hpet_disabled) 457 return (ENXIO); 458 if (acpi_get_handle(dev) != NULL && 459 ACPI_ID_PROBE(device_get_parent(dev), dev, hpet_ids) == NULL) 460 return (ENXIO); 461 462 device_set_desc(dev, "High Precision Event Timer"); 463 return (0); 464 } 465 466 static int 467 hpet_attach(device_t dev) 468 { 469 struct hpet_softc *sc; 470 struct hpet_timer *t; 471 struct make_dev_args mda; 472 int i, j, num_msi, num_timers, num_percpu_et, num_percpu_t, cur_cpu; 473 int pcpu_master, error; 474 static int maxhpetet = 0; 475 uint32_t val, val2, cvectors, dvectors; 476 uint16_t vendor, rev; 477 478 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 479 480 sc = device_get_softc(dev); 481 sc->dev = dev; 482 sc->handle = acpi_get_handle(dev); 483 484 sc->mem_rid = 0; 485 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 486 RF_ACTIVE); 487 if (sc->mem_res == NULL) 488 return (ENOMEM); 489 490 /* Validate that we can access the whole region. */ 491 if (rman_get_size(sc->mem_res) < HPET_MEM_WIDTH) { 492 device_printf(dev, "memory region width %jd too small\n", 493 rman_get_size(sc->mem_res)); 494 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 495 return (ENXIO); 496 } 497 498 /* Be sure timer is enabled. */ 499 hpet_enable(sc); 500 501 /* Read basic statistics about the timer. */ 502 val = bus_read_4(sc->mem_res, HPET_PERIOD); 503 if (val == 0) { 504 device_printf(dev, "invalid period\n"); 505 hpet_disable(sc); 506 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 507 return (ENXIO); 508 } 509 510 sc->freq = (1000000000000000LL + val / 2) / val; 511 sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES); 512 vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16; 513 rev = sc->caps & HPET_CAP_REV_ID; 514 num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8); 515 /* 516 * ATI/AMD violates IA-PC HPET (High Precision Event Timers) 517 * Specification and provides an off by one number 518 * of timers/comparators. 519 * Additionally, they use unregistered value in VENDOR_ID field. 520 */ 521 if (vendor == HPET_VENDID_AMD && rev < 0x10 && num_timers > 0) 522 num_timers--; 523 sc->num_timers = num_timers; 524 if (bootverbose) { 525 device_printf(dev, 526 "vendor 0x%x, rev 0x%x, %jdHz%s, %d timers,%s\n", 527 vendor, rev, sc->freq, 528 (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "", 529 num_timers, 530 (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : ""); 531 } 532 for (i = 0; i < num_timers; i++) { 533 t = &sc->t[i]; 534 t->sc = sc; 535 t->num = i; 536 t->mode = TIMER_STOPPED; 537 t->intr_rid = -1; 538 t->irq = -1; 539 t->pcpu_cpu = -1; 540 t->pcpu_misrouted = 0; 541 t->pcpu_master = -1; 542 t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i)); 543 t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4); 544 if (bootverbose) { 545 device_printf(dev, 546 " t%d: irqs 0x%08x (%d)%s%s%s\n", i, 547 t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9, 548 (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "", 549 (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "", 550 (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : ""); 551 } 552 } 553 if (testenv("debug.acpi.hpet_test")) 554 hpet_test(sc); 555 /* 556 * Don't attach if the timer never increments. Since the spec 557 * requires it to be at least 10 MHz, it has to change in 1 us. 558 */ 559 val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 560 DELAY(1); 561 val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 562 if (val == val2) { 563 device_printf(dev, "HPET never increments, disabling\n"); 564 hpet_disable(sc); 565 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 566 return (ENXIO); 567 } 568 /* Announce first HPET as timecounter. */ 569 if (device_get_unit(dev) == 0) { 570 sc->tc.tc_get_timecount = hpet_get_timecount, 571 sc->tc.tc_counter_mask = ~0u, 572 sc->tc.tc_name = "HPET", 573 sc->tc.tc_quality = 950, 574 sc->tc.tc_frequency = sc->freq; 575 sc->tc.tc_priv = sc; 576 sc->tc.tc_fill_vdso_timehands = hpet_vdso_timehands; 577 #ifdef COMPAT_FREEBSD32 578 sc->tc.tc_fill_vdso_timehands32 = hpet_vdso_timehands32; 579 #endif 580 tc_init(&sc->tc); 581 } 582 /* If not disabled - setup and announce event timers. */ 583 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 584 "clock", &i) == 0 && i == 0) 585 return (0); 586 587 /* Check whether we can and want legacy routing. */ 588 sc->legacy_route = 0; 589 resource_int_value(device_get_name(dev), device_get_unit(dev), 590 "legacy_route", &sc->legacy_route); 591 if ((sc->caps & HPET_CAP_LEG_RT) == 0) 592 sc->legacy_route = 0; 593 if (sc->legacy_route) { 594 sc->t[0].vectors = 0; 595 sc->t[1].vectors = 0; 596 } 597 598 /* Check what IRQs we want use. */ 599 /* By default allow any PCI IRQs. */ 600 sc->allowed_irqs = 0xffff0000; 601 /* 602 * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16 603 * Lower are also not always working for different reasons. 604 * SB800 fixed it, but seems do not implements level triggering 605 * properly, that makes it very unreliable - it freezes after any 606 * interrupt loss. Avoid legacy IRQs for AMD. 607 */ 608 if (vendor == HPET_VENDID_AMD || vendor == HPET_VENDID_AMD2) 609 sc->allowed_irqs = 0x00000000; 610 /* 611 * NVidia MCP5x chipsets have number of unexplained interrupt 612 * problems. For some reason, using HPET interrupts breaks HDA sound. 613 */ 614 if (vendor == HPET_VENDID_NVIDIA && rev <= 0x01) 615 sc->allowed_irqs = 0x00000000; 616 /* 617 * ServerWorks HT1000 reported to have problems with IRQs >= 16. 618 * Lower IRQs are working, but allowed mask is not set correctly. 619 * Legacy_route mode works fine. 620 */ 621 if (vendor == HPET_VENDID_SW && rev <= 0x01) 622 sc->allowed_irqs = 0x00000000; 623 /* 624 * Neither QEMU nor VirtualBox report supported IRQs correctly. 625 * The only way to use HPET there is to specify IRQs manually 626 * and/or use legacy_route. Legacy_route mode works on both. 627 */ 628 if (vm_guest) 629 sc->allowed_irqs = 0x00000000; 630 /* Let user override. */ 631 resource_int_value(device_get_name(dev), device_get_unit(dev), 632 "allowed_irqs", &sc->allowed_irqs); 633 634 /* Get how much per-CPU timers we should try to provide. */ 635 sc->per_cpu = 1; 636 resource_int_value(device_get_name(dev), device_get_unit(dev), 637 "per_cpu", &sc->per_cpu); 638 639 num_msi = 0; 640 sc->useirq = 0; 641 /* Find IRQ vectors for all timers. */ 642 cvectors = sc->allowed_irqs & 0xffff0000; 643 dvectors = sc->allowed_irqs & 0x0000ffff; 644 if (sc->legacy_route) 645 dvectors &= 0x0000fefe; 646 for (i = 0; i < num_timers; i++) { 647 t = &sc->t[i]; 648 if (sc->legacy_route && i < 2) 649 t->irq = (i == 0) ? 0 : 8; 650 #ifdef DEV_APIC 651 else if (t->caps & HPET_TCAP_FSB_INT_DEL) { 652 if ((j = PCIB_ALLOC_MSIX( 653 device_get_parent(device_get_parent(dev)), dev, 654 &t->irq))) { 655 device_printf(dev, 656 "Can't allocate interrupt for t%d: %d\n", 657 i, j); 658 } 659 } 660 #endif 661 else if (dvectors & t->vectors) { 662 t->irq = ffs(dvectors & t->vectors) - 1; 663 dvectors &= ~(1 << t->irq); 664 } 665 if (t->irq >= 0) { 666 t->intr_rid = hpet_find_irq_rid(dev, t->irq, t->irq); 667 t->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 668 &t->intr_rid, t->irq, t->irq, 1, RF_ACTIVE); 669 if (t->intr_res == NULL) { 670 t->irq = -1; 671 device_printf(dev, 672 "Can't map interrupt for t%d.\n", i); 673 } else if (bus_setup_intr(dev, t->intr_res, 674 INTR_TYPE_CLK, hpet_intr_single, NULL, t, 675 &t->intr_handle) != 0) { 676 t->irq = -1; 677 device_printf(dev, 678 "Can't setup interrupt for t%d.\n", i); 679 } else { 680 bus_describe_intr(dev, t->intr_res, 681 t->intr_handle, "t%d", i); 682 num_msi++; 683 } 684 } 685 if (t->irq < 0 && (cvectors & t->vectors) != 0) { 686 cvectors &= t->vectors; 687 sc->useirq |= (1 << i); 688 } 689 } 690 if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0) 691 sc->legacy_route = 0; 692 if (sc->legacy_route) 693 hpet_enable(sc); 694 /* Group timers for per-CPU operation. */ 695 num_percpu_et = min(num_msi / mp_ncpus, sc->per_cpu); 696 num_percpu_t = num_percpu_et * mp_ncpus; 697 pcpu_master = 0; 698 cur_cpu = CPU_FIRST(); 699 for (i = 0; i < num_timers; i++) { 700 t = &sc->t[i]; 701 if (t->irq >= 0 && num_percpu_t > 0) { 702 if (cur_cpu == CPU_FIRST()) 703 pcpu_master = i; 704 t->pcpu_cpu = cur_cpu; 705 t->pcpu_master = pcpu_master; 706 sc->t[pcpu_master]. 707 pcpu_slaves[cur_cpu] = i; 708 bus_bind_intr(dev, t->intr_res, cur_cpu); 709 cur_cpu = CPU_NEXT(cur_cpu); 710 num_percpu_t--; 711 } else if (t->irq >= 0) 712 bus_bind_intr(dev, t->intr_res, CPU_FIRST()); 713 } 714 bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff); 715 sc->irq = -1; 716 /* If at least one timer needs legacy IRQ - set it up. */ 717 if (sc->useirq) { 718 j = i = fls(cvectors) - 1; 719 while (j > 0 && (cvectors & (1 << (j - 1))) != 0) 720 j--; 721 sc->intr_rid = hpet_find_irq_rid(dev, j, i); 722 sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 723 &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE); 724 if (sc->intr_res == NULL) 725 device_printf(dev, "Can't map interrupt.\n"); 726 else if (bus_setup_intr(dev, sc->intr_res, INTR_TYPE_CLK, 727 hpet_intr, NULL, sc, &sc->intr_handle) != 0) { 728 device_printf(dev, "Can't setup interrupt.\n"); 729 } else { 730 sc->irq = rman_get_start(sc->intr_res); 731 /* Bind IRQ to BSP to avoid live migration. */ 732 bus_bind_intr(dev, sc->intr_res, CPU_FIRST()); 733 } 734 } 735 /* Program and announce event timers. */ 736 for (i = 0; i < num_timers; i++) { 737 t = &sc->t[i]; 738 t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE); 739 t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB); 740 t->caps &= ~(HPET_TCNF_INT_TYPE); 741 t->caps |= HPET_TCNF_32MODE; 742 if (t->irq >= 0 && sc->legacy_route && i < 2) { 743 /* Legacy route doesn't need more configuration. */ 744 } else 745 #ifdef DEV_APIC 746 if ((t->caps & HPET_TCAP_FSB_INT_DEL) && t->irq >= 0) { 747 uint64_t addr; 748 uint32_t data; 749 750 if (PCIB_MAP_MSI( 751 device_get_parent(device_get_parent(dev)), dev, 752 t->irq, &addr, &data) == 0) { 753 bus_write_4(sc->mem_res, 754 HPET_TIMER_FSB_ADDR(i), addr); 755 bus_write_4(sc->mem_res, 756 HPET_TIMER_FSB_VAL(i), data); 757 t->caps |= HPET_TCNF_FSB_EN; 758 } else 759 t->irq = -2; 760 } else 761 #endif 762 if (t->irq >= 0) 763 t->caps |= (t->irq << 9); 764 else if (sc->irq >= 0 && (t->vectors & (1 << sc->irq))) 765 t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE; 766 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps); 767 /* Skip event timers without set up IRQ. */ 768 if (t->irq < 0 && 769 (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0)) 770 continue; 771 /* Announce the reset. */ 772 if (maxhpetet == 0) 773 t->et.et_name = "HPET"; 774 else { 775 sprintf(t->name, "HPET%d", maxhpetet); 776 t->et.et_name = t->name; 777 } 778 t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; 779 t->et.et_quality = 450; 780 if (t->pcpu_master >= 0) { 781 t->et.et_flags |= ET_FLAGS_PERCPU; 782 t->et.et_quality += 100; 783 } else if (mp_ncpus >= 8) 784 t->et.et_quality -= 100; 785 if ((t->caps & HPET_TCAP_PER_INT) == 0) 786 t->et.et_quality -= 10; 787 t->et.et_frequency = sc->freq; 788 t->et.et_min_period = 789 ((uint64_t)(HPET_MIN_CYCLES * 2) << 32) / sc->freq; 790 t->et.et_max_period = (0xfffffffeLLU << 32) / sc->freq; 791 t->et.et_start = hpet_start; 792 t->et.et_stop = hpet_stop; 793 t->et.et_priv = &sc->t[i]; 794 if (t->pcpu_master < 0 || t->pcpu_master == i) { 795 et_register(&t->et); 796 maxhpetet++; 797 } 798 } 799 acpi_GetInteger(sc->handle, "_UID", &sc->acpi_uid); 800 801 make_dev_args_init(&mda); 802 mda.mda_devsw = &hpet_cdevsw; 803 mda.mda_uid = UID_ROOT; 804 mda.mda_gid = GID_WHEEL; 805 mda.mda_mode = 0644; 806 mda.mda_si_drv1 = sc; 807 error = make_dev_s(&mda, &sc->pdev, "hpet%d", device_get_unit(dev)); 808 if (error == 0) { 809 sc->mmap_allow = 1; 810 TUNABLE_INT_FETCH("hw.acpi.hpet.mmap_allow", 811 &sc->mmap_allow); 812 sc->mmap_allow_write = 0; 813 TUNABLE_INT_FETCH("hw.acpi.hpet.mmap_allow_write", 814 &sc->mmap_allow_write); 815 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 816 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 817 OID_AUTO, "mmap_allow", 818 CTLFLAG_RW, &sc->mmap_allow, 0, 819 "Allow userland to memory map HPET"); 820 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 821 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 822 OID_AUTO, "mmap_allow_write", 823 CTLFLAG_RW, &sc->mmap_allow_write, 0, 824 "Allow userland write to the HPET register space"); 825 } else { 826 device_printf(dev, "could not create /dev/hpet%d, error %d\n", 827 device_get_unit(dev), error); 828 } 829 830 return (0); 831 } 832 833 static int 834 hpet_detach(device_t dev) 835 { 836 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 837 838 /* XXX Without a tc_remove() function, we can't detach. */ 839 return (EBUSY); 840 } 841 842 static int 843 hpet_suspend(device_t dev) 844 { 845 // struct hpet_softc *sc; 846 847 /* 848 * Disable the timer during suspend. The timer will not lose 849 * its state in S1 or S2, but we are required to disable 850 * it. 851 */ 852 // sc = device_get_softc(dev); 853 // hpet_disable(sc); 854 855 return (0); 856 } 857 858 static int 859 hpet_resume(device_t dev) 860 { 861 struct hpet_softc *sc; 862 struct hpet_timer *t; 863 int i; 864 865 /* Re-enable the timer after a resume to keep the clock advancing. */ 866 sc = device_get_softc(dev); 867 hpet_enable(sc); 868 /* Restart event timers that were running on suspend. */ 869 for (i = 0; i < sc->num_timers; i++) { 870 t = &sc->t[i]; 871 #ifdef DEV_APIC 872 if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) { 873 uint64_t addr; 874 uint32_t data; 875 876 if (PCIB_MAP_MSI( 877 device_get_parent(device_get_parent(dev)), dev, 878 t->irq, &addr, &data) == 0) { 879 bus_write_4(sc->mem_res, 880 HPET_TIMER_FSB_ADDR(i), addr); 881 bus_write_4(sc->mem_res, 882 HPET_TIMER_FSB_VAL(i), data); 883 } 884 } 885 #endif 886 if (t->mode == TIMER_STOPPED) 887 continue; 888 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 889 if (t->mode == TIMER_PERIODIC && 890 (t->caps & HPET_TCAP_PER_INT) != 0) { 891 t->caps |= HPET_TCNF_TYPE; 892 t->next += t->div; 893 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 894 t->caps | HPET_TCNF_VAL_SET); 895 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 896 t->next); 897 bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); 898 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 899 t->div); 900 } else { 901 t->next += sc->freq / 1024; 902 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 903 t->next); 904 } 905 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 906 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 907 } 908 return (0); 909 } 910 911 /* Print some basic latency/rate information to assist in debugging. */ 912 static void 913 hpet_test(struct hpet_softc *sc) 914 { 915 int i; 916 uint32_t u1, u2; 917 struct bintime b0, b1, b2; 918 struct timespec ts; 919 920 binuptime(&b0); 921 binuptime(&b0); 922 binuptime(&b1); 923 u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 924 for (i = 1; i < 1000; i++) 925 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 926 binuptime(&b2); 927 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 928 929 bintime_sub(&b2, &b1); 930 bintime_sub(&b1, &b0); 931 bintime_sub(&b2, &b1); 932 bintime2timespec(&b2, &ts); 933 934 device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n", 935 (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1); 936 937 device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000); 938 } 939 940 #ifdef DEV_APIC 941 static int 942 hpet_remap_intr(device_t dev, device_t child, u_int irq) 943 { 944 struct hpet_softc *sc = device_get_softc(dev); 945 struct hpet_timer *t; 946 uint64_t addr; 947 uint32_t data; 948 int error, i; 949 950 for (i = 0; i < sc->num_timers; i++) { 951 t = &sc->t[i]; 952 if (t->irq != irq) 953 continue; 954 error = PCIB_MAP_MSI( 955 device_get_parent(device_get_parent(dev)), dev, 956 irq, &addr, &data); 957 if (error) 958 return (error); 959 hpet_disable(sc); /* Stop timer to avoid interrupt loss. */ 960 bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr); 961 bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data); 962 hpet_enable(sc); 963 return (0); 964 } 965 return (ENOENT); 966 } 967 #endif 968 969 static device_method_t hpet_methods[] = { 970 /* Device interface */ 971 DEVMETHOD(device_identify, hpet_identify), 972 DEVMETHOD(device_probe, hpet_probe), 973 DEVMETHOD(device_attach, hpet_attach), 974 DEVMETHOD(device_detach, hpet_detach), 975 DEVMETHOD(device_suspend, hpet_suspend), 976 DEVMETHOD(device_resume, hpet_resume), 977 978 #ifdef DEV_APIC 979 DEVMETHOD(bus_remap_intr, hpet_remap_intr), 980 #endif 981 982 DEVMETHOD_END 983 }; 984 985 static driver_t hpet_driver = { 986 "hpet", 987 hpet_methods, 988 sizeof(struct hpet_softc), 989 }; 990 991 DRIVER_MODULE(hpet, acpi, hpet_driver, hpet_devclass, 0, 0); 992 MODULE_DEPEND(hpet, acpi, 1, 1, 1);
Cache object: ed6c077aab408742d79a355b0faea29d
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