Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/dev/acpica/acpi_hpet.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /*- 2 * Copyright (c) 2005 Poul-Henning Kamp 3 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD: releng/12.0/sys/dev/acpica/acpi_hpet.c 333209 2018-05-03 13:14:31Z avg $"); 30 31 #include "opt_acpi.h" 32 33 #if defined(__amd64__) 34 #define DEV_APIC 35 #else 36 #include "opt_apic.h" 37 #endif 38 #include <sys/param.h> 39 #include <sys/conf.h> 40 #include <sys/bus.h> 41 #include <sys/kernel.h> 42 #include <sys/module.h> 43 #include <sys/proc.h> 44 #include <sys/rman.h> 45 #include <sys/mman.h> 46 #include <sys/time.h> 47 #include <sys/smp.h> 48 #include <sys/sysctl.h> 49 #include <sys/timeet.h> 50 #include <sys/timetc.h> 51 #include <sys/vdso.h> 52 53 #include <contrib/dev/acpica/include/acpi.h> 54 #include <contrib/dev/acpica/include/accommon.h> 55 56 #include <dev/acpica/acpivar.h> 57 #include <dev/acpica/acpi_hpet.h> 58 59 #ifdef DEV_APIC 60 #include "pcib_if.h" 61 #endif 62 63 #define HPET_VENDID_AMD 0x4353 64 #define HPET_VENDID_AMD2 0x1022 65 #define HPET_VENDID_INTEL 0x8086 66 #define HPET_VENDID_NVIDIA 0x10de 67 #define HPET_VENDID_SW 0x1166 68 69 ACPI_SERIAL_DECL(hpet, "ACPI HPET support"); 70 71 static devclass_t hpet_devclass; 72 73 /* ACPI CA debugging */ 74 #define _COMPONENT ACPI_TIMER 75 ACPI_MODULE_NAME("HPET") 76 77 struct hpet_softc { 78 device_t dev; 79 int mem_rid; 80 int intr_rid; 81 int irq; 82 int useirq; 83 int legacy_route; 84 int per_cpu; 85 uint32_t allowed_irqs; 86 struct resource *mem_res; 87 struct resource *intr_res; 88 void *intr_handle; 89 ACPI_HANDLE handle; 90 uint32_t acpi_uid; 91 uint64_t freq; 92 uint32_t caps; 93 struct timecounter tc; 94 struct hpet_timer { 95 struct eventtimer et; 96 struct hpet_softc *sc; 97 int num; 98 int mode; 99 #define TIMER_STOPPED 0 100 #define TIMER_PERIODIC 1 101 #define TIMER_ONESHOT 2 102 int intr_rid; 103 int irq; 104 int pcpu_cpu; 105 int pcpu_misrouted; 106 int pcpu_master; 107 int pcpu_slaves[MAXCPU]; 108 struct resource *intr_res; 109 void *intr_handle; 110 uint32_t caps; 111 uint32_t vectors; 112 uint32_t div; 113 uint32_t next; 114 char name[8]; 115 } t[32]; 116 int num_timers; 117 struct cdev *pdev; 118 int mmap_allow; 119 int mmap_allow_write; 120 }; 121 122 static d_open_t hpet_open; 123 static d_mmap_t hpet_mmap; 124 125 static struct cdevsw hpet_cdevsw = { 126 .d_version = D_VERSION, 127 .d_name = "hpet", 128 .d_open = hpet_open, 129 .d_mmap = hpet_mmap, 130 }; 131 132 static u_int hpet_get_timecount(struct timecounter *tc); 133 static void hpet_test(struct hpet_softc *sc); 134 135 static char *hpet_ids[] = { "PNP0103", NULL }; 136 137 /* Knob to disable acpi_hpet device */ 138 bool acpi_hpet_disabled = false; 139 140 static u_int 141 hpet_get_timecount(struct timecounter *tc) 142 { 143 struct hpet_softc *sc; 144 145 sc = tc->tc_priv; 146 return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER)); 147 } 148 149 uint32_t 150 hpet_vdso_timehands(struct vdso_timehands *vdso_th, struct timecounter *tc) 151 { 152 struct hpet_softc *sc; 153 154 sc = tc->tc_priv; 155 vdso_th->th_algo = VDSO_TH_ALGO_X86_HPET; 156 vdso_th->th_x86_shift = 0; 157 vdso_th->th_x86_hpet_idx = device_get_unit(sc->dev); 158 bzero(vdso_th->th_res, sizeof(vdso_th->th_res)); 159 return (sc->mmap_allow != 0); 160 } 161 162 #ifdef COMPAT_FREEBSD32 163 uint32_t 164 hpet_vdso_timehands32(struct vdso_timehands32 *vdso_th32, 165 struct timecounter *tc) 166 { 167 struct hpet_softc *sc; 168 169 sc = tc->tc_priv; 170 vdso_th32->th_algo = VDSO_TH_ALGO_X86_HPET; 171 vdso_th32->th_x86_shift = 0; 172 vdso_th32->th_x86_hpet_idx = device_get_unit(sc->dev); 173 bzero(vdso_th32->th_res, sizeof(vdso_th32->th_res)); 174 return (sc->mmap_allow != 0); 175 } 176 #endif 177 178 static void 179 hpet_enable(struct hpet_softc *sc) 180 { 181 uint32_t val; 182 183 val = bus_read_4(sc->mem_res, HPET_CONFIG); 184 if (sc->legacy_route) 185 val |= HPET_CNF_LEG_RT; 186 else 187 val &= ~HPET_CNF_LEG_RT; 188 val |= HPET_CNF_ENABLE; 189 bus_write_4(sc->mem_res, HPET_CONFIG, val); 190 } 191 192 static void 193 hpet_disable(struct hpet_softc *sc) 194 { 195 uint32_t val; 196 197 val = bus_read_4(sc->mem_res, HPET_CONFIG); 198 val &= ~HPET_CNF_ENABLE; 199 bus_write_4(sc->mem_res, HPET_CONFIG, val); 200 } 201 202 static int 203 hpet_start(struct eventtimer *et, sbintime_t first, sbintime_t period) 204 { 205 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 206 struct hpet_timer *t; 207 struct hpet_softc *sc = mt->sc; 208 uint32_t fdiv, now; 209 210 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 211 if (period != 0) { 212 t->mode = TIMER_PERIODIC; 213 t->div = (sc->freq * period) >> 32; 214 } else { 215 t->mode = TIMER_ONESHOT; 216 t->div = 0; 217 } 218 if (first != 0) 219 fdiv = (sc->freq * first) >> 32; 220 else 221 fdiv = t->div; 222 if (t->irq < 0) 223 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 224 t->caps |= HPET_TCNF_INT_ENB; 225 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 226 restart: 227 t->next = now + fdiv; 228 if (t->mode == TIMER_PERIODIC && (t->caps & HPET_TCAP_PER_INT)) { 229 t->caps |= HPET_TCNF_TYPE; 230 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 231 t->caps | HPET_TCNF_VAL_SET); 232 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 233 t->next); 234 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 235 t->div); 236 } else { 237 t->caps &= ~HPET_TCNF_TYPE; 238 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 239 t->caps); 240 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 241 t->next); 242 } 243 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 244 if ((int32_t)(now - t->next + HPET_MIN_CYCLES) >= 0) { 245 fdiv *= 2; 246 goto restart; 247 } 248 return (0); 249 } 250 251 static int 252 hpet_stop(struct eventtimer *et) 253 { 254 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv; 255 struct hpet_timer *t; 256 struct hpet_softc *sc = mt->sc; 257 258 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]]; 259 t->mode = TIMER_STOPPED; 260 t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE); 261 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 262 return (0); 263 } 264 265 static int 266 hpet_intr_single(void *arg) 267 { 268 struct hpet_timer *t = (struct hpet_timer *)arg; 269 struct hpet_timer *mt; 270 struct hpet_softc *sc = t->sc; 271 uint32_t now; 272 273 if (t->mode == TIMER_STOPPED) 274 return (FILTER_STRAY); 275 /* Check that per-CPU timer interrupt reached right CPU. */ 276 if (t->pcpu_cpu >= 0 && t->pcpu_cpu != curcpu) { 277 if ((++t->pcpu_misrouted) % 32 == 0) { 278 printf("HPET interrupt routed to the wrong CPU" 279 " (timer %d CPU %d -> %d)!\n", 280 t->num, t->pcpu_cpu, curcpu); 281 } 282 283 /* 284 * Reload timer, hoping that next time may be more lucky 285 * (system will manage proper interrupt binding). 286 */ 287 if ((t->mode == TIMER_PERIODIC && 288 (t->caps & HPET_TCAP_PER_INT) == 0) || 289 t->mode == TIMER_ONESHOT) { 290 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER) + 291 sc->freq / 8; 292 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 293 t->next); 294 } 295 return (FILTER_HANDLED); 296 } 297 if (t->mode == TIMER_PERIODIC && 298 (t->caps & HPET_TCAP_PER_INT) == 0) { 299 t->next += t->div; 300 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 301 if ((int32_t)((now + t->div / 2) - t->next) > 0) 302 t->next = now + t->div / 2; 303 bus_write_4(sc->mem_res, 304 HPET_TIMER_COMPARATOR(t->num), t->next); 305 } else if (t->mode == TIMER_ONESHOT) 306 t->mode = TIMER_STOPPED; 307 mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master]; 308 if (mt->et.et_active) 309 mt->et.et_event_cb(&mt->et, mt->et.et_arg); 310 return (FILTER_HANDLED); 311 } 312 313 static int 314 hpet_intr(void *arg) 315 { 316 struct hpet_softc *sc = (struct hpet_softc *)arg; 317 int i; 318 uint32_t val; 319 320 val = bus_read_4(sc->mem_res, HPET_ISR); 321 if (val) { 322 bus_write_4(sc->mem_res, HPET_ISR, val); 323 val &= sc->useirq; 324 for (i = 0; i < sc->num_timers; i++) { 325 if ((val & (1 << i)) == 0) 326 continue; 327 hpet_intr_single(&sc->t[i]); 328 } 329 return (FILTER_HANDLED); 330 } 331 return (FILTER_STRAY); 332 } 333 334 uint32_t 335 hpet_get_uid(device_t dev) 336 { 337 struct hpet_softc *sc; 338 339 sc = device_get_softc(dev); 340 return (sc->acpi_uid); 341 } 342 343 static ACPI_STATUS 344 hpet_find(ACPI_HANDLE handle, UINT32 level, void *context, 345 void **status) 346 { 347 char **ids; 348 uint32_t id = (uint32_t)(uintptr_t)context; 349 uint32_t uid = 0; 350 351 for (ids = hpet_ids; *ids != NULL; ids++) { 352 if (acpi_MatchHid(handle, *ids)) 353 break; 354 } 355 if (*ids == NULL) 356 return (AE_OK); 357 if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &uid)) || 358 id == uid) 359 *status = acpi_get_device(handle); 360 return (AE_OK); 361 } 362 363 /* 364 * Find an existing IRQ resource that matches the requested IRQ range 365 * and return its RID. If one is not found, use a new RID. 366 */ 367 static int 368 hpet_find_irq_rid(device_t dev, u_long start, u_long end) 369 { 370 rman_res_t irq; 371 int error, rid; 372 373 for (rid = 0;; rid++) { 374 error = bus_get_resource(dev, SYS_RES_IRQ, rid, &irq, NULL); 375 if (error != 0 || (start <= irq && irq <= end)) 376 return (rid); 377 } 378 } 379 380 static int 381 hpet_open(struct cdev *cdev, int oflags, int devtype, struct thread *td) 382 { 383 struct hpet_softc *sc; 384 385 sc = cdev->si_drv1; 386 if (!sc->mmap_allow) 387 return (EPERM); 388 else 389 return (0); 390 } 391 392 static int 393 hpet_mmap(struct cdev *cdev, vm_ooffset_t offset, vm_paddr_t *paddr, 394 int nprot, vm_memattr_t *memattr) 395 { 396 struct hpet_softc *sc; 397 398 sc = cdev->si_drv1; 399 if (offset > rman_get_size(sc->mem_res)) 400 return (EINVAL); 401 if (!sc->mmap_allow_write && (nprot & PROT_WRITE)) 402 return (EPERM); 403 *paddr = rman_get_start(sc->mem_res) + offset; 404 *memattr = VM_MEMATTR_UNCACHEABLE; 405 406 return (0); 407 } 408 409 /* Discover the HPET via the ACPI table of the same name. */ 410 static void 411 hpet_identify(driver_t *driver, device_t parent) 412 { 413 ACPI_TABLE_HPET *hpet; 414 ACPI_STATUS status; 415 device_t child; 416 int i; 417 418 /* Only one HPET device can be added. */ 419 if (devclass_get_device(hpet_devclass, 0)) 420 return; 421 for (i = 1; ; i++) { 422 /* Search for HPET table. */ 423 status = AcpiGetTable(ACPI_SIG_HPET, i, (ACPI_TABLE_HEADER **)&hpet); 424 if (ACPI_FAILURE(status)) 425 return; 426 /* Search for HPET device with same ID. */ 427 child = NULL; 428 AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT, 429 100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence, 430 (void *)&child); 431 /* If found - let it be probed in normal way. */ 432 if (child) { 433 if (bus_get_resource(child, SYS_RES_MEMORY, 0, 434 NULL, NULL) != 0) 435 bus_set_resource(child, SYS_RES_MEMORY, 0, 436 hpet->Address.Address, HPET_MEM_WIDTH); 437 continue; 438 } 439 /* If not - create it from table info. */ 440 child = BUS_ADD_CHILD(parent, 2, "hpet", 0); 441 if (child == NULL) { 442 printf("%s: can't add child\n", __func__); 443 continue; 444 } 445 bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address, 446 HPET_MEM_WIDTH); 447 } 448 } 449 450 static int 451 hpet_probe(device_t dev) 452 { 453 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 454 455 if (acpi_disabled("hpet") || acpi_hpet_disabled) 456 return (ENXIO); 457 if (acpi_get_handle(dev) != NULL && 458 ACPI_ID_PROBE(device_get_parent(dev), dev, hpet_ids) == NULL) 459 return (ENXIO); 460 461 device_set_desc(dev, "High Precision Event Timer"); 462 return (0); 463 } 464 465 static int 466 hpet_attach(device_t dev) 467 { 468 struct hpet_softc *sc; 469 struct hpet_timer *t; 470 struct make_dev_args mda; 471 int i, j, num_msi, num_timers, num_percpu_et, num_percpu_t, cur_cpu; 472 int pcpu_master, error; 473 static int maxhpetet = 0; 474 uint32_t val, val2, cvectors, dvectors; 475 uint16_t vendor, rev; 476 477 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 478 479 sc = device_get_softc(dev); 480 sc->dev = dev; 481 sc->handle = acpi_get_handle(dev); 482 483 sc->mem_rid = 0; 484 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 485 RF_ACTIVE); 486 if (sc->mem_res == NULL) 487 return (ENOMEM); 488 489 /* Validate that we can access the whole region. */ 490 if (rman_get_size(sc->mem_res) < HPET_MEM_WIDTH) { 491 device_printf(dev, "memory region width %jd too small\n", 492 rman_get_size(sc->mem_res)); 493 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 494 return (ENXIO); 495 } 496 497 /* Be sure timer is enabled. */ 498 hpet_enable(sc); 499 500 /* Read basic statistics about the timer. */ 501 val = bus_read_4(sc->mem_res, HPET_PERIOD); 502 if (val == 0) { 503 device_printf(dev, "invalid period\n"); 504 hpet_disable(sc); 505 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 506 return (ENXIO); 507 } 508 509 sc->freq = (1000000000000000LL + val / 2) / val; 510 sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES); 511 vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16; 512 rev = sc->caps & HPET_CAP_REV_ID; 513 num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8); 514 /* 515 * ATI/AMD violates IA-PC HPET (High Precision Event Timers) 516 * Specification and provides an off by one number 517 * of timers/comparators. 518 * Additionally, they use unregistered value in VENDOR_ID field. 519 */ 520 if (vendor == HPET_VENDID_AMD && rev < 0x10 && num_timers > 0) 521 num_timers--; 522 sc->num_timers = num_timers; 523 if (bootverbose) { 524 device_printf(dev, 525 "vendor 0x%x, rev 0x%x, %jdHz%s, %d timers,%s\n", 526 vendor, rev, sc->freq, 527 (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "", 528 num_timers, 529 (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : ""); 530 } 531 for (i = 0; i < num_timers; i++) { 532 t = &sc->t[i]; 533 t->sc = sc; 534 t->num = i; 535 t->mode = TIMER_STOPPED; 536 t->intr_rid = -1; 537 t->irq = -1; 538 t->pcpu_cpu = -1; 539 t->pcpu_misrouted = 0; 540 t->pcpu_master = -1; 541 t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i)); 542 t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4); 543 if (bootverbose) { 544 device_printf(dev, 545 " t%d: irqs 0x%08x (%d)%s%s%s\n", i, 546 t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9, 547 (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "", 548 (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "", 549 (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : ""); 550 } 551 } 552 if (testenv("debug.acpi.hpet_test")) 553 hpet_test(sc); 554 /* 555 * Don't attach if the timer never increments. Since the spec 556 * requires it to be at least 10 MHz, it has to change in 1 us. 557 */ 558 val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 559 DELAY(1); 560 val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 561 if (val == val2) { 562 device_printf(dev, "HPET never increments, disabling\n"); 563 hpet_disable(sc); 564 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res); 565 return (ENXIO); 566 } 567 /* Announce first HPET as timecounter. */ 568 if (device_get_unit(dev) == 0) { 569 sc->tc.tc_get_timecount = hpet_get_timecount, 570 sc->tc.tc_counter_mask = ~0u, 571 sc->tc.tc_name = "HPET", 572 sc->tc.tc_quality = 950, 573 sc->tc.tc_frequency = sc->freq; 574 sc->tc.tc_priv = sc; 575 sc->tc.tc_fill_vdso_timehands = hpet_vdso_timehands; 576 #ifdef COMPAT_FREEBSD32 577 sc->tc.tc_fill_vdso_timehands32 = hpet_vdso_timehands32; 578 #endif 579 tc_init(&sc->tc); 580 } 581 /* If not disabled - setup and announce event timers. */ 582 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 583 "clock", &i) == 0 && i == 0) 584 return (0); 585 586 /* Check whether we can and want legacy routing. */ 587 sc->legacy_route = 0; 588 resource_int_value(device_get_name(dev), device_get_unit(dev), 589 "legacy_route", &sc->legacy_route); 590 if ((sc->caps & HPET_CAP_LEG_RT) == 0) 591 sc->legacy_route = 0; 592 if (sc->legacy_route) { 593 sc->t[0].vectors = 0; 594 sc->t[1].vectors = 0; 595 } 596 597 /* Check what IRQs we want use. */ 598 /* By default allow any PCI IRQs. */ 599 sc->allowed_irqs = 0xffff0000; 600 /* 601 * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16 602 * Lower are also not always working for different reasons. 603 * SB800 fixed it, but seems do not implements level triggering 604 * properly, that makes it very unreliable - it freezes after any 605 * interrupt loss. Avoid legacy IRQs for AMD. 606 */ 607 if (vendor == HPET_VENDID_AMD || vendor == HPET_VENDID_AMD2) 608 sc->allowed_irqs = 0x00000000; 609 /* 610 * NVidia MCP5x chipsets have number of unexplained interrupt 611 * problems. For some reason, using HPET interrupts breaks HDA sound. 612 */ 613 if (vendor == HPET_VENDID_NVIDIA && rev <= 0x01) 614 sc->allowed_irqs = 0x00000000; 615 /* 616 * ServerWorks HT1000 reported to have problems with IRQs >= 16. 617 * Lower IRQs are working, but allowed mask is not set correctly. 618 * Legacy_route mode works fine. 619 */ 620 if (vendor == HPET_VENDID_SW && rev <= 0x01) 621 sc->allowed_irqs = 0x00000000; 622 /* 623 * Neither QEMU nor VirtualBox report supported IRQs correctly. 624 * The only way to use HPET there is to specify IRQs manually 625 * and/or use legacy_route. Legacy_route mode works on both. 626 */ 627 if (vm_guest) 628 sc->allowed_irqs = 0x00000000; 629 /* Let user override. */ 630 resource_int_value(device_get_name(dev), device_get_unit(dev), 631 "allowed_irqs", &sc->allowed_irqs); 632 633 /* Get how much per-CPU timers we should try to provide. */ 634 sc->per_cpu = 1; 635 resource_int_value(device_get_name(dev), device_get_unit(dev), 636 "per_cpu", &sc->per_cpu); 637 638 num_msi = 0; 639 sc->useirq = 0; 640 /* Find IRQ vectors for all timers. */ 641 cvectors = sc->allowed_irqs & 0xffff0000; 642 dvectors = sc->allowed_irqs & 0x0000ffff; 643 if (sc->legacy_route) 644 dvectors &= 0x0000fefe; 645 for (i = 0; i < num_timers; i++) { 646 t = &sc->t[i]; 647 if (sc->legacy_route && i < 2) 648 t->irq = (i == 0) ? 0 : 8; 649 #ifdef DEV_APIC 650 else if (t->caps & HPET_TCAP_FSB_INT_DEL) { 651 if ((j = PCIB_ALLOC_MSIX( 652 device_get_parent(device_get_parent(dev)), dev, 653 &t->irq))) { 654 device_printf(dev, 655 "Can't allocate interrupt for t%d: %d\n", 656 i, j); 657 } 658 } 659 #endif 660 else if (dvectors & t->vectors) { 661 t->irq = ffs(dvectors & t->vectors) - 1; 662 dvectors &= ~(1 << t->irq); 663 } 664 if (t->irq >= 0) { 665 t->intr_rid = hpet_find_irq_rid(dev, t->irq, t->irq); 666 t->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 667 &t->intr_rid, t->irq, t->irq, 1, RF_ACTIVE); 668 if (t->intr_res == NULL) { 669 t->irq = -1; 670 device_printf(dev, 671 "Can't map interrupt for t%d.\n", i); 672 } else if (bus_setup_intr(dev, t->intr_res, 673 INTR_TYPE_CLK, hpet_intr_single, NULL, t, 674 &t->intr_handle) != 0) { 675 t->irq = -1; 676 device_printf(dev, 677 "Can't setup interrupt for t%d.\n", i); 678 } else { 679 bus_describe_intr(dev, t->intr_res, 680 t->intr_handle, "t%d", i); 681 num_msi++; 682 } 683 } 684 if (t->irq < 0 && (cvectors & t->vectors) != 0) { 685 cvectors &= t->vectors; 686 sc->useirq |= (1 << i); 687 } 688 } 689 if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0) 690 sc->legacy_route = 0; 691 if (sc->legacy_route) 692 hpet_enable(sc); 693 /* Group timers for per-CPU operation. */ 694 num_percpu_et = min(num_msi / mp_ncpus, sc->per_cpu); 695 num_percpu_t = num_percpu_et * mp_ncpus; 696 pcpu_master = 0; 697 cur_cpu = CPU_FIRST(); 698 for (i = 0; i < num_timers; i++) { 699 t = &sc->t[i]; 700 if (t->irq >= 0 && num_percpu_t > 0) { 701 if (cur_cpu == CPU_FIRST()) 702 pcpu_master = i; 703 t->pcpu_cpu = cur_cpu; 704 t->pcpu_master = pcpu_master; 705 sc->t[pcpu_master]. 706 pcpu_slaves[cur_cpu] = i; 707 bus_bind_intr(dev, t->intr_res, cur_cpu); 708 cur_cpu = CPU_NEXT(cur_cpu); 709 num_percpu_t--; 710 } else if (t->irq >= 0) 711 bus_bind_intr(dev, t->intr_res, CPU_FIRST()); 712 } 713 bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff); 714 sc->irq = -1; 715 /* If at least one timer needs legacy IRQ - set it up. */ 716 if (sc->useirq) { 717 j = i = fls(cvectors) - 1; 718 while (j > 0 && (cvectors & (1 << (j - 1))) != 0) 719 j--; 720 sc->intr_rid = hpet_find_irq_rid(dev, j, i); 721 sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ, 722 &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE); 723 if (sc->intr_res == NULL) 724 device_printf(dev, "Can't map interrupt.\n"); 725 else if (bus_setup_intr(dev, sc->intr_res, INTR_TYPE_CLK, 726 hpet_intr, NULL, sc, &sc->intr_handle) != 0) { 727 device_printf(dev, "Can't setup interrupt.\n"); 728 } else { 729 sc->irq = rman_get_start(sc->intr_res); 730 /* Bind IRQ to BSP to avoid live migration. */ 731 bus_bind_intr(dev, sc->intr_res, CPU_FIRST()); 732 } 733 } 734 /* Program and announce event timers. */ 735 for (i = 0; i < num_timers; i++) { 736 t = &sc->t[i]; 737 t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE); 738 t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB); 739 t->caps &= ~(HPET_TCNF_INT_TYPE); 740 t->caps |= HPET_TCNF_32MODE; 741 if (t->irq >= 0 && sc->legacy_route && i < 2) { 742 /* Legacy route doesn't need more configuration. */ 743 } else 744 #ifdef DEV_APIC 745 if ((t->caps & HPET_TCAP_FSB_INT_DEL) && t->irq >= 0) { 746 uint64_t addr; 747 uint32_t data; 748 749 if (PCIB_MAP_MSI( 750 device_get_parent(device_get_parent(dev)), dev, 751 t->irq, &addr, &data) == 0) { 752 bus_write_4(sc->mem_res, 753 HPET_TIMER_FSB_ADDR(i), addr); 754 bus_write_4(sc->mem_res, 755 HPET_TIMER_FSB_VAL(i), data); 756 t->caps |= HPET_TCNF_FSB_EN; 757 } else 758 t->irq = -2; 759 } else 760 #endif 761 if (t->irq >= 0) 762 t->caps |= (t->irq << 9); 763 else if (sc->irq >= 0 && (t->vectors & (1 << sc->irq))) 764 t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE; 765 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps); 766 /* Skip event timers without set up IRQ. */ 767 if (t->irq < 0 && 768 (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0)) 769 continue; 770 /* Announce the reset. */ 771 if (maxhpetet == 0) 772 t->et.et_name = "HPET"; 773 else { 774 sprintf(t->name, "HPET%d", maxhpetet); 775 t->et.et_name = t->name; 776 } 777 t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; 778 t->et.et_quality = 450; 779 if (t->pcpu_master >= 0) { 780 t->et.et_flags |= ET_FLAGS_PERCPU; 781 t->et.et_quality += 100; 782 } else if (mp_ncpus >= 8) 783 t->et.et_quality -= 100; 784 if ((t->caps & HPET_TCAP_PER_INT) == 0) 785 t->et.et_quality -= 10; 786 t->et.et_frequency = sc->freq; 787 t->et.et_min_period = 788 ((uint64_t)(HPET_MIN_CYCLES * 2) << 32) / sc->freq; 789 t->et.et_max_period = (0xfffffffeLLU << 32) / sc->freq; 790 t->et.et_start = hpet_start; 791 t->et.et_stop = hpet_stop; 792 t->et.et_priv = &sc->t[i]; 793 if (t->pcpu_master < 0 || t->pcpu_master == i) { 794 et_register(&t->et); 795 maxhpetet++; 796 } 797 } 798 acpi_GetInteger(sc->handle, "_UID", &sc->acpi_uid); 799 800 make_dev_args_init(&mda); 801 mda.mda_devsw = &hpet_cdevsw; 802 mda.mda_uid = UID_ROOT; 803 mda.mda_gid = GID_WHEEL; 804 mda.mda_mode = 0644; 805 mda.mda_si_drv1 = sc; 806 error = make_dev_s(&mda, &sc->pdev, "hpet%d", device_get_unit(dev)); 807 if (error == 0) { 808 sc->mmap_allow = 1; 809 TUNABLE_INT_FETCH("hw.acpi.hpet.mmap_allow", 810 &sc->mmap_allow); 811 sc->mmap_allow_write = 0; 812 TUNABLE_INT_FETCH("hw.acpi.hpet.mmap_allow_write", 813 &sc->mmap_allow_write); 814 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 815 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 816 OID_AUTO, "mmap_allow", 817 CTLFLAG_RW, &sc->mmap_allow, 0, 818 "Allow userland to memory map HPET"); 819 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 820 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 821 OID_AUTO, "mmap_allow_write", 822 CTLFLAG_RW, &sc->mmap_allow_write, 0, 823 "Allow userland write to the HPET register space"); 824 } else { 825 device_printf(dev, "could not create /dev/hpet%d, error %d\n", 826 device_get_unit(dev), error); 827 } 828 829 return (0); 830 } 831 832 static int 833 hpet_detach(device_t dev) 834 { 835 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__); 836 837 /* XXX Without a tc_remove() function, we can't detach. */ 838 return (EBUSY); 839 } 840 841 static int 842 hpet_suspend(device_t dev) 843 { 844 // struct hpet_softc *sc; 845 846 /* 847 * Disable the timer during suspend. The timer will not lose 848 * its state in S1 or S2, but we are required to disable 849 * it. 850 */ 851 // sc = device_get_softc(dev); 852 // hpet_disable(sc); 853 854 return (0); 855 } 856 857 static int 858 hpet_resume(device_t dev) 859 { 860 struct hpet_softc *sc; 861 struct hpet_timer *t; 862 int i; 863 864 /* Re-enable the timer after a resume to keep the clock advancing. */ 865 sc = device_get_softc(dev); 866 hpet_enable(sc); 867 /* Restart event timers that were running on suspend. */ 868 for (i = 0; i < sc->num_timers; i++) { 869 t = &sc->t[i]; 870 #ifdef DEV_APIC 871 if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) { 872 uint64_t addr; 873 uint32_t data; 874 875 if (PCIB_MAP_MSI( 876 device_get_parent(device_get_parent(dev)), dev, 877 t->irq, &addr, &data) == 0) { 878 bus_write_4(sc->mem_res, 879 HPET_TIMER_FSB_ADDR(i), addr); 880 bus_write_4(sc->mem_res, 881 HPET_TIMER_FSB_VAL(i), data); 882 } 883 } 884 #endif 885 if (t->mode == TIMER_STOPPED) 886 continue; 887 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 888 if (t->mode == TIMER_PERIODIC && 889 (t->caps & HPET_TCAP_PER_INT) != 0) { 890 t->caps |= HPET_TCNF_TYPE; 891 t->next += t->div; 892 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), 893 t->caps | HPET_TCNF_VAL_SET); 894 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 895 t->next); 896 bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num)); 897 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 898 t->div); 899 } else { 900 t->next += sc->freq / 1024; 901 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num), 902 t->next); 903 } 904 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num); 905 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps); 906 } 907 return (0); 908 } 909 910 /* Print some basic latency/rate information to assist in debugging. */ 911 static void 912 hpet_test(struct hpet_softc *sc) 913 { 914 int i; 915 uint32_t u1, u2; 916 struct bintime b0, b1, b2; 917 struct timespec ts; 918 919 binuptime(&b0); 920 binuptime(&b0); 921 binuptime(&b1); 922 u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 923 for (i = 1; i < 1000; i++) 924 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 925 binuptime(&b2); 926 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER); 927 928 bintime_sub(&b2, &b1); 929 bintime_sub(&b1, &b0); 930 bintime_sub(&b2, &b1); 931 bintime2timespec(&b2, &ts); 932 933 device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n", 934 (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1); 935 936 device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000); 937 } 938 939 #ifdef DEV_APIC 940 static int 941 hpet_remap_intr(device_t dev, device_t child, u_int irq) 942 { 943 struct hpet_softc *sc = device_get_softc(dev); 944 struct hpet_timer *t; 945 uint64_t addr; 946 uint32_t data; 947 int error, i; 948 949 for (i = 0; i < sc->num_timers; i++) { 950 t = &sc->t[i]; 951 if (t->irq != irq) 952 continue; 953 error = PCIB_MAP_MSI( 954 device_get_parent(device_get_parent(dev)), dev, 955 irq, &addr, &data); 956 if (error) 957 return (error); 958 hpet_disable(sc); /* Stop timer to avoid interrupt loss. */ 959 bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr); 960 bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data); 961 hpet_enable(sc); 962 return (0); 963 } 964 return (ENOENT); 965 } 966 #endif 967 968 static device_method_t hpet_methods[] = { 969 /* Device interface */ 970 DEVMETHOD(device_identify, hpet_identify), 971 DEVMETHOD(device_probe, hpet_probe), 972 DEVMETHOD(device_attach, hpet_attach), 973 DEVMETHOD(device_detach, hpet_detach), 974 DEVMETHOD(device_suspend, hpet_suspend), 975 DEVMETHOD(device_resume, hpet_resume), 976 977 #ifdef DEV_APIC 978 DEVMETHOD(bus_remap_intr, hpet_remap_intr), 979 #endif 980 981 DEVMETHOD_END 982 }; 983 984 static driver_t hpet_driver = { 985 "hpet", 986 hpet_methods, 987 sizeof(struct hpet_softc), 988 }; 989 990 DRIVER_MODULE(hpet, acpi, hpet_driver, hpet_devclass, 0, 0); 991 MODULE_DEPEND(hpet, acpi, 1, 1, 1);
Cache object: d976862e9b51db192ce08035b8b7493b
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]