Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/advansys/adv_pci.c
Version:
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1 /*- 2 * Device probe and attach routines for the following 3 * Advanced Systems Inc. SCSI controllers: 4 * 5 * Connectivity Products: 6 * ABP902/3902 - Bus-Master PCI (16 CDB) 7 * ABP3905 - Bus-Master PCI (16 CDB) 8 * ABP915 - Bus-Master PCI (16 CDB) 9 * ABP920 - Bus-Master PCI (16 CDB) 10 * ABP3922 - Bus-Master PCI (16 CDB) 11 * ABP3925 - Bus-Master PCI (16 CDB) 12 * ABP930 - Bus-Master PCI (16 CDB) * 13 * ABP930U - Bus-Master PCI Ultra (16 CDB) 14 * ABP930UA - Bus-Master PCI Ultra (16 CDB) 15 * ABP960 - Bus-Master PCI MAC/PC (16 CDB) ** 16 * ABP960U - Bus-Master PCI MAC/PC (16 CDB) ** 17 * 18 * Single Channel Products: 19 * ABP940 - Bus-Master PCI (240 CDB) 20 * ABP940U - Bus-Master PCI Ultra (240 CDB) 21 * ABP940UA/3940UA - Bus-Master PCI Ultra (240 CDB) 22 * ABP3960UA - Bus-Master PCI MAC/PC (240 CDB) 23 * ABP970 - Bus-Master PCI MAC/PC (240 CDB) 24 * ABP970U - Bus-Master PCI MAC/PC Ultra (240 CDB) 25 * 26 * Dual Channel Products: 27 * ABP950 - Dual Channel Bus-Master PCI (240 CDB Per Channel) 28 * ABP980 - Four Channel Bus-Master PCI (240 CDB Per Channel) 29 * ABP980U - Four Channel Bus-Master PCI Ultra (240 CDB Per Channel) 30 * ABP980UA/3980UA - Four Channel Bus-Master PCI Ultra (16 CDB Per Chan.) 31 * 32 * Footnotes: 33 * * This board has been sold by SIIG as the Fast SCSI Pro PCI. 34 * ** This board has been sold by Iomega as a Jaz Jet PCI adapter. 35 * 36 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 37 * 38 * Copyright (c) 1997 Justin Gibbs. 39 * All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions, and the following disclaimer, 46 * without modification. 47 * 2. The name of the author may not be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 51 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 52 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 53 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 54 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 55 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 56 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 57 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 58 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 59 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 60 * SUCH DAMAGE. 61 */ 62 63 #include <sys/cdefs.h> 64 __FBSDID("$FreeBSD$"); 65 66 #include <sys/param.h> 67 #include <sys/systm.h> 68 #include <sys/kernel.h> 69 #include <sys/lock.h> 70 #include <sys/module.h> 71 #include <sys/mutex.h> 72 73 #include <machine/bus.h> 74 #include <machine/resource.h> 75 #include <sys/bus.h> 76 #include <sys/rman.h> 77 78 #include <dev/pci/pcireg.h> 79 #include <dev/pci/pcivar.h> 80 81 #include <dev/advansys/advansys.h> 82 83 #define PCI_BASEADR0 PCIR_BAR(0) /* I/O Address */ 84 #define PCI_BASEADR1 PCIR_BAR(1) /* Mem I/O Address */ 85 86 #define PCI_DEVICE_ID_ADVANSYS_1200A 0x110010CD 87 #define PCI_DEVICE_ID_ADVANSYS_1200B 0x120010CD 88 #define PCI_DEVICE_ID_ADVANSYS_3000 0x130010CD 89 #define PCI_DEVICE_REV_ADVANSYS_3150 0x02 90 #define PCI_DEVICE_REV_ADVANSYS_3050 0x03 91 92 #define ADV_PCI_MAX_DMA_ADDR (0xFFFFFFFFL) 93 #define ADV_PCI_MAX_DMA_COUNT (0xFFFFFFFFL) 94 95 static int adv_pci_probe(device_t); 96 static int adv_pci_attach(device_t); 97 98 /* 99 * The overrun buffer shared amongst all PCI adapters. 100 */ 101 static void* overrun_buf; 102 static bus_dma_tag_t overrun_dmat; 103 static bus_dmamap_t overrun_dmamap; 104 static bus_addr_t overrun_physbase; 105 106 static int 107 adv_pci_probe(device_t dev) 108 { 109 int rev = pci_get_revid(dev); 110 111 switch (pci_get_devid(dev)) { 112 case PCI_DEVICE_ID_ADVANSYS_1200A: 113 device_set_desc(dev, "AdvanSys ASC1200A SCSI controller"); 114 return BUS_PROBE_DEFAULT; 115 case PCI_DEVICE_ID_ADVANSYS_1200B: 116 device_set_desc(dev, "AdvanSys ASC1200B SCSI controller"); 117 return BUS_PROBE_DEFAULT; 118 case PCI_DEVICE_ID_ADVANSYS_3000: 119 if (rev == PCI_DEVICE_REV_ADVANSYS_3150) { 120 device_set_desc(dev, 121 "AdvanSys ASC3150 SCSI controller"); 122 return BUS_PROBE_DEFAULT; 123 } else if (rev == PCI_DEVICE_REV_ADVANSYS_3050) { 124 device_set_desc(dev, 125 "AdvanSys ASC3030/50 SCSI controller"); 126 return BUS_PROBE_DEFAULT; 127 } else if (rev >= PCI_DEVICE_REV_ADVANSYS_3150) { 128 device_set_desc(dev, "Unknown AdvanSys controller"); 129 return BUS_PROBE_DEFAULT; 130 } 131 break; 132 default: 133 break; 134 } 135 return ENXIO; 136 } 137 138 static int 139 adv_pci_attach(device_t dev) 140 { 141 struct adv_softc *adv; 142 u_int32_t id; 143 int error, rid, irqrid; 144 void *ih; 145 struct resource *iores, *irqres; 146 147 /* 148 * Determine the chip version. 149 */ 150 id = pci_get_devid(dev); 151 pci_enable_busmaster(dev); 152 153 /* 154 * Early chips can't handle non-zero latency timer settings. 155 */ 156 if (id == PCI_DEVICE_ID_ADVANSYS_1200A 157 || id == PCI_DEVICE_ID_ADVANSYS_1200B) { 158 pci_write_config(dev, PCIR_LATTIMER, /*value*/0, /*bytes*/1); 159 } 160 161 rid = PCI_BASEADR0; 162 iores = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 163 RF_ACTIVE); 164 if (iores == NULL) 165 return ENXIO; 166 167 if (adv_find_signature(iores) == 0) { 168 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores); 169 return ENXIO; 170 } 171 172 adv = adv_alloc(dev, iores, 0); 173 if (adv == NULL) { 174 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores); 175 return ENXIO; 176 } 177 178 /* Allocate a dmatag for our transfer DMA maps */ 179 error = bus_dma_tag_create( 180 /* parent */ bus_get_dma_tag(dev), 181 /* alignment */ 1, 182 /* boundary */ 0, 183 /* lowaddr */ ADV_PCI_MAX_DMA_ADDR, 184 /* highaddr */ BUS_SPACE_MAXADDR, 185 /* filter */ NULL, 186 /* filterarg */ NULL, 187 /* maxsize */ BUS_SPACE_MAXSIZE_32BIT, 188 /* nsegments */ ~0, 189 /* maxsegsz */ ADV_PCI_MAX_DMA_COUNT, 190 /* flags */ 0, 191 /* lockfunc */ NULL, 192 /* lockarg */ NULL, 193 &adv->parent_dmat); 194 195 if (error != 0) { 196 device_printf(dev, "Could not allocate DMA tag - error %d\n", 197 error); 198 adv_free(adv); 199 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores); 200 return ENXIO; 201 } 202 203 adv->init_level++; 204 205 if (overrun_buf == NULL) { 206 /* Need to allocate our overrun buffer */ 207 if (bus_dma_tag_create( 208 /* parent */ adv->parent_dmat, 209 /* alignment */ 8, 210 /* boundary */ 0, 211 /* lowaddr */ ADV_PCI_MAX_DMA_ADDR, 212 /* highaddr */ BUS_SPACE_MAXADDR, 213 /* filter */ NULL, 214 /* filterarg */ NULL, 215 /* maxsize */ ADV_OVERRUN_BSIZE, 216 /* nsegments */ 1, 217 /* maxsegsz */ BUS_SPACE_MAXSIZE_32BIT, 218 /* flags */ 0, 219 /* lockfunc */ NULL, 220 /* lockarg */ NULL, 221 &overrun_dmat) != 0) { 222 bus_dma_tag_destroy(adv->parent_dmat); 223 adv_free(adv); 224 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores); 225 return ENXIO; 226 } 227 if (bus_dmamem_alloc(overrun_dmat, 228 &overrun_buf, 229 BUS_DMA_NOWAIT, 230 &overrun_dmamap) != 0) { 231 bus_dma_tag_destroy(overrun_dmat); 232 bus_dma_tag_destroy(adv->parent_dmat); 233 adv_free(adv); 234 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores); 235 return ENXIO; 236 } 237 /* And permanently map it in */ 238 bus_dmamap_load(overrun_dmat, overrun_dmamap, 239 overrun_buf, ADV_OVERRUN_BSIZE, 240 adv_map, &overrun_physbase, 241 /*flags*/0); 242 } 243 244 adv->overrun_physbase = overrun_physbase; 245 246 /* 247 * Stop the chip. 248 */ 249 ADV_OUTB(adv, ADV_CHIP_CTRL, ADV_CC_HALT); 250 ADV_OUTW(adv, ADV_CHIP_STATUS, 0); 251 252 adv->chip_version = ADV_INB(adv, ADV_NONEISA_CHIP_REVISION); 253 adv->type = ADV_PCI; 254 255 /* 256 * Setup active negation and signal filtering. 257 */ 258 { 259 u_int8_t extra_cfg; 260 261 if (adv->chip_version >= ADV_CHIP_VER_PCI_ULTRA_3150) 262 adv->type |= ADV_ULTRA; 263 if (adv->chip_version == ADV_CHIP_VER_PCI_ULTRA_3050) 264 extra_cfg = ADV_IFC_ACT_NEG | ADV_IFC_WR_EN_FILTER; 265 else 266 extra_cfg = ADV_IFC_ACT_NEG | ADV_IFC_SLEW_RATE; 267 ADV_OUTB(adv, ADV_REG_IFC, extra_cfg); 268 } 269 270 if (adv_init(adv) != 0) { 271 adv_free(adv); 272 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores); 273 return ENXIO; 274 } 275 276 adv->max_dma_count = ADV_PCI_MAX_DMA_COUNT; 277 adv->max_dma_addr = ADV_PCI_MAX_DMA_ADDR; 278 279 #if defined(CC_DISABLE_PCI_PARITY_INT) && CC_DISABLE_PCI_PARITY_INT 280 { 281 u_int16_t config_msw; 282 283 config_msw = ADV_INW(adv, ADV_CONFIG_MSW); 284 config_msw &= 0xFFC0; 285 ADV_OUTW(adv, ADV_CONFIG_MSW, config_msw); 286 } 287 #endif 288 289 if (id == PCI_DEVICE_ID_ADVANSYS_1200A 290 || id == PCI_DEVICE_ID_ADVANSYS_1200B) { 291 adv->bug_fix_control |= ADV_BUG_FIX_IF_NOT_DWB; 292 adv->bug_fix_control |= ADV_BUG_FIX_ASYN_USE_SYN; 293 adv->fix_asyn_xfer = ~0; 294 } 295 296 irqrid = 0; 297 irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irqrid, 298 RF_SHAREABLE | RF_ACTIVE); 299 if (irqres == NULL || 300 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, 301 NULL, adv_intr, adv, &ih) != 0) { 302 if (irqres != NULL) 303 bus_release_resource(dev, SYS_RES_IRQ, irqrid, irqres); 304 adv_free(adv); 305 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores); 306 return ENXIO; 307 } 308 309 if (adv_attach(adv) != 0) { 310 bus_teardown_intr(dev, irqres, ih); 311 bus_release_resource(dev, SYS_RES_IRQ, irqrid, irqres); 312 adv_free(adv); 313 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores); 314 return ENXIO; 315 } 316 return 0; 317 } 318 319 static device_method_t adv_pci_methods[] = { 320 /* Device interface */ 321 DEVMETHOD(device_probe, adv_pci_probe), 322 DEVMETHOD(device_attach, adv_pci_attach), 323 { 0, 0 } 324 }; 325 326 static driver_t adv_pci_driver = { 327 "adv", adv_pci_methods, sizeof(struct adv_softc) 328 }; 329 330 static devclass_t adv_pci_devclass; 331 DRIVER_MODULE(adv, pci, adv_pci_driver, adv_pci_devclass, 0, 0); 332 MODULE_DEPEND(adv, pci, 1, 1, 1);
Cache object: b046bbeaaa82b8509451f05d47e8e5e6
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