1 /*
2 * Device probe and attach routines for the following
3 * Advanced Systems Inc. SCSI controllers:
4 *
5 * Connectivity Products:
6 * ABP902/3902 - Bus-Master PCI (16 CDB)
7 * ABP3905 - Bus-Master PCI (16 CDB)
8 * ABP915 - Bus-Master PCI (16 CDB)
9 * ABP920 - Bus-Master PCI (16 CDB)
10 * ABP3922 - Bus-Master PCI (16 CDB)
11 * ABP3925 - Bus-Master PCI (16 CDB)
12 * ABP930 - Bus-Master PCI (16 CDB) *
13 * ABP930U - Bus-Master PCI Ultra (16 CDB)
14 * ABP930UA - Bus-Master PCI Ultra (16 CDB)
15 * ABP960 - Bus-Master PCI MAC/PC (16 CDB) **
16 * ABP960U - Bus-Master PCI MAC/PC (16 CDB) **
17 *
18 * Single Channel Products:
19 * ABP940 - Bus-Master PCI (240 CDB)
20 * ABP940U - Bus-Master PCI Ultra (240 CDB)
21 * ABP940UA/3940UA - Bus-Master PCI Ultra (240 CDB)
22 * ABP3960UA - Bus-Master PCI MAC/PC (240 CDB)
23 * ABP970 - Bus-Master PCI MAC/PC (240 CDB)
24 * ABP970U - Bus-Master PCI MAC/PC Ultra (240 CDB)
25 *
26 * Dual Channel Products:
27 * ABP950 - Dual Channel Bus-Master PCI (240 CDB Per Channel)
28 * ABP980 - Four Channel Bus-Master PCI (240 CDB Per Channel)
29 * ABP980U - Four Channel Bus-Master PCI Ultra (240 CDB Per Channel)
30 * ABP980UA/3980UA - Four Channel Bus-Master PCI Ultra (16 CDB Per Chan.)
31 *
32 * Footnotes:
33 * * This board has been sold by SIIG as the Fast SCSI Pro PCI.
34 * ** This board has been sold by Iomega as a Jaz Jet PCI adapter.
35 *
36 * Copyright (c) 1997 Justin Gibbs.
37 * All rights reserved.
38 *
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
41 * are met:
42 * 1. Redistributions of source code must retain the above copyright
43 * notice, this list of conditions, and the following disclaimer,
44 * without modification.
45 * 2. The name of the author may not be used to endorse or promote products
46 * derived from this software without specific prior written permission.
47 *
48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
51 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
52 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
58 * SUCH DAMAGE.
59 *
60 * $FreeBSD: releng/5.0/sys/dev/advansys/adv_pci.c 104707 2002-10-09 08:50:26Z peter $
61 */
62
63 #include <sys/param.h>
64 #include <sys/systm.h>
65 #include <sys/kernel.h>
66
67 #include <machine/bus_pio.h>
68 #include <machine/bus.h>
69 #include <machine/resource.h>
70 #include <sys/bus.h>
71 #include <sys/rman.h>
72
73 #include <pci/pcireg.h>
74 #include <pci/pcivar.h>
75
76 #include <dev/advansys/advansys.h>
77
78 #define PCI_BASEADR0 PCIR_MAPS /* I/O Address */
79 #define PCI_BASEADR1 PCIR_MAPS + 4 /* Mem I/O Address */
80
81 #define PCI_DEVICE_ID_ADVANSYS_1200A 0x110010CD
82 #define PCI_DEVICE_ID_ADVANSYS_1200B 0x120010CD
83 #define PCI_DEVICE_ID_ADVANSYS_3000 0x130010CD
84 #define PCI_DEVICE_REV_ADVANSYS_3150 0x02
85 #define PCI_DEVICE_REV_ADVANSYS_3050 0x03
86
87 #define ADV_PCI_MAX_DMA_ADDR (0xFFFFFFFFL)
88 #define ADV_PCI_MAX_DMA_COUNT (0xFFFFFFFFL)
89
90 static int adv_pci_probe(device_t);
91 static int adv_pci_attach(device_t);
92
93 /*
94 * The overrun buffer shared amongst all PCI adapters.
95 */
96 static u_int8_t* overrun_buf;
97 static bus_dma_tag_t overrun_dmat;
98 static bus_dmamap_t overrun_dmamap;
99 static bus_addr_t overrun_physbase;
100
101 static int
102 adv_pci_probe(device_t dev)
103 {
104 int rev = pci_get_revid(dev);
105
106 switch (pci_get_devid(dev)) {
107 case PCI_DEVICE_ID_ADVANSYS_1200A:
108 device_set_desc(dev, "AdvanSys ASC1200A SCSI controller");
109 return 0;
110 case PCI_DEVICE_ID_ADVANSYS_1200B:
111 device_set_desc(dev, "AdvanSys ASC1200B SCSI controller");
112 return 0;
113 case PCI_DEVICE_ID_ADVANSYS_3000:
114 if (rev == PCI_DEVICE_REV_ADVANSYS_3150) {
115 device_set_desc(dev,
116 "AdvanSys ASC3150 SCSI controller");
117 return 0;
118 } else if (rev == PCI_DEVICE_REV_ADVANSYS_3050) {
119 device_set_desc(dev,
120 "AdvanSys ASC3030/50 SCSI controller");
121 return 0;
122 } else if (rev >= PCI_DEVICE_REV_ADVANSYS_3150) {
123 device_set_desc(dev, "Unknown AdvanSys controller");
124 return 0;
125 }
126 break;
127 default:
128 break;
129 }
130 return ENXIO;
131 }
132
133 static int
134 adv_pci_attach(device_t dev)
135 {
136 struct adv_softc *adv;
137 u_int32_t id;
138 u_int32_t command;
139 int error, rid, irqrid;
140 void *ih;
141 struct resource *iores, *irqres;
142
143 /*
144 * Determine the chip version.
145 */
146 id = pci_read_config(dev, PCIR_DEVVENDOR, /*bytes*/4);
147 command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1);
148
149 /*
150 * These cards do not allow memory mapped accesses, so we must
151 * ensure that I/O accesses are available or we won't be able
152 * to talk to them.
153 */
154 if ((command & (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN))
155 != (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN)) {
156 command |= PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN;
157 pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1);
158 }
159
160 /*
161 * Early chips can't handle non-zero latency timer settings.
162 */
163 if (id == PCI_DEVICE_ID_ADVANSYS_1200A
164 || id == PCI_DEVICE_ID_ADVANSYS_1200B) {
165 pci_write_config(dev, PCIR_LATTIMER, /*value*/0, /*bytes*/1);
166 }
167
168 rid = PCI_BASEADR0;
169 iores = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0, ~0, 1,
170 RF_ACTIVE);
171 if (iores == NULL)
172 return ENXIO;
173
174 if (adv_find_signature(rman_get_bustag(iores),
175 rman_get_bushandle(iores)) == 0) {
176 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
177 return ENXIO;
178 }
179
180 adv = adv_alloc(dev, rman_get_bustag(iores), rman_get_bushandle(iores));
181 if (adv == NULL) {
182 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
183 return ENXIO;
184 }
185
186 /* Allocate a dmatag for our transfer DMA maps */
187 /* XXX Should be a child of the PCI bus dma tag */
188 error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/1,
189 /*boundary*/0,
190 /*lowaddr*/ADV_PCI_MAX_DMA_ADDR,
191 /*highaddr*/BUS_SPACE_MAXADDR,
192 /*filter*/NULL, /*filterarg*/NULL,
193 /*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
194 /*nsegments*/~0,
195 /*maxsegsz*/ADV_PCI_MAX_DMA_COUNT,
196 /*flags*/0,
197 &adv->parent_dmat);
198
199 if (error != 0) {
200 printf("%s: Could not allocate DMA tag - error %d\n",
201 adv_name(adv), error);
202 adv_free(adv);
203 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
204 return ENXIO;
205 }
206
207 adv->init_level++;
208
209 if (overrun_buf == NULL) {
210 /* Need to allocate our overrun buffer */
211 if (bus_dma_tag_create(adv->parent_dmat,
212 /*alignment*/8, /*boundary*/0,
213 ADV_PCI_MAX_DMA_ADDR, BUS_SPACE_MAXADDR,
214 /*filter*/NULL, /*filterarg*/NULL,
215 ADV_OVERRUN_BSIZE, /*nsegments*/1,
216 BUS_SPACE_MAXSIZE_32BIT, /*flags*/0,
217 &overrun_dmat) != 0) {
218 bus_dma_tag_destroy(adv->parent_dmat);
219 adv_free(adv);
220 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
221 return ENXIO;
222 }
223 if (bus_dmamem_alloc(overrun_dmat,
224 (void **)&overrun_buf,
225 BUS_DMA_NOWAIT,
226 &overrun_dmamap) != 0) {
227 bus_dma_tag_destroy(overrun_dmat);
228 bus_dma_tag_destroy(adv->parent_dmat);
229 adv_free(adv);
230 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
231 return ENXIO;
232 }
233 /* And permanently map it in */
234 bus_dmamap_load(overrun_dmat, overrun_dmamap,
235 overrun_buf, ADV_OVERRUN_BSIZE,
236 adv_map, &overrun_physbase,
237 /*flags*/0);
238 }
239
240 adv->overrun_physbase = overrun_physbase;
241
242 /*
243 * Stop the chip.
244 */
245 ADV_OUTB(adv, ADV_CHIP_CTRL, ADV_CC_HALT);
246 ADV_OUTW(adv, ADV_CHIP_STATUS, 0);
247
248 adv->chip_version = ADV_INB(adv, ADV_NONEISA_CHIP_REVISION);
249 adv->type = ADV_PCI;
250
251 /*
252 * Setup active negation and signal filtering.
253 */
254 {
255 u_int8_t extra_cfg;
256
257 if (adv->chip_version >= ADV_CHIP_VER_PCI_ULTRA_3150)
258 adv->type |= ADV_ULTRA;
259 if (adv->chip_version == ADV_CHIP_VER_PCI_ULTRA_3050)
260 extra_cfg = ADV_IFC_ACT_NEG | ADV_IFC_WR_EN_FILTER;
261 else
262 extra_cfg = ADV_IFC_ACT_NEG | ADV_IFC_SLEW_RATE;
263 ADV_OUTB(adv, ADV_REG_IFC, extra_cfg);
264 }
265
266 if (adv_init(adv) != 0) {
267 adv_free(adv);
268 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
269 return ENXIO;
270 }
271
272 adv->max_dma_count = ADV_PCI_MAX_DMA_COUNT;
273 adv->max_dma_addr = ADV_PCI_MAX_DMA_ADDR;
274
275 #if CC_DISABLE_PCI_PARITY_INT
276 {
277 u_int16_t config_msw;
278
279 config_msw = ADV_INW(adv, ADV_CONFIG_MSW);
280 config_msw &= 0xFFC0;
281 ADV_OUTW(adv, ADV_CONFIG_MSW, config_msw);
282 }
283 #endif
284
285 if (id == PCI_DEVICE_ID_ADVANSYS_1200A
286 || id == PCI_DEVICE_ID_ADVANSYS_1200B) {
287 adv->bug_fix_control |= ADV_BUG_FIX_IF_NOT_DWB;
288 adv->bug_fix_control |= ADV_BUG_FIX_ASYN_USE_SYN;
289 adv->fix_asyn_xfer = ~0;
290 }
291
292 irqrid = 0;
293 irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &irqrid, 0, ~0, 1,
294 RF_SHAREABLE | RF_ACTIVE);
295 if (irqres == NULL ||
296 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY, adv_intr, adv, &ih)) {
297 adv_free(adv);
298 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
299 return ENXIO;
300 }
301
302 adv_attach(adv);
303 return 0;
304 }
305
306 static device_method_t adv_pci_methods[] = {
307 /* Device interface */
308 DEVMETHOD(device_probe, adv_pci_probe),
309 DEVMETHOD(device_attach, adv_pci_attach),
310 { 0, 0 }
311 };
312
313 static driver_t adv_pci_driver = {
314 "adv", adv_pci_methods, sizeof(struct adv_softc)
315 };
316
317 static devclass_t adv_pci_devclass;
318 DRIVER_MODULE(adv, pci, adv_pci_driver, adv_pci_devclass, 0, 0);
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