The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/advansys/adv_pci.c

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    1 /*-
    2  * Device probe and attach routines for the following
    3  * Advanced Systems Inc. SCSI controllers:
    4  *
    5  *   Connectivity Products:
    6  *      ABP902/3902     - Bus-Master PCI (16 CDB)
    7  *      ABP3905         - Bus-Master PCI (16 CDB)
    8  *      ABP915          - Bus-Master PCI (16 CDB)
    9  *      ABP920          - Bus-Master PCI (16 CDB)
   10  *      ABP3922         - Bus-Master PCI (16 CDB)
   11  *      ABP3925         - Bus-Master PCI (16 CDB)
   12  *      ABP930          - Bus-Master PCI (16 CDB) *
   13  *      ABP930U         - Bus-Master PCI Ultra (16 CDB)
   14  *      ABP930UA        - Bus-Master PCI Ultra (16 CDB)
   15  *      ABP960          - Bus-Master PCI MAC/PC (16 CDB) **
   16  *      ABP960U         - Bus-Master PCI MAC/PC (16 CDB) **
   17  *
   18  *   Single Channel Products:
   19  *      ABP940          - Bus-Master PCI (240 CDB)
   20  *      ABP940U         - Bus-Master PCI Ultra (240 CDB)
   21  *      ABP940UA/3940UA - Bus-Master PCI Ultra (240 CDB)
   22  *      ABP3960UA       - Bus-Master PCI MAC/PC (240 CDB)
   23  *      ABP970          - Bus-Master PCI MAC/PC (240 CDB)
   24  *      ABP970U         - Bus-Master PCI MAC/PC Ultra (240 CDB)
   25  *
   26  *   Dual Channel Products:  
   27  *      ABP950 - Dual Channel Bus-Master PCI (240 CDB Per Channel)
   28  *      ABP980 - Four Channel Bus-Master PCI (240 CDB Per Channel)
   29  *      ABP980U - Four Channel Bus-Master PCI Ultra (240 CDB Per Channel)
   30  *      ABP980UA/3980UA - Four Channel Bus-Master PCI Ultra (16 CDB Per Chan.)
   31  *
   32  *   Footnotes:
   33  *       * This board has been sold by SIIG as the Fast SCSI Pro PCI.
   34  *      ** This board has been sold by Iomega as a Jaz Jet PCI adapter. 
   35  *
   36  * Copyright (c) 1997 Justin Gibbs.
   37  * All rights reserved.
   38  *
   39  * Redistribution and use in source and binary forms, with or without
   40  * modification, are permitted provided that the following conditions
   41  * are met:
   42  * 1. Redistributions of source code must retain the above copyright
   43  *    notice, this list of conditions, and the following disclaimer,
   44  *    without modification.
   45  * 2. The name of the author may not be used to endorse or promote products
   46  *    derived from this software without specific prior written permission.
   47  *
   48  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   49  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   50  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   51  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
   52  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   53  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   54  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   55  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   56  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   57  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   58  * SUCH DAMAGE.
   59  */
   60 
   61 #include <sys/cdefs.h>
   62 __FBSDID("$FreeBSD: releng/8.4/sys/dev/advansys/adv_pci.c 233025 2012-03-16 09:22:59Z scottl $");
   63 
   64 #include <sys/param.h>
   65 #include <sys/systm.h>
   66 #include <sys/kernel.h>
   67 #include <sys/lock.h>
   68 #include <sys/module.h>
   69 #include <sys/mutex.h>
   70 
   71 #include <machine/bus.h>
   72 #include <machine/resource.h>
   73 #include <sys/bus.h>
   74 #include <sys/rman.h>
   75 
   76 #include <dev/pci/pcireg.h>
   77 #include <dev/pci/pcivar.h>
   78 
   79 #include <dev/advansys/advansys.h>
   80 
   81 #define PCI_BASEADR0    PCIR_BAR(0)             /* I/O Address */
   82 #define PCI_BASEADR1    PCIR_BAR(1)             /* Mem I/O Address */
   83 
   84 #define PCI_DEVICE_ID_ADVANSYS_1200A    0x110010CD
   85 #define PCI_DEVICE_ID_ADVANSYS_1200B    0x120010CD
   86 #define PCI_DEVICE_ID_ADVANSYS_3000     0x130010CD
   87 #define PCI_DEVICE_REV_ADVANSYS_3150    0x02
   88 #define PCI_DEVICE_REV_ADVANSYS_3050    0x03
   89 
   90 #define ADV_PCI_MAX_DMA_ADDR    (0xFFFFFFFFL)
   91 #define ADV_PCI_MAX_DMA_COUNT   (0xFFFFFFFFL)
   92 
   93 static int adv_pci_probe(device_t);
   94 static int adv_pci_attach(device_t);
   95 
   96 /* 
   97  * The overrun buffer shared amongst all PCI adapters.
   98  */
   99 static  void*           overrun_buf;
  100 static  bus_dma_tag_t   overrun_dmat;
  101 static  bus_dmamap_t    overrun_dmamap;
  102 static  bus_addr_t      overrun_physbase;
  103 
  104 static int
  105 adv_pci_probe(device_t dev)
  106 {
  107         int     rev = pci_get_revid(dev);
  108 
  109         switch (pci_get_devid(dev)) {
  110         case PCI_DEVICE_ID_ADVANSYS_1200A:
  111                 device_set_desc(dev, "AdvanSys ASC1200A SCSI controller");
  112                 return BUS_PROBE_DEFAULT;
  113         case PCI_DEVICE_ID_ADVANSYS_1200B:
  114                 device_set_desc(dev, "AdvanSys ASC1200B SCSI controller");
  115                 return BUS_PROBE_DEFAULT;
  116         case PCI_DEVICE_ID_ADVANSYS_3000:
  117                 if (rev == PCI_DEVICE_REV_ADVANSYS_3150) {
  118                         device_set_desc(dev,
  119                                         "AdvanSys ASC3150 SCSI controller");
  120                         return BUS_PROBE_DEFAULT;
  121                 } else if (rev == PCI_DEVICE_REV_ADVANSYS_3050) {
  122                         device_set_desc(dev,
  123                                         "AdvanSys ASC3030/50 SCSI controller");
  124                         return BUS_PROBE_DEFAULT;
  125                 } else if (rev >= PCI_DEVICE_REV_ADVANSYS_3150) {
  126                         device_set_desc(dev, "Unknown AdvanSys controller");
  127                         return BUS_PROBE_DEFAULT;
  128                 }
  129                 break;
  130         default:
  131                 break;
  132         }
  133         return ENXIO;
  134 }
  135 
  136 static int
  137 adv_pci_attach(device_t dev)
  138 {
  139         struct          adv_softc *adv;
  140         u_int32_t       id;
  141         u_int32_t       command;
  142         int             error, rid, irqrid;
  143         void            *ih;
  144         struct resource *iores, *irqres;
  145 
  146         /*
  147          * Determine the chip version.
  148          */
  149         id = pci_read_config(dev, PCIR_DEVVENDOR, /*bytes*/4);
  150         command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1);
  151 
  152         /*
  153          * These cards do not allow memory mapped accesses, so we must
  154          * ensure that I/O accesses are available or we won't be able
  155          * to talk to them.
  156          */
  157         if ((command & (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN))
  158          != (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN)) {
  159                 command |= PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN;
  160                 pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1);
  161         }
  162 
  163         /*
  164          * Early chips can't handle non-zero latency timer settings.
  165          */
  166         if (id == PCI_DEVICE_ID_ADVANSYS_1200A
  167          || id == PCI_DEVICE_ID_ADVANSYS_1200B) {
  168                 pci_write_config(dev, PCIR_LATTIMER, /*value*/0, /*bytes*/1);
  169         }
  170 
  171         rid = PCI_BASEADR0;
  172         iores = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
  173                                        RF_ACTIVE);
  174         if (iores == NULL)
  175                 return ENXIO;
  176 
  177         if (adv_find_signature(rman_get_bustag(iores),
  178                                rman_get_bushandle(iores)) == 0) {
  179                 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
  180                 return ENXIO;
  181         }
  182 
  183         adv = adv_alloc(dev, rman_get_bustag(iores), rman_get_bushandle(iores));
  184         if (adv == NULL) {
  185                 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
  186                 return ENXIO;
  187         }
  188 
  189         /* Allocate a dmatag for our transfer DMA maps */
  190         error = bus_dma_tag_create(
  191                         /* parent       */ bus_get_dma_tag(dev),
  192                         /* alignment    */ 1,
  193                         /* boundary     */ 0,
  194                         /* lowaddr      */ ADV_PCI_MAX_DMA_ADDR,
  195                         /* highaddr     */ BUS_SPACE_MAXADDR,
  196                         /* filter       */ NULL,
  197                         /* filterarg    */ NULL,
  198                         /* maxsize      */ BUS_SPACE_MAXSIZE_32BIT,
  199                         /* nsegments    */ ~0,
  200                         /* maxsegsz     */ ADV_PCI_MAX_DMA_COUNT,
  201                         /* flags        */ 0,
  202                         /* lockfunc     */ busdma_lock_mutex,
  203                         /* lockarg      */ &Giant,
  204                         &adv->parent_dmat);
  205  
  206         if (error != 0) {
  207                 printf("%s: Could not allocate DMA tag - error %d\n",
  208                        adv_name(adv), error);
  209                 adv_free(adv);
  210                 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
  211                 return ENXIO;
  212         }
  213 
  214         adv->init_level++;
  215 
  216         if (overrun_buf == NULL) {
  217                 /* Need to allocate our overrun buffer */
  218                 if (bus_dma_tag_create(
  219                                 /* parent       */ adv->parent_dmat,
  220                                 /* alignment    */ 8,
  221                                 /* boundary     */ 0,
  222                                 /* lowaddr      */ ADV_PCI_MAX_DMA_ADDR,
  223                                 /* highaddr     */ BUS_SPACE_MAXADDR,
  224                                 /* filter       */ NULL,
  225                                 /* filterarg    */ NULL,
  226                                 /* maxsize      */ ADV_OVERRUN_BSIZE,
  227                                 /* nsegments    */ 1,
  228                                 /* maxsegsz     */ BUS_SPACE_MAXSIZE_32BIT,
  229                                 /* flags        */ 0,
  230                                 /* lockfunc     */ busdma_lock_mutex,
  231                                 /* lockarg      */ &Giant,
  232                                 &overrun_dmat) != 0) {
  233                         bus_dma_tag_destroy(adv->parent_dmat);
  234                         adv_free(adv);
  235                         bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
  236                         return ENXIO;
  237                 }
  238                 if (bus_dmamem_alloc(overrun_dmat,
  239                                      &overrun_buf,
  240                                      BUS_DMA_NOWAIT,
  241                                      &overrun_dmamap) != 0) {
  242                         bus_dma_tag_destroy(overrun_dmat);
  243                         bus_dma_tag_destroy(adv->parent_dmat);
  244                         adv_free(adv);
  245                         bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
  246                         return ENXIO;
  247                 }
  248                 /* And permanently map it in */  
  249                 bus_dmamap_load(overrun_dmat, overrun_dmamap,
  250                                 overrun_buf, ADV_OVERRUN_BSIZE,
  251                                 adv_map, &overrun_physbase,
  252                                 /*flags*/0);
  253         }
  254 
  255         adv->overrun_physbase = overrun_physbase;
  256                         
  257         /*
  258          * Stop the chip.
  259          */
  260         ADV_OUTB(adv, ADV_CHIP_CTRL, ADV_CC_HALT);
  261         ADV_OUTW(adv, ADV_CHIP_STATUS, 0);
  262 
  263         adv->chip_version = ADV_INB(adv, ADV_NONEISA_CHIP_REVISION);
  264         adv->type = ADV_PCI;
  265         
  266         /*
  267          * Setup active negation and signal filtering.
  268          */
  269         {
  270                 u_int8_t extra_cfg;
  271 
  272                 if (adv->chip_version >= ADV_CHIP_VER_PCI_ULTRA_3150)
  273                         adv->type |= ADV_ULTRA;
  274                 if (adv->chip_version == ADV_CHIP_VER_PCI_ULTRA_3050)
  275                         extra_cfg = ADV_IFC_ACT_NEG | ADV_IFC_WR_EN_FILTER;
  276                 else
  277                         extra_cfg = ADV_IFC_ACT_NEG | ADV_IFC_SLEW_RATE;
  278                 ADV_OUTB(adv, ADV_REG_IFC, extra_cfg);
  279         }
  280 
  281         if (adv_init(adv) != 0) {
  282                 adv_free(adv);
  283                 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
  284                 return ENXIO;
  285         }
  286 
  287         adv->max_dma_count = ADV_PCI_MAX_DMA_COUNT;
  288         adv->max_dma_addr = ADV_PCI_MAX_DMA_ADDR;
  289 
  290 #if defined(CC_DISABLE_PCI_PARITY_INT) && CC_DISABLE_PCI_PARITY_INT
  291         {
  292                 u_int16_t config_msw;
  293 
  294                 config_msw = ADV_INW(adv, ADV_CONFIG_MSW);
  295                 config_msw &= 0xFFC0;
  296                 ADV_OUTW(adv, ADV_CONFIG_MSW, config_msw); 
  297         }
  298 #endif
  299  
  300         if (id == PCI_DEVICE_ID_ADVANSYS_1200A
  301          || id == PCI_DEVICE_ID_ADVANSYS_1200B) {
  302                 adv->bug_fix_control |= ADV_BUG_FIX_IF_NOT_DWB;
  303                 adv->bug_fix_control |= ADV_BUG_FIX_ASYN_USE_SYN;
  304                 adv->fix_asyn_xfer = ~0;
  305         }
  306 
  307         irqrid = 0;
  308         irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irqrid,
  309                                         RF_SHAREABLE | RF_ACTIVE);
  310         if (irqres == NULL ||
  311             bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY, NULL, 
  312                 adv_intr, adv, &ih)) {
  313                 adv_free(adv);
  314                 bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
  315                 return ENXIO;
  316         }
  317 
  318         adv_attach(adv);
  319         return 0;
  320 }
  321 
  322 static device_method_t adv_pci_methods[] = {
  323         /* Device interface */
  324         DEVMETHOD(device_probe,         adv_pci_probe),
  325         DEVMETHOD(device_attach,        adv_pci_attach),
  326         { 0, 0 }
  327 };
  328 
  329 static driver_t adv_pci_driver = {
  330         "adv", adv_pci_methods, sizeof(struct adv_softc)
  331 };
  332 
  333 static devclass_t adv_pci_devclass;
  334 DRIVER_MODULE(adv, pci, adv_pci_driver, adv_pci_devclass, 0, 0);
  335 MODULE_DEPEND(adv, pci, 1, 1, 1);

Cache object: b7fcbdb3dfcce20e88b87490597291e2


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