The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/advansys/advlib.h

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    1 /*-
    2  * Definitions for low level routines and data structures
    3  * for the Advanced Systems Inc. SCSI controllers chips.
    4  *
    5  * Copyright (c) 1996-1997, 1999-2000 Justin T. Gibbs.
    6  * All rights reserved.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions, and the following disclaimer,
   13  *    without modification, immediately at the beginning of the file.
   14  * 2. Redistributions in binary form must reproduce the above copyright
   15  *    notice, this list of conditions and the following disclaimer in the
   16  *    documentation and/or other materials provided with the distribution.
   17  * 3. The name of the author may not be used to endorse or promote products
   18  *    derived from this software without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
   24  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   30  * SUCH DAMAGE.
   31  *
   32  * $FreeBSD: releng/10.3/sys/dev/advansys/advlib.h 241492 2012-10-12 21:31:44Z jhb $
   33  */
   34 /*-
   35  * Ported from:
   36  * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
   37  *     
   38  * Copyright (c) 1995-1996 Advanced System Products, Inc.
   39  * All Rights Reserved.
   40  *   
   41  * Redistribution and use in source and binary forms, with or without
   42  * modification, are permitted provided that redistributions of source
   43  * code retain the above copyright notice and this comment without
   44  * modification.
   45  */
   46 
   47 #ifndef _ADVLIB_H_
   48 #define _ADVLIB_H_
   49 
   50 #include <sys/queue.h>
   51 
   52 struct cam_path;
   53 union ccb;
   54 
   55 typedef u_int8_t target_bit_vector;
   56 #define TARGET_BIT_VECTOR_SET -1
   57 #define ADV_SCSI_ID_BITS        3
   58 #define ADV_MAX_TID             7
   59 #define ADV_MAX_LUN             7
   60 
   61 #define ADV_MAXPHYS             (128 * 1024)
   62 
   63 /* Enumeration of board types */
   64 typedef enum {
   65         ADV_NONE        = 0x000,
   66         ADV_ISA         = 0x001,
   67         ADV_ISAPNP      = 0x003,
   68         ADV_VL          = 0x004,
   69         ADV_EISA        = 0x008,
   70         ADV_PCI         = 0x010,
   71         ADV_MCA         = 0x020,
   72         ADV_PCMCIA      = 0x040,
   73         ADV_ULTRA       = 0x100,
   74         ADV_WIDE        = 0x200,
   75         ADV_WIDE32      = 0x400
   76 } adv_btype;
   77 
   78 typedef enum {
   79         ADV_STATE_NONE                  = 0x00,
   80         ADV_RESOURCE_SHORTAGE           = 0x01,
   81         ADV_IN_TIMEOUT                  = 0x02,
   82         ADV_BUSDMA_BLOCK                = 0x04,
   83         ADV_BUSDMA_BLOCK_CLEARED        = 0x08
   84         
   85 } adv_state;
   86 
   87 typedef enum {
   88         ACCB_FREE               = 0x00,
   89         ACCB_ACTIVE             = 0x01,
   90         ACCB_ABORT_QUEUED       = 0x02,
   91         ACCB_RECOVERY_CCB       = 0x04
   92 } adv_ccb_state;
   93 
   94 struct adv_ccb_info {
   95         adv_ccb_state   state;
   96         bus_dmamap_t    dmamap;
   97         struct callout  timer;
   98         union ccb*      ccb;
   99         SLIST_ENTRY(adv_ccb_info) links;
  100 };
  101 
  102 #define ccb_cinfo_ptr spriv_ptr0
  103 
  104 #define ADV_SYN_XFER_NO                 8
  105 #define ADV_SYN_MAX_OFFSET              0x0F
  106 #define ADV_DEF_SDTR_OFFSET             0x0F
  107 #define ADV_DEF_SDTR_INDEX              0x00
  108 #define ADV_OVERRUN_BSIZE               0x00000040
  109 #define ADV_MAX_CDB_LEN                 12
  110 #define ADV_MAX_SENSE_LEN               32
  111 #define ADV_MIN_SENSE_LEN               14
  112 
  113 #define ADV_TIDLUN_TO_IX(tid, lun) ((tid) | ((lun) << ADV_SCSI_ID_BITS) )
  114 #define ADV_TID_TO_TARGET_MASK(tid)  (0x01 << (tid))
  115 #define ADV_TIX_TO_TARGET_MASK(tix)  (0x01 << ((tix) & ADV_MAX_TID))
  116 #define ADV_TIX_TO_TID(tix)  ((tix) & ADV_MAX_TID)
  117 #define ADV_TID_TO_TIX(tid)  ((tid) & ADV_MAX_TID)
  118 #define ADV_TIX_TO_LUN(tix)  (((tix) >> ADV_SCSI_ID_BITS) & ADV_MAX_LUN )
  119 
  120 
  121 /*
  122  * XXX
  123  * PnP port addresses
  124  * I believe that these are standard PnP address and should be replaced
  125  * by the values in a central ISA PnP header file when we get one.
  126  */
  127 #define ADV_ISA_PNP_PORT_ADDR  (0x279)
  128 #define ADV_ISA_PNP_PORT_WRITE (ADV_ISA_PNP_PORT_ADDR+0x800)
  129 
  130 /*
  131  * Board Signatures
  132  */
  133 #define ADV_SIGNATURE_WORD                      0x0000
  134 #define          ADV_1000_ID0W                  0x04C1
  135 #define          ADV_1000_ID0W_FIX              0x00C1
  136 
  137 #define ADV_SIGNATURE_BYTE                      0x0001
  138 #define          ADV_1000_ID1B                  0x25    
  139 
  140 #define ADV_REG_IH                              0x0002
  141 #define         ADV_INS_HALTINT                 0x6281
  142 #define         ADV_INS_HALT                    0x6280
  143 #define         ADV_INS_SINT                    0x6200
  144 #define         ADV_INS_RFLAG_WTM               0x7380
  145 
  146 #define ADV_CONFIG_LSW                          0x0002
  147 #define         ADV_CFG_LSW_ISA_DMA_CHANNEL     0x0003
  148 #define         ADV_CFG_LSW_HOST_INT_ON         0x0020
  149 #define         ADV_CFG_LSW_BIOS_ON             0x0040
  150 #define         ADV_CFG_LSW_VERA_BURST_ON       0x0080
  151 #define         ADV_CFG_LSW_SCSI_PARITY_ON      0x0800
  152 #define         ADV_CFG_LSW_SCSIID              0x0700
  153 #define         ADV_CFG_LSW_SCSIID_SHIFT        8
  154 #define ADV_CONFIG_SCSIID(cfg) ((cfg >> ADV_CFG_LSW_SCSIID_SHIFT) & ADV_MAX_TID)
  155         
  156 /*
  157  * Chip Revision Number
  158  */
  159 #define ADV_NONEISA_CHIP_REVISION               0x0003
  160 #define         ADV_CHIP_MIN_VER_VL             0x01
  161 #define         ADV_CHIP_MAX_VER_VL             0x07
  162 #define         ADV_CHIP_MIN_VER_PCI            0x09
  163 #define         ADV_CHIP_MAX_VER_PCI            0x0F
  164 #define         ADV_CHIP_VER_PCI_BIT            0x08
  165 #define         ADV_CHIP_VER_PCI_ULTRA_3150  (ADV_CHIP_VER_PCI_BIT | 0x02)
  166 #define         ADV_CHIP_VER_PCI_ULTRA_3050  (ADV_CHIP_VER_PCI_BIT | 0x03)
  167 #define         ADV_CHIP_MIN_VER_ISA            0x11
  168 #define         ADV_CHIP_MIN_VER_ISA_PNP        0x21
  169 #define         ADV_CHIP_MAX_VER_ISA            0x27
  170 #define         ADV_CHIP_VER_ISA_BIT            0x30
  171 #define         ADV_CHIP_VER_ISAPNP_BIT         0x20
  172 #define         ADV_CHIP_VER_ASYN_BUG           0x21
  173 #define         ADV_CHIP_MIN_VER_EISA           0x41
  174 #define         ADV_CHIP_MAX_VER_EISA           0x47
  175 #define         ADV_CHIP_VER_EISA_BIT           0x40
  176 
  177 #define ADV_CONFIG_MSW                          0x0004
  178 #define         ADV_CFG_MSW_SCSI_TARGET_ON      0x0080
  179 #define         ADV_CFG_MSW_LRAM_8BITS_ON       0x0800
  180 #define         ADV_CFG_MSW_CLR_MASK            0x30C0
  181 
  182 #define ADV_EEPROM_DATA                         0x0006
  183 
  184 #define ADV_EEPROM_CMD                          0x0007
  185 #define         ADV_EEPROM_CMD_READ             0x80
  186 #define         ADV_EEPROM_CMD_WRITE            0x40
  187 #define         ADV_EEPROM_CMD_WRITE_ENABLE     0x30
  188 #define         ADV_EEPROM_CMD_WRITE_DISABLE    0x00
  189 
  190 #define ADV_DMA_SPEED                           0x0007
  191 #define         ADV_DEF_ISA_DMA_SPEED           4
  192 #define ADV_REG_FLAG                            0x0007
  193 
  194 #define ADV_LRAM_DATA                           0x0008
  195 
  196 #define ADV_LRAM_ADDR                           0x000A
  197 
  198 #define ADV_SYN_OFFSET                          0x000B
  199 
  200 #define ADV_REG_PROG_COUNTER                    0x000C
  201 #define         ADV_MCODE_START_ADDR            0x0080
  202 
  203 #define ADV_REG_IFC                             0x000D
  204 #define         ADV_IFC_REG_LOCK                0x00
  205 #define         ADV_IFC_REG_UNLOCK              0x09
  206 #define         ADV_IFC_WR_EN_FILTER            0x10
  207 #define         ADV_IFC_RD_NO_EEPROM            0x10
  208 #define         ADV_IFC_SLEW_RATE               0x20
  209 #define         ADV_IFC_ACT_NEG                 0x40
  210 #define         ADV_IFC_INP_FILTER              0x80
  211 #define         ADV_IFC_INIT_DEFAULT  (ADV_IFC_ACT_NEG | ADV_IFC_REG_UNLOCK)
  212         
  213 #define ADV_CHIP_STATUS                         0x000E
  214 #define         ADV_CSW_TEST1                   0x8000
  215 #define         ADV_CSW_AUTO_CONFIG             0x4000
  216 #define         ADV_CSW_RESERVED1               0x2000
  217 #define         ADV_CSW_IRQ_WRITTEN             0x1000
  218 #define         ADV_CSW_33MHZ_SELECTED          0x0800
  219 #define         ADV_CSW_TEST2                   0x0400
  220 #define         ADV_CSW_TEST3                   0x0200
  221 #define         ADV_CSW_RESERVED2               0x0100
  222 #define         ADV_CSW_DMA_DONE                0x0080
  223 #define         ADV_CSW_FIFO_RDY                0x0040
  224 #define         ADV_CSW_EEP_READ_DONE           0x0020
  225 #define         ADV_CSW_HALTED                  0x0010
  226 #define         ADV_CSW_SCSI_RESET_ACTIVE       0x0008
  227 #define         ADV_CSW_PARITY_ERR              0x0004
  228 #define         ADV_CSW_SCSI_RESET_LATCH        0x0002
  229 #define         ADV_CSW_INT_PENDING             0x0001
  230 /*
  231  * XXX I don't understand the relevence of the naming
  232  * convention change here.  What does CIW stand for?
  233  * Perhaps this is to differentiate read and write
  234  * values?
  235  */
  236 #define         ADV_CIW_INT_ACK                 0x0100
  237 #define         ADV_CIW_TEST1                   0x0200
  238 #define         ADV_CIW_TEST2                   0x0400
  239 #define         ADV_CIW_SEL_33MHZ               0x0800
  240 #define         ADV_CIW_IRQ_ACT                 0x1000
  241 #define         ADV_CIW_CLR_SCSI_RESET_INT      0x1000  
  242 
  243 #define ADV_CHIP_CTRL                           0x000F
  244 #define         ADV_CC_CHIP_RESET               0x80
  245 #define         ADV_CC_SCSI_RESET               0x40
  246 #define         ADV_CC_HALT                     0x20
  247 #define         ADV_CC_SINGLE_STEP              0x10
  248 #define         ADV_CC_DMA_ENABLE               0x08
  249 #define         ADV_CC_TEST                     0x04
  250 #define         ADV_CC_BANK_ONE                 0x02    
  251 #define         ADV_CC_DIAG                     0x01
  252         
  253 #define ADV_HALTCODE_W                          0x0040
  254 #define ADV_STOP_CODE_B                         0x0034
  255 #define         ADV_STOP_REQ_RISC_STOP          0x01
  256 #define         ADV_STOP_ACK_RISC_STOP          0x03
  257 #define         ADV_STOP_CLEAN_UP_BUSY_Q        0x10
  258 #define         ADV_STOP_CLEAN_UP_DISC_Q        0x20
  259 #define         ADV_STOP_HOST_REQ_RISC_HALT     0x40
  260 
  261 /*
  262  * EEPROM routine constants
  263  * XXX What about wide controllers?
  264  * Surely they have space for 8 more targets.
  265  */     
  266 #define ADV_EEPROM_CFG_BEG_VL           2
  267 #define ADV_EEPROM_MAX_ADDR_VL          15
  268 #define ADV_EEPROM_CFG_BEG              32
  269 #define ADV_EEPROM_MAX_ADDR             45
  270 #define ADV_EEPROM_MAX_RETRY            20
  271         
  272 struct adv_eeprom_config {
  273         u_int16_t       cfg_lsw;
  274         
  275         u_int16_t       cfg_msw;
  276 
  277         u_int8_t        init_sdtr;
  278         u_int8_t        disc_enable;
  279 
  280         u_int8_t        use_cmd_qng;
  281         u_int8_t        start_motor;
  282         
  283         u_int8_t        max_total_qng;
  284         u_int8_t        max_tag_qng;
  285         
  286         u_int8_t        bios_scan;
  287         u_int8_t        power_up_wait;
  288 
  289         u_int8_t        no_scam;
  290         u_int8_t        scsi_id_dma_speed;
  291 #define         EEPROM_SCSI_ID_MASK     0x0F
  292 #define         EEPROM_DMA_SPEED_MASK   0xF0
  293 #define         EEPROM_DMA_SPEED(ep)                            \
  294                 (((ep).scsi_id_dma_speed & EEPROM_DMA_SPEED_MASK) >> 4)
  295 #define         EEPROM_SET_DMA_SPEED(ep, speed)                 \
  296                 (ep).scsi_id_dma_speed &= ~EEPROM_DMA_SPEED_MASK;       \
  297                 (ep).scsi_id_dma_speed |=                               \
  298                     (((speed) << 4) & EEPROM_DMA_SPEED_MASK)
  299 #define         EEPROM_SCSIID(ep) ((ep).scsi_id_dma_speed & EEPROM_SCSI_ID_MASK)
  300 #define         EEPROM_SET_SCSIID(ep, id)                       \
  301                 (ep).scsi_id_dma_speed &= ~EEPROM_SCSI_ID_MASK; \
  302                 (ep).scsi_id_dma_speed |= ((id) & EEPROM_SCSI_ID_MASK)
  303         u_int8_t        sdtr_data[8];
  304         u_int8_t        adapter_info[6];
  305 
  306         u_int16_t       cntl;
  307 
  308         u_int16_t       chksum;
  309 };
  310 
  311 /* Bank 1 */
  312 #define ADV_SEQ_ACCUM                           0x0000
  313 #define ADV_QUEUE_ELEMENT_INDEX                 0x0001
  314 #define ADV_SEQ_INSTRUCTION_HOLD                0x0002
  315 #define ADV_QUEUE_ELEMENT_POINTER               0x0003
  316 #define ADV_HOST_DATA_FIFO_L                    0x0004
  317 #define ADV_HOST_SCSIID                         0x0005
  318 #define ADV_HOST_DATA_FIFO_H                    0x0006
  319 #define ADV_SCSI_CONTROL                        0x0009
  320 #define         SC_SEL                          0x80
  321 #define         SC_BSY                          0x40
  322 #define         SC_ACK                          0x20
  323 #define         SC_REQ                          0x10
  324 #define         SC_ATN                          0x08
  325 #define         SC_IO                           0x04
  326 #define         SC_CD                           0x02
  327 #define         SC_MSG                          0x01
  328 #define ADV_SCSIDATL                            0x000B
  329 #define ADV_DMA_TRANSFER_CNT                    0x000C
  330 #define ADV_DMA_TRANSFER_CNT1                   0x000E
  331 
  332 /*
  333  * Instruction data and code segment addresses,
  334  * and transaction address translation (queues).
  335  * All addresses refer to on board LRAM.
  336  */
  337 #define ADV_DATA_SEC_BEG                0x0080
  338 #define ADV_DATA_SEC_END                0x0080
  339 #define ADV_CODE_SEC_BEG                0x0080
  340 #define ADV_CODE_SEC_END                0x0080
  341 #define ADV_QADR_BEG                    0x4000
  342 #define ADV_QADR_END                    0x7FFF
  343 #define ADV_QLAST_ADR                   0x7FC0
  344 #define ADV_QBLK_SIZE                   0x40
  345 #define ADV_BIOS_DATA_QBEG              0xF8
  346 #define ADV_MAX_QNO                     0xF8
  347 #define ADV_QADR_USED (ADV_MAX_QNO * 64)
  348 #define ADV_QNO_TO_QADDR(q_no) ((ADV_QADR_BEG) + ((u_int16_t)(q_no) << 6))
  349 
  350 #define ADV_MIN_ACTIVE_QNO              0x01
  351 #define ADV_QLINK_END                   0xFF
  352 
  353 #define ADV_MAX_SG_QUEUE                5
  354 #define ADV_SG_LIST_PER_Q               7
  355 #define ADV_MAX_SG_LIST                 (1 + ((ADV_SG_LIST_PER_Q) * (ADV_MAX_SG_QUEUE)))
  356 
  357 #define ADV_MIN_REMAIN_Q                0x02
  358 #define ADV_DEF_MAX_TOTAL_QNG           0xF0
  359 #define ADV_MIN_TAG_Q_PER_DVC           0x04
  360 #define ADV_DEF_TAG_Q_PER_DVC           0x04
  361 #define ADV_MIN_FREE_Q                  ADV_MIN_REMAIN_Q
  362 #define ADV_MIN_TOTAL_QNG               ((ADV_MAX_SG_QUEUE)+(ADV_MIN_FREE_Q))
  363 #define ADV_MAX_TOTAL_QNG               240
  364 #define ADV_MAX_INRAM_TAG_QNG           16
  365 #define ADV_MAX_PCI_INRAM_TOTAL_QNG     20
  366 #define ADV_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
  367 #define ADV_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
  368 
  369 #define ADV_DEF_IRQ_NO                  10
  370 #define ADV_MAX_IRQ_NO                  15
  371 #define ADV_MIN_IRQ_NO                  10
  372 
  373 #define ADV_SCSIQ_CPY_BEG               4
  374 #define ADV_SCSIQ_SGHD_CPY_BEG          2
  375 
  376 /* SCSIQ Microcode representation offsets */
  377 #define ADV_SCSIQ_B_FWD                 0
  378 #define ADV_SCSIQ_B_BWD                 1
  379 #define ADV_SCSIQ_B_STATUS              2
  380 #define ADV_SCSIQ_B_QNO                 3
  381 #define ADV_SCSIQ_B_CNTL                4
  382 #define ADV_SCSIQ_B_SG_QUEUE_CNT        5
  383 #define ADV_SCSIQ_B_LIST_CNT            6
  384 #define ADV_SCSIQ_B_CUR_LIST_CNT        7
  385 #define ADV_SCSIQ_D_DATA_ADDR           8
  386 #define ADV_SCSIQ_D_DATA_CNT            12
  387 #define ADV_SCSIQ_B_SENSE_LEN           20
  388 #define ADV_SCSIQ_DONE_INFO_BEG         22
  389 #define ADV_SCSIQ_D_CINFO_IDX           22
  390 #define ADV_SCSIQ_B_TARGET_IX           26
  391 #define ADV_SCSIQ_B_CDB_LEN             28
  392 #define ADV_SCSIQ_B_TAG_CODE            29
  393 #define ADV_SCSIQ_W_VM_ID               30
  394 #define ADV_SCSIQ_DONE_STATUS           32
  395 #define ADV_SCSIQ_HOST_STATUS           33
  396 #define ADV_SCSIQ_SCSI_STATUS           34
  397 #define ADV_SCSIQ_CDB_BEG               36
  398 #define ADV_SCSIQ_B_FIRST_SG_QK_QP      48
  399 #define ADV_SCSIQ_B_SG_WK_QP            49
  400 #define ADV_SCSIQ_B_SG_WK_IX            50
  401 #define ADV_SCSIQ_W_ALT_DC1             52
  402 #define ADV_SCSIQ_DW_REMAIN_XFER_ADDR   56
  403 #define ADV_SCSIQ_DW_REMAIN_XFER_CNT    60
  404 
  405 /* LRAM Offsets */
  406 #define ADVV_MSGOUT_BEG                 0x0000
  407 #define ADVV_MSGOUT_SDTR_PERIOD         (ADVV_MSGOUT_BEG+3)
  408 #define ADVV_MSGOUT_SDTR_OFFSET         (ADVV_MSGOUT_BEG+4)
  409 
  410 #define ADVV_BREAK_SAVED_CODE           0x0006
  411 
  412 #define ADVV_MSGIN_BEG                  (ADVV_MSGOUT_BEG+8)
  413 #define ADVV_MSGIN_SDTR_PERIOD          (ADVV_MSGIN_BEG+3)
  414 #define ADVV_MSGIN_SDTR_OFFSET          (ADVV_MSGIN_BEG+4)
  415 
  416 #define ADVV_SDTR_DATA_BEG              (ADVV_MSGIN_BEG+8)
  417 #define ADVV_SDTR_DONE_BEG              (ADVV_SDTR_DATA_BEG+8)
  418 #define ADVV_MAX_DVC_QNG_BEG            0x0020
  419 
  420 #define ADVV_BREAK_ADDR                 0x0028
  421 #define ADVV_BREAK_NOTIFY_COUNT         0x002A
  422 #define ADVV_BREAK_CONTROL              0x002C
  423 #define ADVV_BREAK_HIT_COUNT            0x002E
  424 
  425 #define ADVV_ASCDVC_ERR_CODE_W          0x0030
  426 #define ADVV_MCODE_CHKSUM_W             0x0032
  427 #define ADVV_MCODE_SIZE_W               0x0034
  428 #define ADVV_STOP_CODE_B                0x0036
  429 #define ADVV_DVC_ERR_CODE_B             0x0037
  430 
  431 #define ADVV_OVERRUN_PADDR_D            0x0038
  432 #define ADVV_OVERRUN_BSIZE_D            0x003C
  433 
  434 #define ADVV_HALTCODE_W                 0x0040
  435 #define         ADV_HALT_EXTMSG_IN                      0x8000
  436 #define         ADV_HALT_CHK_CONDITION                  0x8100
  437 #define         ADV_HALT_SS_QUEUE_FULL                  0x8200
  438 #define         ADV_HALT_DISABLE_ASYN_USE_SYN_FIX       0x8300
  439 #define         ADV_HALT_ENABLE_ASYN_USE_SYN_FIX        0x8400
  440 #define         ADV_HALT_SDTR_REJECTED                  0x4000
  441 #define         ADV_HALT_HOST_COPY_SG_LIST_TO_RISC      0x2000
  442 
  443 #define ADVV_CHKSUM_W                   0x0042
  444 #define ADVV_MC_DATE_W                  0x0044
  445 #define ADVV_MC_VER_W                   0x0046
  446 #define ADVV_NEXTRDY_B                  0x0048
  447 #define ADVV_DONENEXT_B                 0x0049
  448 #define ADVV_USE_TAGGED_QNG_B           0x004A
  449 #define ADVV_SCSIBUSY_B                 0x004B
  450 #define ADVV_Q_DONE_IN_PROGRESS_B       0x004C
  451 #define ADVV_CURCDB_B                   0x004D
  452 #define ADVV_RCLUN_B                    0x004E
  453 #define ADVV_BUSY_QHEAD_B               0x004F
  454 #define ADVV_DISC1_QHEAD_B              0x0050
  455 
  456 #define ADVV_DISC_ENABLE_B              0x0052
  457 #define ADVV_CAN_TAGGED_QNG_B           0x0053
  458 #define ADVV_HOSTSCSI_ID_B              0x0055
  459 #define ADVV_MCODE_CNTL_B               0x0056
  460 #define ADVV_NULL_TARGET_B              0x0057
  461 
  462 #define ADVV_FREE_Q_HEAD_W              0x0058
  463 #define ADVV_DONE_Q_TAIL_W              0x005A
  464 #define ADVV_FREE_Q_HEAD_B              (ADVV_FREE_Q_HEAD_W+1)
  465 #define ADVV_DONE_Q_TAIL_B              (ADVV_DONE_Q_TAIL_W+1)
  466 
  467 #define ADVV_HOST_FLAG_B                0x005D
  468 #define         ADV_HOST_FLAG_IN_ISR    0x01
  469 #define         ADV_HOST_FLAG_ACK_INT   0x02
  470 
  471 
  472 #define ADVV_TOTAL_READY_Q_B              0x0064
  473 #define ADVV_VER_SERIAL_B                 0x0065
  474 #define ADVV_HALTCODE_SAVED_W             0x0066
  475 #define ADVV_WTM_FLAG_B                   0x0068
  476 #define ADVV_RISC_FLAG_B                  0x006A
  477 #define         ADV_RISC_FLAG_GEN_INT     0x01
  478 #define         ADV_RISC_FLAG_REQ_SG_LIST 0x02
  479 
  480 #define ADVV_REQ_SG_LIST_QP             0x006B
  481 
  482 #define ADV_TRANS_CUR           0x01    /* Modify current neogtiation status */
  483 #define ADV_TRANS_ACTIVE        0x03    /* Assume this is the active target */
  484 #define ADV_TRANS_GOAL          0x04    /* Modify negotiation goal */
  485 #define ADV_TRANS_USER          0x08    /* Modify user negotiation settings */
  486 
  487 struct adv_transinfo {
  488         u_int8_t period;
  489         u_int8_t offset;
  490 };
  491 
  492 struct adv_target_transinfo {
  493         struct adv_transinfo current;
  494         struct adv_transinfo goal;
  495         struct adv_transinfo user;
  496 };
  497 
  498 struct adv_softc {
  499         device_t                 dev;
  500         struct resource         *res;
  501         long                     reg_off;
  502         struct cam_sim          *sim;
  503         LIST_HEAD(, ccb_hdr)     pending_ccbs;
  504         struct adv_ccb_info     *ccb_infos;
  505         SLIST_HEAD(, adv_ccb_info) free_ccb_infos;
  506         bus_dma_tag_t            parent_dmat;
  507         bus_dma_tag_t            buffer_dmat;
  508         bus_dma_tag_t            sense_dmat;
  509         bus_dmamap_t             sense_dmamap;
  510         struct scsi_sense_data  *sense_buffers;
  511         bus_addr_t               sense_physbase;
  512         bus_addr_t               overrun_physbase;
  513         adv_btype                type;
  514         struct                   adv_target_transinfo tinfo[8];
  515         target_bit_vector        fix_asyn_xfer;
  516         target_bit_vector        fix_asyn_xfer_always;
  517         target_bit_vector        disc_enable;
  518         target_bit_vector        user_disc_enable;
  519         target_bit_vector        cmd_qng_enabled;
  520         target_bit_vector        user_cmd_qng_enabled;
  521         u_int16_t                control;
  522 #define         ADV_CNTL_INITIATOR              0x0001
  523 #define         ADV_CNTL_BIOS_GT_1GB            0x0002
  524 #define         ADV_CNTL_BIOS_GT_2_DISK         0x0004
  525 #define         ADV_CNTL_BIOS_REMOVABLE         0x0008
  526 #define         ADV_CNTL_NO_SCAM                0x0010
  527 #define         ADV_CNTL_INT_MULTI_Q            0x0080
  528 #define         ADV_CNTL_NO_LUN_SUPPORT         0x0040
  529 #define         ADV_CNTL_NO_VERIFY_COPY         0x0100
  530 #define         ADV_CNTL_RESET_SCSI             0x0200
  531 #define         ADV_CNTL_INIT_INQUIRY           0x0400
  532 #define         ADV_CNTL_INIT_VERBOSE           0x0800
  533 #define         ADV_CNTL_SCSI_PARITY            0x1000
  534 #define         ADV_CNTL_BURST_MODE             0x2000
  535 #define         ADV_CNTL_SDTR_ENABLE_ULTRA      0x4000
  536         
  537         u_int16_t                bug_fix_control;
  538 #define         ADV_BUG_FIX_IF_NOT_DWB          0x0001
  539 #define         ADV_BUG_FIX_ASYN_USE_SYN        0x0002
  540         
  541         adv_state                state;
  542         struct cam_path         *path;
  543         int                      init_level;
  544         u_int32_t                max_dma_addr;
  545         u_int32_t                max_dma_count;
  546         u_int8_t                 isa_dma_speed;
  547         u_int8_t                 isa_dma_channel;
  548         u_int8_t                 scsi_id;
  549         u_int8_t                 chip_version;
  550         u_int8_t                 max_tags_per_target;
  551         u_int8_t                 max_openings;
  552         u_int8_t                 cur_active;
  553         u_int8_t                 openings_needed;
  554         u_int8_t                 ccb_infos_allocated;
  555         u_int8_t                *sdtr_period_tbl;
  556         u_int8_t                 sdtr_period_tbl_size;
  557         struct mtx               lock;
  558 };
  559 
  560 /*
  561  * Structures for talking to the RISC engine.
  562  */
  563 struct adv_scsiq_1 {
  564         u_int8_t                status;
  565 #define         QS_FREE        0x00
  566 #define         QS_READY       0x01
  567 #define         QS_DISC1       0x02
  568 #define         QS_DISC2       0x04
  569 #define         QS_BUSY        0x08
  570 #define         QS_ABORTED     0x40
  571 #define         QS_DONE        0x80
  572         
  573         u_int8_t                q_no;           /*
  574                                                  * Queue ID of the first queue
  575                                                  * used in this transaction.
  576                                                  */
  577         u_int8_t                cntl;
  578 #define         QC_NO_CALLBACK   0x01
  579 #define         QC_SG_SWAP_QUEUE 0x02
  580 #define         QC_SG_HEAD       0x04
  581 #define         QC_DATA_IN       0x08
  582 #define         QC_DATA_OUT      0x10
  583 #define         QC_URGENT        0x20
  584 #define         QC_MSG_OUT       0x40
  585 #define         QC_REQ_SENSE     0x80
  586         
  587         u_int8_t                sg_queue_cnt;   /* Number of SG entries */
  588 
  589         u_int8_t                target_id;      /* target id as a bit vector */
  590         u_int8_t                target_lun;     /* LUN - taken from our xs */
  591 
  592         u_int32_t               data_addr;      /*
  593                                                  * physical addres of first
  594                                                  * (possibly only) segment
  595                                                  * to transfer.
  596                                                  */
  597         u_int32_t               data_cnt;       /*
  598                                                  * byte count of the first
  599                                                  * (possibly only) segment
  600                                                  * to transfer.
  601                                                  */
  602         u_int32_t               sense_addr;     /*
  603                                                  * physical address of the sense
  604                                                  * buffer.
  605                                                  */
  606         u_int8_t                sense_len;      /* length of sense buffer */
  607         u_int8_t                extra_bytes;
  608 };
  609 
  610 struct adv_scsiq_2 {
  611         u_int32_t               ccb_index;      /* Index to our CCB Info */
  612         u_int8_t                target_ix;      /* Combined TID and LUN */
  613 
  614         u_int8_t                flag;
  615         u_int8_t                cdb_len;        /*
  616                                                  * Number of bytes in the SCSI
  617                                                  * command to execute.
  618                                                  */
  619         u_int8_t                tag_code;       /*
  620                                                  * Tag type for this transaction
  621                                                  * (SIMPLE, ORDERED, HEAD )
  622                                                  */
  623 #define         ADV_TAG_FLAG_EXTRA_BYTES               0x10
  624 #define         ADV_TAG_FLAG_DISABLE_DISCONNECT        0x04
  625 #define         ADV_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX  0x08
  626 #define         ADV_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
  627         
  628         u_int16_t               vm_id;
  629 };
  630 
  631 struct adv_scsiq_3 {
  632         u_int8_t                done_stat;
  633 #define         QD_IN_PROGRESS                  0x00
  634 #define         QD_NO_ERROR                     0x01
  635 #define         QD_ABORTED_BY_HOST              0x02
  636 #define         QD_WITH_ERROR                   0x04
  637 #define         QD_INVALID_REQUEST              0x80
  638 #define         QD_INVALID_HOST_NUM             0x81
  639 #define         QD_INVALID_DEVICE               0x82
  640 #define         QD_ERR_INTERNAL                 0xFF
  641         
  642         u_int8_t                host_stat;
  643 #define         QHSTA_NO_ERROR                  0x00
  644 #define         QHSTA_M_SEL_TIMEOUT             0x11
  645 #define         QHSTA_M_DATA_OVER_RUN           0x12
  646 #define         QHSTA_M_DATA_UNDER_RUN          0x12
  647 #define         QHSTA_M_UNEXPECTED_BUS_FREE     0x13
  648 #define         QHSTA_M_BAD_BUS_PHASE_SEQ       0x14
  649 
  650 #define         QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
  651 #define         QHSTA_D_ASC_DVC_ERROR_CODE_SET  0x22
  652 #define         QHSTA_D_HOST_ABORT_FAILED       0x23
  653 #define         QHSTA_D_EXE_SCSI_Q_FAILED       0x24
  654 #define         QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
  655 #define         QHSTA_D_ASPI_NO_BUF_POOL        0x26
  656 
  657 #define         QHSTA_M_WTM_TIMEOUT             0x41
  658 #define         QHSTA_M_BAD_CMPL_STATUS_IN      0x42
  659 #define         QHSTA_M_NO_AUTO_REQ_SENSE       0x43
  660 #define         QHSTA_M_AUTO_REQ_SENSE_FAIL     0x44
  661 #define         QHSTA_M_TARGET_STATUS_BUSY      0x45
  662 #define         QHSTA_M_BAD_TAG_CODE            0x46
  663 
  664 #define         QHSTA_M_BAD_QUEUE_FULL_OR_BUSY  0x47
  665 #define         QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
  666 
  667 #define         QHSTA_D_LRAM_CMP_ERROR          0x81
  668         
  669 #define         QHSTA_M_MICRO_CODE_ERROR_HALT   0xA1
  670         
  671         u_int8_t                scsi_stat;
  672         u_int8_t                scsi_msg;
  673 };
  674 
  675 struct adv_scsiq_4 {
  676         u_int8_t                cdb[ADV_MAX_CDB_LEN];
  677         u_int8_t                y_first_sg_list_qp;
  678         u_int8_t                y_working_sg_qp;
  679         u_int8_t                y_working_sg_ix;
  680         u_int8_t                y_res;
  681         u_int16_t               x_req_count;
  682         u_int16_t               x_reconnect_rtn;
  683         u_int32_t               x_saved_data_addr;
  684         u_int32_t               x_saved_data_cnt;
  685 };
  686 
  687 struct adv_q_done_info {
  688         struct adv_scsiq_2      d2;
  689         struct adv_scsiq_3      d3;
  690         u_int8_t                q_status;
  691         u_int8_t                q_no;
  692         u_int8_t                cntl;
  693         u_int8_t                sense_len;
  694         u_int8_t                extra_bytes;
  695         u_int8_t                res;
  696         u_int32_t               remain_bytes;
  697 };
  698 
  699 struct adv_sg_entry {
  700         u_int32_t               addr;
  701         u_int32_t               bytes;
  702 };
  703 
  704 struct adv_sg_head {
  705         u_int16_t               entry_cnt;      /*
  706                                                  * Number of SG entries
  707                                                  * in this list
  708                                                  */
  709 
  710         u_int16_t               queue_cnt;      /*
  711                                                  * Number of queues required
  712                                                  * to store entry_cnt
  713                                                  * SG entries.
  714                                                  */
  715 
  716         u_int16_t               entry_to_copy;  /*
  717                                                  * Number of SG entries to
  718                                                  * copy to the board.
  719                                                  */
  720         u_int16_t               res;
  721         struct adv_sg_entry     *sg_list;
  722 };
  723 
  724 #define QCX_SORT        (0x0001)
  725 #define QCX_COALEASE    (0x0002)
  726 
  727 struct adv_scsi_q {
  728         struct adv_scsiq_1      q1;
  729         struct adv_scsiq_2      q2;
  730         u_int8_t                *cdbptr;        /*
  731                                                  * Pointer to the SCSI command
  732                                                  * to execute.
  733                                                  */
  734 
  735         struct adv_sg_head      *sg_head;       /*
  736                                                  * Pointer to possible SG list
  737                                                  */
  738 };
  739 
  740 struct adv_scsi_req_q {
  741         struct adv_scsiq_1      r1;
  742         struct adv_scsiq_2      r2;
  743         u_int8_t                *cdbptr;
  744         struct adv_sg_head      *sg_head;
  745         u_int8_t                *sense_ptr;
  746         struct adv_scsiq_3      r3;
  747         u_int8_t                cdb[ADV_MAX_CDB_LEN];
  748         u_int8_t                sense[ADV_MIN_SENSE_LEN];
  749 };
  750 
  751 struct adv_risc_q {
  752         u_int8_t                fwd;
  753         u_int8_t                bwd;
  754         struct adv_scsiq_1      i1;
  755         struct adv_scsiq_2      i2;
  756         struct adv_scsiq_3      i3;
  757         struct adv_scsiq_4      i4;
  758 };
  759 
  760 struct adv_sg_list_q {
  761         u_int8_t                seq_no;
  762         u_int8_t                q_no;
  763         u_int8_t                cntl;
  764 #define         QCSG_SG_XFER_LIST  0x02
  765 #define         QCSG_SG_XFER_MORE  0x04
  766 #define         QCSG_SG_XFER_END   0x08
  767         
  768         u_int8_t                sg_head_qp;
  769         u_int8_t                sg_list_cnt;
  770         u_int8_t                sg_cur_list_cnt;
  771 };
  772 #define ADV_SGQ_B_SG_CNTL               4
  773 #define ADV_SGQ_B_SG_HEAD_QP            5
  774 #define ADV_SGQ_B_SG_LIST_CNT           6
  775 #define ADV_SGQ_B_SG_CUR_LIST_CNT       7
  776 #define ADV_SGQ_LIST_BEG                8
  777 
  778 struct asc_risc_sg_list_q {
  779         u_int8_t                fwd;
  780         u_int8_t                bwd;
  781         struct adv_sg_list_q    sg;
  782         struct adv_sg_entry     sg_list[ADV_SG_LIST_PER_Q];
  783 };
  784 
  785 /* Chip Register functions */
  786 void      adv_set_bank(struct adv_softc *adv, u_int8_t bank);
  787 
  788 /* LRAM routines */
  789 u_int8_t  adv_read_lram_8(struct adv_softc *adv, u_int16_t addr);
  790 void      adv_write_lram_8(struct adv_softc *adv, u_int16_t addr,
  791                            u_int8_t value);
  792 u_int16_t adv_read_lram_16(struct adv_softc *adv, u_int16_t addr);
  793 void      adv_write_lram_16(struct adv_softc *adv, u_int16_t addr,
  794                             u_int16_t value);
  795 
  796 /* Intialization */
  797 int       adv_find_signature(struct resource *res);
  798 void      adv_lib_init(struct adv_softc *adv);
  799 
  800 u_int16_t adv_get_eeprom_config(struct adv_softc *adv,
  801                                 struct adv_eeprom_config *eeprom_config);
  802 int       adv_set_eeprom_config(struct adv_softc *adv,
  803                                 struct adv_eeprom_config *eeprom_config);
  804 int       adv_reset_chip(struct adv_softc *adv, int reset_bus);
  805 int       adv_test_external_lram(struct adv_softc* adv);
  806 int       adv_init_lram_and_mcode(struct adv_softc *adv);
  807 u_int8_t  adv_get_chip_irq(struct adv_softc *adv);
  808 u_int8_t  adv_set_chip_irq(struct adv_softc *adv, u_int8_t irq_no);
  809 void      adv_set_chip_scsiid(struct adv_softc *adv, int new_id);
  810 
  811 /* Queue handling and execution */
  812 int       adv_execute_scsi_queue(struct adv_softc *adv,
  813                                  struct adv_scsi_q *scsiq,
  814                                  u_int32_t datalen);
  815 u_int8_t  adv_copy_lram_doneq(struct adv_softc *adv, u_int16_t q_addr,
  816                               struct adv_q_done_info *scsiq, u_int32_t max_dma_count);
  817 
  818 /* Chip Control */
  819 int       adv_start_chip(struct adv_softc *adv);
  820 void      adv_start_execution(struct adv_softc *adv);
  821 int       adv_stop_execution(struct adv_softc *adv);
  822 int       adv_stop_chip(struct adv_softc *adv);
  823 int       adv_is_chip_halted(struct adv_softc *adv);
  824 
  825 /* Interrupt processing */
  826 void      adv_ack_interrupt(struct adv_softc *adv);
  827 void      adv_isr_chip_halted(struct adv_softc *adv);
  828 
  829 /* SDTR Conversion */
  830 void      adv_set_syncrate(struct adv_softc *adv, struct cam_path *path,
  831                            u_int target_id, u_int period, u_int offset,
  832                            u_int type);
  833 void      adv_sdtr_to_period_offset(struct adv_softc *adv,
  834                                     u_int8_t sync_data, u_int8_t *period,
  835                                     u_int8_t *offset, int tid);
  836 u_int8_t  adv_period_offset_to_sdtr(struct adv_softc *adv, u_int *period,
  837                                     u_int *offset, int tid);
  838 
  839 /* Error recovery */
  840 union ccb;
  841 int       adv_abort_ccb(struct adv_softc *adv, int target, int lun,
  842                         union ccb *ccb, u_int32_t status, int queued_only);
  843 int       adv_reset_bus(struct adv_softc *adv, int initiate_reset);
  844 
  845 /* Async event callback */
  846 void    advasync(void *callback_arg, u_int32_t code,
  847                  struct cam_path *path, void *arg);
  848 
  849 #define ADV_INB(adv, offset)                    \
  850         bus_read_1((adv)->res, (adv)->reg_off + offset)
  851 #define ADV_INW(adv, offset)                    \
  852         bus_read_2((adv)->res, (adv)->reg_off + offset)
  853 #define ADV_INSB(adv, offset, valp, count)      \
  854         bus_read_multi_1((adv)->res, (adv)->reg_off + offset, valp, count)
  855 
  856 /* These controllers seem to have problems with PIO on some fast processors */
  857 static __inline void ADV_INSW(struct adv_softc *, u_int, u_int16_t *, u_int);
  858 static __inline void
  859 ADV_INSW(struct adv_softc *adv, u_int offset, u_int16_t *valp, u_int count)
  860 {
  861         while (count--)
  862                 *valp++ = bus_read_2(adv->res, adv->reg_off + offset);
  863 }
  864 
  865 #define ADV_OUTB(adv, offset, val)              \
  866         bus_write_1((adv)->res, (adv)->reg_off + offset, val)
  867 #define ADV_OUTW(adv, offset, val)              \
  868         bus_write_2((adv)->res, (adv)->reg_off + offset, val)
  869 
  870 /* These controllers seem to have problems with PIO on some fast processors */
  871 static __inline void ADV_OUTSW(struct adv_softc *, u_int, u_int16_t *, u_int);
  872 static __inline void
  873 ADV_OUTSW(struct adv_softc *adv, u_int offset, u_int16_t *valp, u_int count)
  874 {
  875         while (count--)
  876                 bus_write_2(adv->res, adv->reg_off + offset, *valp++);
  877 }
  878 
  879 #endif /* _ADVLIB_H_ */

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