The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/advansys/advlib.h

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    1 /*
    2  * Definitions for low level routines and data structures
    3  * for the Advanced Systems Inc. SCSI controllers chips.
    4  *
    5  * Copyright (c) 1996-1997 Justin T. Gibbs.
    6  * All rights reserved.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions, and the following disclaimer,
   13  *    without modification, immediately at the beginning of the file.
   14  * 2. Redistributions in binary form must reproduce the above copyright
   15  *    notice, this list of conditions and the following disclaimer in the
   16  *    documentation and/or other materials provided with the distribution.
   17  * 3. The name of the author may not be used to endorse or promote products
   18  *    derived from this software without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
   24  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   30  * SUCH DAMAGE.
   31  *
   32  * $FreeBSD: stable/3/sys/dev/advansys/advlib.h 51257 1999-09-14 04:08:11Z gibbs $
   33  */
   34 /*
   35  * Ported from:
   36  * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
   37  *     
   38  * Copyright (c) 1995-1996 Advanced System Products, Inc.
   39  * All Rights Reserved.
   40  *   
   41  * Redistribution and use in source and binary forms, with or without
   42  * modification, are permitted provided that redistributions of source
   43  * code retain the above copyright notice and this comment without
   44  * modification.
   45  */
   46 
   47 #ifndef _ADVLIB_H_
   48 #define _ADVLIB_H_
   49 
   50 #include <sys/queue.h>
   51 
   52 struct cam_path;
   53 union ccb;
   54 
   55 typedef u_int8_t target_bit_vector;
   56 #define TARGET_BIT_VECTOR_SET -1
   57 #define ADV_SCSI_ID_BITS        3
   58 #define ADV_MAX_TID             7
   59 #define ADV_MAX_LUN             7
   60 
   61 /* Enumeration of board types */
   62 typedef enum {
   63         ADV_NONE        = 0x000,
   64         ADV_ISA         = 0x001,
   65         ADV_ISAPNP      = 0x003,
   66         ADV_VL          = 0x004,
   67         ADV_EISA        = 0x008,
   68         ADV_PCI         = 0x010,
   69         ADV_MCA         = 0x020,
   70         ADV_PCMCIA      = 0x040,
   71         ADV_ULTRA       = 0x100,
   72         ADV_WIDE        = 0x200,
   73         ADV_WIDE32      = 0x400
   74 } adv_btype;
   75 
   76 typedef enum {
   77         ADV_STATE_NONE                  = 0x00
   78 } adv_state;
   79 
   80 typedef enum {
   81         ACCB_FREE               = 0x00,
   82         ACCB_ACTIVE             = 0x01,
   83         ACCB_ABORT_QUEUED       = 0x02,
   84         ACCB_RECOVERY_CCB       = 0x04,
   85         ACCB_RELEASE_SIMQ       = 0x08
   86 } adv_ccb_state;
   87 
   88 struct adv_ccb_info {
   89         adv_ccb_state   state;
   90         bus_dmamap_t    dmamap;
   91         SLIST_ENTRY(adv_ccb_info) links;
   92 };
   93 
   94 #define ccb_cinfo_ptr spriv_ptr0
   95 
   96 #define ADV_SYN_XFER_NO                 8
   97 #define ADV_SYN_MAX_OFFSET              0x0F
   98 #define ADV_DEF_SDTR_OFFSET             0x0F
   99 #define ADV_DEF_SDTR_INDEX              0x00
  100 #define ADV_OVERRUN_BSIZE               0x00000040
  101 #define ADV_MAX_CDB_LEN                 12
  102 #define ADV_MAX_SENSE_LEN               32
  103 #define ADV_MIN_SENSE_LEN               14
  104 
  105 #define ADV_TIDLUN_TO_IX(tid, lun) ((tid) | ((lun) << ADV_SCSI_ID_BITS) )
  106 #define ADV_TID_TO_TARGET_MASK(tid)  (0x01 << (tid))
  107 #define ADV_TIX_TO_TARGET_MASK(tix)  (0x01 << ((tix) & ADV_MAX_TID))
  108 #define ADV_TIX_TO_TID(tix)  ((tix) & ADV_MAX_TID)
  109 #define ADV_TID_TO_TIX(tid)  ((tid) & ADV_MAX_TID)
  110 #define ADV_TIX_TO_LUN(tix)  (((tix) >> ADV_SCSI_ID_BITS) & ADV_MAX_LUN )
  111 
  112 
  113 /*
  114  * XXX
  115  * PnP port addresses
  116  * I believe that these are standard PnP address and should be replaced
  117  * by the values in a central ISA PnP header file when we get one.
  118  */
  119 #define ADV_ISA_PNP_PORT_ADDR  (0x279)
  120 #define ADV_ISA_PNP_PORT_WRITE (ADV_ISA_PNP_PORT_ADDR+0x800)
  121 
  122 /*
  123  * Board Signatures
  124  */
  125 #define ADV_SIGNATURE_WORD                      0x0000
  126 #define          ADV_1000_ID0W                  0x04C1
  127 #define          ADV_1000_ID0W_FIX              0x00C1
  128 
  129 #define ADV_SIGNATURE_BYTE                      0x0001
  130 #define          ADV_1000_ID1B                  0x25    
  131 
  132 #define ADV_REG_IH                              0x0002
  133 #define         ADV_INS_HALTINT                 0x6281
  134 #define         ADV_INS_HALT                    0x6280
  135 #define         ADV_INS_SINT                    0x6200
  136 #define         ADV_INS_RFLAG_WTM               0x7380
  137 
  138 #define ADV_CONFIG_LSW                          0x0002
  139 #define         ADV_CFG_LSW_ISA_DMA_CHANNEL     0x0003
  140 #define         ADV_CFG_LSW_HOST_INT_ON         0x0020
  141 #define         ADV_CFG_LSW_BIOS_ON             0x0040
  142 #define         ADV_CFG_LSW_VERA_BURST_ON       0x0080
  143 #define         ADV_CFG_LSW_SCSI_PARITY_ON      0x0800
  144 #define         ADV_CFG_LSW_SCSIID              0x0700
  145 #define         ADV_CFG_LSW_SCSIID_SHIFT        8
  146 #define ADV_CONFIG_SCSIID(cfg) ((cfg >> ADV_CFG_LSW_SCSIID_SHIFT) & ADV_MAX_TID)
  147         
  148 /*
  149  * Chip Revision Number
  150  */
  151 #define ADV_NONEISA_CHIP_REVISION               0x0003
  152 #define         ADV_CHIP_MIN_VER_VL             0x01
  153 #define         ADV_CHIP_MAX_VER_VL             0x07
  154 #define         ADV_CHIP_MIN_VER_PCI            0x09
  155 #define         ADV_CHIP_MAX_VER_PCI            0x0F
  156 #define         ADV_CHIP_VER_PCI_BIT            0x08
  157 #define         ADV_CHIP_VER_PCI_ULTRA_3150  (ADV_CHIP_VER_PCI_BIT | 0x02)
  158 #define         ADV_CHIP_VER_PCI_ULTRA_3050  (ADV_CHIP_VER_PCI_BIT | 0x03)
  159 #define         ADV_CHIP_MIN_VER_ISA            0x11
  160 #define         ADV_CHIP_MIN_VER_ISA_PNP        0x21
  161 #define         ADV_CHIP_MAX_VER_ISA            0x27
  162 #define         ADV_CHIP_VER_ISA_BIT            0x30
  163 #define         ADV_CHIP_VER_ISAPNP_BIT         0x20
  164 #define         ADV_CHIP_VER_ASYN_BUG           0x21
  165 #define         ADV_CHIP_MIN_VER_EISA           0x41
  166 #define         ADV_CHIP_MAX_VER_EISA           0x47
  167 #define         ADV_CHIP_VER_EISA_BIT           0x40
  168 
  169 #define ADV_CONFIG_MSW                          0x0004
  170 #define         ADV_CFG_MSW_SCSI_TARGET_ON      0x0080
  171 #define         ADV_CFG_MSW_LRAM_8BITS_ON       0x0800
  172 #define         ADV_CFG_MSW_CLR_MASK            0x30C0
  173 
  174 #define ADV_EEPROM_DATA                         0x0006
  175 
  176 #define ADV_EEPROM_CMD                          0x0007
  177 #define         ADV_EEPROM_CMD_READ             0x80
  178 #define         ADV_EEPROM_CMD_WRITE            0x40
  179 #define         ADV_EEPROM_CMD_WRITE_ENABLE     0x30
  180 #define         ADV_EEPROM_CMD_WRITE_DISABLE    0x00
  181 
  182 #define ADV_DMA_SPEED                           0x0007
  183 #define         ADV_DEF_ISA_DMA_SPEED           4
  184 #define ADV_REG_FLAG                            0x0007
  185 
  186 #define ADV_LRAM_DATA                           0x0008
  187 
  188 #define ADV_LRAM_ADDR                           0x000A
  189 
  190 #define ADV_SYN_OFFSET                          0x000B
  191 
  192 #define ADV_REG_PROG_COUNTER                    0x000C
  193 #define         ADV_MCODE_START_ADDR            0x0080
  194 
  195 #define ADV_REG_IFC                             0x000D
  196 #define         ADV_IFC_REG_LOCK                0x00
  197 #define         ADV_IFC_REG_UNLOCK              0x09
  198 #define         ADV_IFC_WR_EN_FILTER            0x10
  199 #define         ADV_IFC_RD_NO_EEPROM            0x10
  200 #define         ADV_IFC_SLEW_RATE               0x20
  201 #define         ADV_IFC_ACT_NEG                 0x40
  202 #define         ADV_IFC_INP_FILTER              0x80
  203 #define         ADV_IFC_INIT_DEFAULT  (ADV_IFC_ACT_NEG | ADV_IFC_REG_UNLOCK)
  204         
  205 #define ADV_CHIP_STATUS                         0x000E
  206 #define         ADV_CSW_TEST1                   0x8000
  207 #define         ADV_CSW_AUTO_CONFIG             0x4000
  208 #define         ADV_CSW_RESERVED1               0x2000
  209 #define         ADV_CSW_IRQ_WRITTEN             0x1000
  210 #define         ADV_CSW_33MHZ_SELECTED          0x0800
  211 #define         ADV_CSW_TEST2                   0x0400
  212 #define         ADV_CSW_TEST3                   0x0200
  213 #define         ADV_CSW_RESERVED2               0x0100
  214 #define         ADV_CSW_DMA_DONE                0x0080
  215 #define         ADV_CSW_FIFO_RDY                0x0040
  216 #define         ADV_CSW_EEP_READ_DONE           0x0020
  217 #define         ADV_CSW_HALTED                  0x0010
  218 #define         ADV_CSW_SCSI_RESET_ACTIVE       0x0008
  219 #define         ADV_CSW_PARITY_ERR              0x0004
  220 #define         ADV_CSW_SCSI_RESET_LATCH        0x0002
  221 #define         ADV_CSW_INT_PENDING             0x0001
  222 /*
  223  * XXX I don't understand the relevence of the naming
  224  * convention change here.  What does CIW stand for?
  225  * Perhaps this is to differentiate read and write
  226  * values?
  227  */
  228 #define         ADV_CIW_INT_ACK                 0x0100
  229 #define         ADV_CIW_TEST1                   0x0200
  230 #define         ADV_CIW_TEST2                   0x0400
  231 #define         ADV_CIW_SEL_33MHZ               0x0800
  232 #define         ADV_CIW_IRQ_ACT                 0x1000
  233 #define         ADV_CIW_CLR_SCSI_RESET_INT      0x1000  
  234 
  235 #define ADV_CHIP_CTRL                           0x000F
  236 #define         ADV_CC_CHIP_RESET               0x80
  237 #define         ADV_CC_SCSI_RESET               0x40
  238 #define         ADV_CC_HALT                     0x20
  239 #define         ADV_CC_SINGLE_STEP              0x10
  240 #define         ADV_CC_DMA_ENABLE               0x08
  241 #define         ADV_CC_TEST                     0x04
  242 #define         ADV_CC_BANK_ONE                 0x02    
  243 #define         ADV_CC_DIAG                     0x01
  244         
  245 #define ADV_HALTCODE_W                          0x0040
  246 #define ADV_STOP_CODE_B                         0x0034
  247 #define         ADV_STOP_REQ_RISC_STOP          0x01
  248 #define         ADV_STOP_ACK_RISC_STOP          0x03
  249 #define         ADV_STOP_CLEAN_UP_BUSY_Q        0x10
  250 #define         ADV_STOP_CLEAN_UP_DISC_Q        0x20
  251 #define         ADV_STOP_HOST_REQ_RISC_HALT     0x40
  252 
  253 /*
  254  * EEPROM routine constants
  255  * XXX What about wide controllers?
  256  * Surely they have space for 8 more targets.
  257  */     
  258 #define ADV_EEPROM_CFG_BEG_VL           2
  259 #define ADV_EEPROM_MAX_ADDR_VL          15
  260 #define ADV_EEPROM_CFG_BEG              32
  261 #define ADV_EEPROM_MAX_ADDR             45
  262 #define ADV_EEPROM_MAX_RETRY            20
  263         
  264 struct adv_eeprom_config {
  265         u_int16_t       cfg_lsw;
  266         
  267         u_int16_t       cfg_msw;
  268 
  269         u_int8_t        init_sdtr;
  270         u_int8_t        disc_enable;
  271 
  272         u_int8_t        use_cmd_qng;
  273         u_int8_t        start_motor;
  274         
  275         u_int8_t        max_total_qng;
  276         u_int8_t        max_tag_qng;
  277         
  278         u_int8_t        bios_scan;
  279         u_int8_t        power_up_wait;
  280 
  281         u_int8_t        no_scam;
  282         u_int8_t        scsi_id_dma_speed;
  283 #define         EEPROM_SCSI_ID_MASK     0x0F
  284 #define         EEPROM_DMA_SPEED_MASK   0xF0
  285 #define         EEPROM_DMA_SPEED(ep)                            \
  286                 (((ep).scsi_id_dma_speed & EEPROM_DMA_SPEED_MASK) >> 4)
  287 #define         EEPROM_SET_DMA_SPEED(ep, speed)                 \
  288                 (ep).scsi_id_dma_speed &= ~EEPROM_DMA_SPEED_MASK;       \
  289                 (ep).scsi_id_dma_speed |=                               \
  290                     (((speed) << 4) & EEPROM_DMA_SPEED_MASK)
  291 #define         EEPROM_SCSIID(ep) ((ep).scsi_id_dma_speed & EEPROM_SCSI_ID_MASK)
  292 #define         EEPROM_SET_SCSIID(ep, id)                       \
  293                 (ep).scsi_id_dma_speed &= ~EEPROM_SCSI_ID_MASK; \
  294                 (ep).scsi_id_dma_speed |= ((id) & EEPROM_SCSI_ID_MASK)
  295         /* XXX What about wide controllers??? */
  296         u_int8_t        sdtr_data[8];
  297         u_int8_t        adapter_info[6];
  298 
  299         u_int16_t       cntl;
  300 
  301         u_int16_t       chksum;
  302 };
  303 
  304 /* Bank 1 */
  305 #define ADV_SEQ_ACCUM                           0x0000
  306 #define ADV_QUEUE_ELEMENT_INDEX                 0x0001
  307 #define ADV_SEQ_INSTRUCTION_HOLD                0x0002
  308 #define ADV_QUEUE_ELEMENT_POINTER               0x0003
  309 #define ADV_HOST_DATA_FIFO_L                    0x0004
  310 #define ADV_HOST_SCSIID                         0x0005
  311 #define ADV_HOST_DATA_FIFO_H                    0x0006
  312 #define ADV_SCSI_CONTROL                        0x0009
  313 #define         SC_SEL                          0x80
  314 #define         SC_BSY                          0x40
  315 #define         SC_ACK                          0x20
  316 #define         SC_REQ                          0x10
  317 #define         SC_ATN                          0x08
  318 #define         SC_IO                           0x04
  319 #define         SC_CD                           0x02
  320 #define         SC_MSG                          0x01
  321 #define ADV_SCSIDATL                            0x000B
  322 #define ADV_DMA_TRANSFER_CNT                    0x000C
  323 #define ADV_DMA_TRANSFER_CNT1                   0x000E
  324 
  325 /*
  326  * Instruction data and code segment addresses,
  327  * and transaction address translation (queues).
  328  * All addresses refer to on board LRAM.
  329  */
  330 #define ADV_DATA_SEC_BEG                0x0080
  331 #define ADV_DATA_SEC_END                0x0080
  332 #define ADV_CODE_SEC_BEG                0x0080
  333 #define ADV_CODE_SEC_END                0x0080
  334 #define ADV_QADR_BEG                    0x4000
  335 #define ADV_QADR_END                    0x7FFF
  336 #define ADV_QLAST_ADR                   0x7FC0
  337 #define ADV_QBLK_SIZE                   0x40
  338 #define ADV_BIOS_DATA_QBEG              0xF8
  339 #define ADV_MAX_QNO                     0xF8
  340 #define ADV_QADR_USED (ADV_MAX_QNO * 64)
  341 #define ADV_QNO_TO_QADDR(q_no) ((ADV_QADR_BEG) + ((u_int16_t)(q_no) << 6))
  342 
  343 #define ADV_MIN_ACTIVE_QNO              0x01
  344 #define ADV_QLINK_END                   0xFF
  345 
  346 #define ADV_MAX_SG_QUEUE                5
  347 #define ADV_SG_LIST_PER_Q               7
  348 #define ADV_MAX_SG_LIST                 (1 + ((ADV_SG_LIST_PER_Q) * (ADV_MAX_SG_QUEUE)))
  349 
  350 #define ADV_MIN_REMAIN_Q                0x02
  351 #define ADV_DEF_MAX_TOTAL_QNG           0xF0
  352 #define ADV_MIN_TAG_Q_PER_DVC           0x04
  353 #define ADV_DEF_TAG_Q_PER_DVC           0x04
  354 #define ADV_MIN_FREE_Q                  ADV_MIN_REMAIN_Q
  355 #define ADV_MIN_TOTAL_QNG               ((ADV_MAX_SG_QUEUE)+(ADV_MIN_FREE_Q))
  356 #define ADV_MAX_TOTAL_QNG               240
  357 #define ADV_MAX_INRAM_TAG_QNG           16
  358 #define ADV_MAX_PCI_INRAM_TOTAL_QNG     20
  359 #define ADV_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
  360 #define ADV_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
  361 
  362 #define ADV_DEF_IRQ_NO                  10
  363 #define ADV_MAX_IRQ_NO                  15
  364 #define ADV_MIN_IRQ_NO                  10
  365 
  366 #define ADV_SCSIQ_CPY_BEG               4
  367 #define ADV_SCSIQ_SGHD_CPY_BEG          2
  368 
  369 /* SCSIQ Microcode representation offsets */
  370 #define ADV_SCSIQ_B_FWD                 0
  371 #define ADV_SCSIQ_B_BWD                 1
  372 #define ADV_SCSIQ_B_STATUS              2
  373 #define ADV_SCSIQ_B_QNO                 3
  374 #define ADV_SCSIQ_B_CNTL                4
  375 #define ADV_SCSIQ_B_SG_QUEUE_CNT        5
  376 #define ADV_SCSIQ_B_LIST_CNT            6
  377 #define ADV_SCSIQ_B_CUR_LIST_CNT        7
  378 #define ADV_SCSIQ_D_DATA_ADDR           8
  379 #define ADV_SCSIQ_D_DATA_CNT            12
  380 #define ADV_SCSIQ_B_SENSE_LEN           20
  381 #define ADV_SCSIQ_DONE_INFO_BEG         22
  382 #define ADV_SCSIQ_D_CCBPTR              22
  383 #define ADV_SCSIQ_B_TARGET_IX           26
  384 #define ADV_SCSIQ_B_CDB_LEN             28
  385 #define ADV_SCSIQ_B_TAG_CODE            29
  386 #define ADV_SCSIQ_W_VM_ID               30
  387 #define ADV_SCSIQ_DONE_STATUS           32
  388 #define ADV_SCSIQ_HOST_STATUS           33
  389 #define ADV_SCSIQ_SCSI_STATUS           34
  390 #define ADV_SCSIQ_CDB_BEG               36
  391 #define ADV_SCSIQ_B_SG_WK_QP            49
  392 #define ADV_SCSIQ_B_SG_WK_IX            50
  393 #define ADV_SCSIQ_W_REQ_COUNT           52
  394 #define ADV_SCSIQ_DW_REMAIN_XFER_ADDR   56
  395 #define ADV_SCSIQ_DW_REMAIN_XFER_CNT    60
  396 
  397 /* LRAM Offsets */
  398 #define ADVV_MSGOUT_BEG                 0x0000
  399 #define ADVV_MSGOUT_SDTR_PERIOD         (ADVV_MSGOUT_BEG+3)
  400 #define ADVV_MSGOUT_SDTR_OFFSET         (ADVV_MSGOUT_BEG+4)
  401 
  402 #define ADVV_BREAK_SAVED_CODE           0x0006
  403 
  404 #define ADVV_MSGIN_BEG                  (ADVV_MSGOUT_BEG+8)
  405 #define ADVV_MSGIN_SDTR_PERIOD          (ADVV_MSGIN_BEG+3)
  406 #define ADVV_MSGIN_SDTR_OFFSET          (ADVV_MSGIN_BEG+4)
  407 
  408 #define ADVV_SDTR_DATA_BEG              (ADVV_MSGIN_BEG+8)
  409 #define ADVV_SDTR_DONE_BEG              (ADVV_SDTR_DATA_BEG+8)
  410 #define ADVV_MAX_DVC_QNG_BEG            0x0020
  411 
  412 #define ADVV_BREAK_ADDR                 0x0028
  413 #define ADVV_BREAK_NOTIFY_COUNT         0x002A
  414 #define ADVV_BREAK_CONTROL              0x002C
  415 #define ADVV_BREAK_HIT_COUNT            0x002E
  416 
  417 #define ADVV_ASCDVC_ERR_CODE_W          0x0030
  418 #define ADVV_MCODE_CHKSUM_W             0x0032
  419 #define ADVV_MCODE_SIZE_W               0x0034
  420 #define ADVV_STOP_CODE_B                0x0036
  421 #define ADVV_DVC_ERR_CODE_B             0x0037
  422 
  423 #define ADVV_OVERRUN_PADDR_D            0x0038
  424 #define ADVV_OVERRUN_BSIZE_D            0x003C
  425 
  426 #define ADVV_HALTCODE_W                 0x0040
  427 #define         ADV_HALT_EXTMSG_IN                      0x8000
  428 #define         ADV_HALT_CHK_CONDITION                  0x8100
  429 #define         ADV_HALT_SS_QUEUE_FULL                  0x8200
  430 #define         ADV_HALT_DISABLE_ASYN_USE_SYN_FIX       0x8300
  431 #define         ADV_HALT_ENABLE_ASYN_USE_SYN_FIX        0x8400
  432 #define         ADV_HALT_SDTR_REJECTED                  0x4000
  433 
  434 #define ADVV_CHKSUM_W                   0x0042
  435 #define ADVV_MC_DATE_W                  0x0044
  436 #define ADVV_MC_VER_W                   0x0046
  437 #define ADVV_NEXTRDY_B                  0x0048
  438 #define ADVV_DONENEXT_B                 0x0049
  439 #define ADVV_USE_TAGGED_QNG_B           0x004A
  440 #define ADVV_SCSIBUSY_B                 0x004B
  441 #define ADVV_Q_DONE_IN_PROGRESS_B       0x004C
  442 #define ADVV_CURCDB_B                   0x004D
  443 #define ADVV_RCLUN_B                    0x004E
  444 #define ADVV_BUSY_QHEAD_B               0x004F
  445 #define ADVV_DISC1_QHEAD_B              0x0050
  446 
  447 #define ADVV_DISC_ENABLE_B              0x0052
  448 #define ADVV_CAN_TAGGED_QNG_B           0x0053
  449 #define ADVV_HOSTSCSI_ID_B              0x0055
  450 #define ADVV_MCODE_CNTL_B               0x0056
  451 #define ADVV_NULL_TARGET_B              0x0057
  452 
  453 #define ADVV_FREE_Q_HEAD_W              0x0058
  454 #define ADVV_DONE_Q_TAIL_W              0x005A
  455 #define ADVV_FREE_Q_HEAD_B              (ADVV_FREE_Q_HEAD_W+1)
  456 #define ADVV_DONE_Q_TAIL_B              (ADVV_DONE_Q_TAIL_W+1)
  457 
  458 #define ADVV_HOST_FLAG_B                0x005D
  459 #define         ADV_HOST_FLAG_IN_ISR    0x01
  460 #define         ADV_HOST_FLAG_ACK_INT   0x02
  461 
  462 
  463 #define ADVV_TOTAL_READY_Q_B              0x0064
  464 #define ADVV_VER_SERIAL_B                 0x0065
  465 #define ADVV_HALTCODE_SAVED_W             0x0066
  466 #define ADVV_WTM_FLAG_B                   0x0068
  467 #define ADVV_RISC_FLAG_B                  0x006A
  468 #define         ADV_RISC_FLAG_GEN_INT     0x01
  469 #define         ADV_RISC_FLAG_REQ_SG_LIST 0x02
  470 
  471 #define ADVV_REQ_SG_LIST_QP             0x006B
  472 
  473 #define ADV_TRANS_CUR           0x01    /* Modify current neogtiation status */
  474 #define ADV_TRANS_ACTIVE        0x03    /* Assume this is the active target */
  475 #define ADV_TRANS_GOAL          0x04    /* Modify negotiation goal */
  476 #define ADV_TRANS_USER          0x08    /* Modify user negotiation settings */
  477 
  478 struct adv_transinfo {
  479         u_int8_t period;
  480         u_int8_t offset;
  481 };
  482 
  483 struct adv_target_transinfo {
  484         struct adv_transinfo current;
  485         struct adv_transinfo goal;
  486         struct adv_transinfo user;
  487 };
  488 
  489 struct adv_softc
  490 {
  491         bus_space_tag_t         tag;
  492         bus_space_handle_t      bsh;
  493         bus_dma_tag_t           parent_dmat;
  494         bus_dma_tag_t           buffer_dmat;
  495         bus_dma_tag_t           sense_dmat;
  496         bus_dmamap_t            sense_dmamap;
  497         struct scsi_sense_data  *sense_buffers;
  498         bus_addr_t              sense_physbase;
  499         bus_addr_t              overrun_physbase;
  500         adv_btype               type;
  501         struct                  adv_target_transinfo tinfo[8];
  502         target_bit_vector       fix_asyn_xfer;
  503         target_bit_vector       fix_asyn_xfer_always;
  504         target_bit_vector       disc_enable;
  505         target_bit_vector       user_disc_enable;
  506         target_bit_vector       cmd_qng_enabled;
  507         target_bit_vector       user_cmd_qng_enabled;
  508         u_int16_t               control;
  509 #define         ADV_CNTL_INITIATOR              0x0001
  510 #define         ADV_CNTL_BIOS_GT_1GB            0x0002
  511 #define         ADV_CNTL_BIOS_GT_2_DISK         0x0004
  512 #define         ADV_CNTL_BIOS_REMOVABLE         0x0008
  513 #define         ADV_CNTL_NO_SCAM                0x0010
  514 #define         ADV_CNTL_INT_MULTI_Q            0x0080
  515 #define         ADV_CNTL_NO_LUN_SUPPORT         0x0040
  516 #define         ADV_CNTL_NO_VERIFY_COPY         0x0100
  517 #define         ADV_CNTL_RESET_SCSI             0x0200
  518 #define         ADV_CNTL_INIT_INQUIRY           0x0400
  519 #define         ADV_CNTL_INIT_VERBOSE           0x0800
  520 #define         ADV_CNTL_SCSI_PARITY            0x1000
  521 #define         ADV_CNTL_BURST_MODE             0x2000
  522 #define         ADV_CNTL_SDTR_ENABLE_ULTRA      0x4000
  523         
  524         u_int16_t               bug_fix_control;
  525 #define         ADV_BUG_FIX_IF_NOT_DWB          0x0001
  526 #define         ADV_BUG_FIX_ASYN_USE_SYN        0x0002
  527         
  528         adv_state               state;
  529         struct cam_path         *path;
  530         int                     unit;
  531         int                     init_level;
  532         u_int32_t               max_dma_addr;
  533         u_int32_t               max_dma_count;
  534         u_int8_t                isa_dma_speed;
  535         u_int8_t                isa_dma_channel;
  536         u_int8_t                scsi_id;
  537         u_int8_t                chip_version;
  538         u_int8_t                max_tags_per_target;
  539         u_int8_t                max_openings;
  540         u_int8_t                cur_active;
  541         u_int8_t                openings_needed;
  542         u_int8_t                *sdtr_period_tbl;
  543         u_int8_t                sdtr_period_tbl_size;
  544         struct cam_sim          *sim;
  545         LIST_HEAD(, ccb_hdr)    pending_ccbs;
  546         SLIST_HEAD(, adv_ccb_info) free_ccb_infos;
  547 };
  548 
  549 /*
  550  * Structures for talking to the RISC engine.
  551  */
  552 struct adv_scsiq_1 {
  553         u_int8_t                status;
  554 #define         QS_FREE        0x00
  555 #define         QS_READY       0x01
  556 #define         QS_DISC1       0x02
  557 #define         QS_DISC2       0x04
  558 #define         QS_BUSY        0x08
  559 #define         QS_ABORTED     0x40
  560 #define         QS_DONE        0x80
  561         
  562         u_int8_t                q_no;           /*
  563                                                  * Queue ID of the first queue
  564                                                  * used in this transaction.
  565                                                  */
  566         u_int8_t                cntl;
  567 #define         QC_NO_CALLBACK   0x01
  568 #define         QC_SG_SWAP_QUEUE 0x02
  569 #define         QC_SG_HEAD       0x04
  570 #define         QC_DATA_IN       0x08
  571 #define         QC_DATA_OUT      0x10
  572 #define         QC_URGENT        0x20
  573 #define         QC_MSG_OUT       0x40
  574 #define         QC_REQ_SENSE     0x80
  575         
  576         u_int8_t                sg_queue_cnt;   /* Number of SG entries */
  577 
  578         u_int8_t                target_id;      /* target id as a bit vector */
  579         u_int8_t                target_lun;     /* LUN - taken from our xs */
  580 
  581         u_int32_t               data_addr;      /*
  582                                                  * physical addres of first
  583                                                  * (possibly only) segment
  584                                                  * to transfer.
  585                                                  */
  586         u_int32_t               data_cnt;       /*
  587                                                  * byte count of the first
  588                                                  * (possibly only) segment
  589                                                  * to transfer.
  590                                                  */
  591         u_int32_t               sense_addr;     /*
  592                                                  * physical address of the sense
  593                                                  * buffer.
  594                                                  */
  595         u_int8_t                sense_len;      /* length of sense buffer */
  596         u_int8_t                extra_bytes;
  597 };
  598 
  599 struct adv_scsiq_2 {
  600         u_int32_t               ccb_ptr;        /* Pointer to our CCB */
  601         u_int8_t                target_ix;      /* Combined TID and LUN */
  602 
  603         u_int8_t                flag;
  604         u_int8_t                cdb_len;        /*
  605                                                  * Number of bytes in the SCSI
  606                                                  * command to execute.
  607                                                  */
  608         u_int8_t                tag_code;       /*
  609                                                  * Tag type for this transaction
  610                                                  * (SIMPLE, ORDERED, HEAD )
  611                                                  */
  612 #define         ADV_TAG_FLAG_EXTRA_BYTES               0x10
  613 #define         ADV_TAG_FLAG_DISABLE_DISCONNECT        0x04
  614 #define         ADV_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX  0x08
  615 #define         ADV_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
  616         
  617         u_int16_t               vm_id;
  618 };
  619 
  620 struct adv_scsiq_3 {
  621         u_int8_t                done_stat;
  622 #define         QD_IN_PROGRESS                  0x00
  623 #define         QD_NO_ERROR                     0x01
  624 #define         QD_ABORTED_BY_HOST              0x02
  625 #define         QD_WITH_ERROR                   0x04
  626 #define         QD_INVALID_REQUEST              0x80
  627 #define         QD_INVALID_HOST_NUM             0x81
  628 #define         QD_INVALID_DEVICE               0x82
  629 #define         QD_ERR_INTERNAL                 0xFF
  630         
  631         u_int8_t                host_stat;
  632 #define         QHSTA_NO_ERROR                  0x00
  633 #define         QHSTA_M_SEL_TIMEOUT             0x11
  634 #define         QHSTA_M_DATA_OVER_RUN           0x12
  635 #define         QHSTA_M_DATA_UNDER_RUN          0x12
  636 #define         QHSTA_M_UNEXPECTED_BUS_FREE     0x13
  637 #define         QHSTA_M_BAD_BUS_PHASE_SEQ       0x14
  638 
  639 #define         QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
  640 #define         QHSTA_D_ASC_DVC_ERROR_CODE_SET  0x22
  641 #define         QHSTA_D_HOST_ABORT_FAILED       0x23
  642 #define         QHSTA_D_EXE_SCSI_Q_FAILED       0x24
  643 #define         QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
  644 #define         QHSTA_D_ASPI_NO_BUF_POOL        0x26
  645 
  646 #define         QHSTA_M_WTM_TIMEOUT             0x41
  647 #define         QHSTA_M_BAD_CMPL_STATUS_IN      0x42
  648 #define         QHSTA_M_NO_AUTO_REQ_SENSE       0x43
  649 #define         QHSTA_M_AUTO_REQ_SENSE_FAIL     0x44
  650 #define         QHSTA_M_TARGET_STATUS_BUSY      0x45
  651 #define         QHSTA_M_BAD_TAG_CODE            0x46
  652 
  653 #define         QHSTA_M_BAD_QUEUE_FULL_OR_BUSY  0x47
  654 #define         QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
  655 
  656 #define         QHSTA_D_LRAM_CMP_ERROR          0x81
  657         
  658 #define         QHSTA_M_MICRO_CODE_ERROR_HALT   0xA1
  659         
  660         u_int8_t                scsi_stat;
  661         u_int8_t                scsi_msg;
  662 };
  663 
  664 struct adv_scsiq_4 {
  665         u_int8_t                cdb[ADV_MAX_CDB_LEN];
  666         u_int8_t                y_first_sg_list_qp;
  667         u_int8_t                y_working_sg_qp;
  668         u_int8_t                y_working_sg_ix;
  669         u_int8_t                y_res;
  670         u_int16_t               x_req_count;
  671         u_int16_t               x_reconnect_rtn;
  672         u_int32_t               x_saved_data_addr;
  673         u_int32_t               x_saved_data_cnt;
  674 };
  675 
  676 struct adv_q_done_info {
  677         struct adv_scsiq_2      d2;
  678         struct adv_scsiq_3      d3;
  679         u_int8_t                q_status;
  680         u_int8_t                q_no;
  681         u_int8_t                cntl;
  682         u_int8_t                sense_len;
  683         u_int8_t                extra_bytes;
  684         u_int8_t                res;
  685         u_int32_t               remain_bytes;
  686 };
  687 
  688 struct adv_sg_entry {
  689         u_int32_t               addr;
  690         u_int32_t               bytes;
  691 };
  692 
  693 struct adv_sg_head {
  694         u_int16_t               entry_cnt;      /*
  695                                                  * Number of SG entries
  696                                                  * in this list
  697                                                  */
  698 
  699         u_int16_t               queue_cnt;      /*
  700                                                  * Number of queues required
  701                                                  * to store entry_cnt
  702                                                  * SG entries.
  703                                                  */
  704 
  705         u_int16_t               entry_to_copy;  /*
  706                                                  * Number of SG entries to
  707                                                  * copy to the board.
  708                                                  */
  709         u_int16_t               res;
  710         struct adv_sg_entry     *sg_list;
  711 };
  712 
  713 #define QCX_SORT        (0x0001)
  714 #define QCX_COALEASE    (0x0002)
  715 
  716 struct adv_scsi_q {
  717         struct adv_scsiq_1      q1;
  718         struct adv_scsiq_2      q2;
  719         u_int8_t                *cdbptr;        /*
  720                                                  * Pointer to the SCSI command
  721                                                  * to execute.
  722                                                  */
  723 
  724         struct adv_sg_head      *sg_head;       /*
  725                                                  * Pointer to possible SG list
  726                                                  */
  727 };
  728 
  729 struct adv_scsi_req_q {
  730         struct adv_scsiq_1      r1;
  731         struct adv_scsiq_2      r2;
  732         u_int8_t                *cdbptr;
  733         struct adv_sg_head      *sg_head;
  734         u_int8_t                *sense_ptr;
  735         struct adv_scsiq_3      r3;
  736         u_int8_t                cdb[ADV_MAX_CDB_LEN];
  737         u_int8_t                sense[ADV_MIN_SENSE_LEN];
  738 };
  739 
  740 struct adv_risc_q {
  741         u_int8_t                fwd;
  742         u_int8_t                bwd;
  743         struct adv_scsiq_1      i1;
  744         struct adv_scsiq_2      i2;
  745         struct adv_scsiq_3      i3;
  746         struct adv_scsiq_4      i4;
  747 };
  748 
  749 struct adv_sg_list_q {
  750         u_int8_t                seq_no;
  751         u_int8_t                q_no;
  752         u_int8_t                cntl;
  753 #define         QCSG_SG_XFER_LIST  0x02
  754 #define         QCSG_SG_XFER_MORE  0x04
  755 #define         QCSG_SG_XFER_END   0x08
  756         
  757         u_int8_t                sg_head_qp;
  758         u_int8_t                sg_list_cnt;
  759         u_int8_t                sg_cur_list_cnt;
  760 };
  761 #define ADV_SGQ_B_SG_CNTL               4
  762 #define ADV_SGQ_B_SG_HEAD_QP            5
  763 #define ADV_SGQ_B_SG_LIST_CNT           6
  764 #define ADV_SGQ_B_SG_CUR_LIST_CNT       7
  765 #define ADV_SGQ_LIST_BEG                8
  766 
  767 struct asc_risc_sg_list_q {
  768         u_int8_t                fwd;
  769         u_int8_t                bwd;
  770         struct adv_sg_list_q    sg;
  771         struct adv_sg_entry     sg_list[ADV_SG_LIST_PER_Q];
  772 };
  773 
  774 /* Chip Register functions */
  775 void      adv_set_bank(struct adv_softc *adv, u_int8_t bank);
  776 
  777 /* LRAM routines */
  778 u_int8_t  adv_read_lram_8(struct adv_softc *adv, u_int16_t addr);
  779 void      adv_write_lram_8(struct adv_softc *adv, u_int16_t addr,
  780                            u_int8_t value);
  781 u_int16_t adv_read_lram_16(struct adv_softc *adv, u_int16_t addr);
  782 void      adv_write_lram_16(struct adv_softc *adv, u_int16_t addr,
  783                             u_int16_t value);
  784 
  785 /* Intialization */
  786 int       adv_find_signature(bus_space_tag_t tag, bus_space_handle_t bsh);
  787 void      adv_lib_init(struct adv_softc *adv);
  788 
  789 u_int16_t adv_get_eeprom_config(struct adv_softc *adv,
  790                                 struct adv_eeprom_config *eeprom_config);
  791 int       adv_set_eeprom_config(struct adv_softc *adv,
  792                                 struct adv_eeprom_config *eeprom_config);
  793 int       adv_reset_chip_and_scsi_bus(struct adv_softc *adv);
  794 int       adv_test_external_lram(struct adv_softc* adv);
  795 int       adv_init_lram_and_mcode(struct adv_softc *adv);
  796 u_int8_t  adv_get_chip_irq(struct adv_softc *adv);
  797 u_int8_t  adv_set_chip_irq(struct adv_softc *adv, u_int8_t irq_no);
  798 void      adv_set_chip_scsiid(struct adv_softc *adv, int new_id);
  799 
  800 /* Queue handling and execution */
  801 int       adv_execute_scsi_queue(struct adv_softc *adv,
  802                                  struct adv_scsi_q *scsiq,
  803                                  u_int32_t datalen);
  804 u_int8_t  adv_copy_lram_doneq(struct adv_softc *adv, u_int16_t q_addr,
  805                               struct adv_q_done_info *scsiq, u_int32_t max_dma_count);
  806 
  807 /* Chip Control */
  808 int       adv_start_chip(struct adv_softc *adv);
  809 void      adv_start_execution(struct adv_softc *adv);
  810 int       adv_stop_execution(struct adv_softc *adv);
  811 int       adv_is_chip_halted(struct adv_softc *adv);
  812 
  813 /* Interrupt processing */
  814 void      adv_ack_interrupt(struct adv_softc *adv);
  815 void      adv_isr_chip_halted(struct adv_softc *adv);
  816 
  817 /* SDTR Conversion */
  818 void      adv_set_syncrate(struct adv_softc *adv, struct cam_path *path,
  819                            u_int target_id, u_int period, u_int offset,
  820                            u_int type);
  821 void      adv_sdtr_to_period_offset(struct adv_softc *adv,
  822                                     u_int8_t sync_data, u_int8_t *period,
  823                                     u_int8_t *offset, int tid);
  824 u_int8_t  adv_period_offset_to_sdtr(struct adv_softc *adv, u_int *period,
  825                                     u_int *offset, int tid);
  826 
  827 /* Error recovery */
  828 int       adv_abort_ccb(struct adv_softc *adv, int target, int lun,
  829                         union ccb *ccb, u_int32_t status, int queued_only);
  830 int       adv_reset_bus(struct adv_softc *adv);
  831 
  832 /* Async event callback */
  833 void    advasync(void *callback_arg, u_int32_t code,
  834                  struct cam_path *path, void *arg);
  835 
  836 #define ADV_INB(adv, offset)                    \
  837         bus_space_read_1((adv)->tag, (adv)->bsh, offset)
  838 #define ADV_INW(adv, offset)                    \
  839         bus_space_read_2((adv)->tag, (adv)->bsh, offset)
  840 #define ADV_INSB(adv, offset, valp, count)      \
  841         bus_space_read_multi_1((adv)->tag, (adv)->bsh, offset, valp, count)
  842 
  843 /* These controllers seem to have problems with PIO on some fast processors */
  844 static __inline void ADV_INSW(struct adv_softc *, u_int, u_int16_t *, u_int);
  845 static __inline void
  846 ADV_INSW(struct adv_softc *adv, u_int offset, u_int16_t *valp, u_int count)
  847 {
  848         while (count--)
  849                 *valp++ = bus_space_read_2(adv->tag, adv->bsh, offset);
  850 }
  851 
  852 #define ADV_OUTB(adv, offset, val)              \
  853         bus_space_write_1((adv)->tag, (adv)->bsh, offset, val)
  854 #define ADV_OUTW(adv, offset, val)              \
  855         bus_space_write_2((adv)->tag, (adv)->bsh, offset, val)
  856 
  857 /* These controllers seem to have problems with PIO on some fast processors */
  858 static __inline void ADV_OUTSW(struct adv_softc *, u_int, u_int16_t *, u_int);
  859 static __inline void
  860 ADV_OUTSW(struct adv_softc *adv, u_int offset, u_int16_t *valp, u_int count)
  861 {
  862         while (count--)
  863                 bus_space_write_2(adv->tag, adv->bsh, offset, *valp++);
  864 }
  865 
  866 #endif /* _ADVLIB_H_ */

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