1 /*
2 * Device probe and attach routines for the following
3 * Advanced Systems Inc. SCSI controllers:
4 *
5 * ABP[3]940UW - Bus-Master PCI Ultra-Wide (253 CDB)
6 * ABP950UW - Dual Channel Bus-Master PCI Ultra-Wide (253 CDB/Channel)
7 * ABP970UW - Bus-Master PCI Ultra-Wide (253 CDB)
8 * ABP3940U2W - Bus-Master PCI LVD/Ultra2-Wide (253 CDB)
9 * ABP3950U2W - Bus-Master PCI LVD/Ultra2-Wide (253 CDB)
10 *
11 * Copyright (c) 1998, 1999, 2000 Justin Gibbs.
12 * All rights reserved.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions, and the following disclaimer,
19 * without modification.
20 * 2. The name of the author may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
27 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 *
35 * $FreeBSD: releng/5.0/sys/dev/advansys/adw_pci.c 104707 2002-10-09 08:50:26Z peter $
36 */
37
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <sys/bus.h>
43
44 #include <machine/bus_pio.h>
45 #include <machine/bus.h>
46 #include <machine/resource.h>
47
48 #include <sys/rman.h>
49
50 #include <pci/pcireg.h>
51 #include <pci/pcivar.h>
52
53 #include <cam/cam.h>
54 #include <cam/scsi/scsi_all.h>
55
56 #include <dev/advansys/adwvar.h>
57 #include <dev/advansys/adwlib.h>
58 #include <dev/advansys/adwmcode.h>
59
60 #define ADW_PCI_IOBASE PCIR_MAPS /* I/O Address */
61 #define ADW_PCI_MEMBASE PCIR_MAPS + 4 /* Mem I/O Address */
62
63 #define PCI_ID_ADVANSYS_3550 0x230010CD00000000ull
64 #define PCI_ID_ADVANSYS_38C0800_REV1 0x250010CD00000000ull
65 #define PCI_ID_ADVANSYS_38C1600_REV1 0x270010CD00000000ull
66 #define PCI_ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
67 #define PCI_ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
68
69 struct adw_pci_identity;
70 typedef int (adw_device_setup_t)(device_t, struct adw_pci_identity *,
71 struct adw_softc *adw);
72
73 struct adw_pci_identity {
74 u_int64_t full_id;
75 u_int64_t id_mask;
76 char *name;
77 adw_device_setup_t *setup;
78 const struct adw_mcode *mcode_data;
79 const struct adw_eeprom *default_eeprom;
80 };
81
82 static adw_device_setup_t adw_asc3550_setup;
83 static adw_device_setup_t adw_asc38C0800_setup;
84 #ifdef NOTYET
85 static adw_device_setup_t adw_asc38C1600_setup;
86 #endif
87
88 struct adw_pci_identity adw_pci_ident_table[] =
89 {
90 /* asc3550 based controllers */
91 {
92 PCI_ID_ADVANSYS_3550,
93 PCI_ID_DEV_VENDOR_MASK,
94 "AdvanSys 3550 Ultra SCSI Adapter",
95 adw_asc3550_setup,
96 &adw_asc3550_mcode_data,
97 &adw_asc3550_default_eeprom
98 },
99 /* asc38C0800 based controllers */
100 {
101 PCI_ID_ADVANSYS_38C0800_REV1,
102 PCI_ID_DEV_VENDOR_MASK,
103 "AdvanSys 38C0800 Ultra2 SCSI Adapter",
104 adw_asc38C0800_setup,
105 &adw_asc38C0800_mcode_data,
106 &adw_asc38C0800_default_eeprom
107 },
108 #if NOTYET
109 /* XXX Disabled until I have hardware to test with */
110 /* asc38C1600 based controllers */
111 {
112 PCI_ID_ADVANSYS_38C1600_REV1,
113 PCI_ID_DEV_VENDOR_MASK,
114 "AdvanSys 38C1600 Ultra160 SCSI Adapter",
115 adw_asc38C1600_setup,
116 NULL, /* None provided by vendor thus far */
117 NULL /* None provided by vendor thus far */
118 }
119 #endif
120 };
121
122 static const int adw_num_pci_devs =
123 sizeof(adw_pci_ident_table) / sizeof(*adw_pci_ident_table);
124
125 #define ADW_PCI_MAX_DMA_ADDR (0xFFFFFFFFUL)
126 #define ADW_PCI_MAX_DMA_COUNT (0xFFFFFFFFUL)
127
128 static int adw_pci_probe(device_t dev);
129 static int adw_pci_attach(device_t dev);
130
131 static device_method_t adw_pci_methods[] = {
132 /* Device interface */
133 DEVMETHOD(device_probe, adw_pci_probe),
134 DEVMETHOD(device_attach, adw_pci_attach),
135 { 0, 0 }
136 };
137
138 static driver_t adw_pci_driver = {
139 "adw",
140 adw_pci_methods,
141 sizeof(struct adw_softc)
142 };
143
144 static devclass_t adw_devclass;
145
146 DRIVER_MODULE(adw, pci, adw_pci_driver, adw_devclass, 0, 0);
147
148 static __inline u_int64_t
149 adw_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
150 {
151 u_int64_t id;
152
153 id = subvendor
154 | (subdevice << 16)
155 | ((u_int64_t)vendor << 32)
156 | ((u_int64_t)device << 48);
157
158 return (id);
159 }
160
161 static struct adw_pci_identity *
162 adw_find_pci_device(device_t dev)
163 {
164 u_int64_t full_id;
165 struct adw_pci_identity *entry;
166 u_int i;
167
168 full_id = adw_compose_id(pci_get_device(dev),
169 pci_get_vendor(dev),
170 pci_get_subdevice(dev),
171 pci_get_subvendor(dev));
172
173 for (i = 0; i < adw_num_pci_devs; i++) {
174 entry = &adw_pci_ident_table[i];
175 if (entry->full_id == (full_id & entry->id_mask))
176 return (entry);
177 }
178 return (NULL);
179 }
180
181 static int
182 adw_pci_probe(device_t dev)
183 {
184 struct adw_pci_identity *entry;
185
186 entry = adw_find_pci_device(dev);
187 if (entry != NULL) {
188 device_set_desc(dev, entry->name);
189 return (0);
190 }
191 return (ENXIO);
192 }
193
194 static int
195 adw_pci_attach(device_t dev)
196 {
197 struct adw_softc *adw;
198 struct adw_pci_identity *entry;
199 u_int32_t command;
200 struct resource *regs;
201 int regs_type;
202 int regs_id;
203 int error;
204 int zero;
205
206 command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1);
207 entry = adw_find_pci_device(dev);
208 if (entry == NULL)
209 return (ENXIO);
210 regs = NULL;
211 regs_type = 0;
212 regs_id = 0;
213 #ifdef ADW_ALLOW_MEMIO
214 if ((command & PCIM_CMD_MEMEN) != 0) {
215 regs_type = SYS_RES_MEMORY;
216 regs_id = ADW_PCI_MEMBASE;
217 regs = bus_alloc_resource(dev, regs_type,
218 ®s_id, 0, ~0, 1, RF_ACTIVE);
219 }
220 #endif
221 if (regs == NULL && (command & PCIM_CMD_PORTEN) != 0) {
222 regs_type = SYS_RES_IOPORT;
223 regs_id = ADW_PCI_IOBASE;
224 regs = bus_alloc_resource(dev, regs_type,
225 ®s_id, 0, ~0, 1, RF_ACTIVE);
226 }
227
228 if (regs == NULL) {
229 device_printf(dev, "can't allocate register resources\n");
230 return (ENOMEM);
231 }
232
233 adw = adw_alloc(dev, regs, regs_type, regs_id);
234 if (adw == NULL)
235 return(ENOMEM);
236
237 /*
238 * Now that we have access to our registers, just verify that
239 * this really is an AdvanSys device.
240 */
241 if (adw_find_signature(adw) == 0) {
242 adw_free(adw);
243 return (ENXIO);
244 }
245
246 adw_reset_chip(adw);
247
248 error = entry->setup(dev, entry, adw);
249
250 if (error != 0)
251 return (error);
252
253 /* Ensure busmastering is enabled */
254 command |= PCIM_CMD_BUSMASTEREN;
255 pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1);
256
257 /* Allocate a dmatag for our transfer DMA maps */
258 /* XXX Should be a child of the PCI bus dma tag */
259 error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/1,
260 /*boundary*/0,
261 /*lowaddr*/ADW_PCI_MAX_DMA_ADDR,
262 /*highaddr*/BUS_SPACE_MAXADDR,
263 /*filter*/NULL, /*filterarg*/NULL,
264 /*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
265 /*nsegments*/~0,
266 /*maxsegsz*/ADW_PCI_MAX_DMA_COUNT,
267 /*flags*/0,
268 &adw->parent_dmat);
269
270 adw->init_level++;
271
272 if (error != 0) {
273 printf("%s: Could not allocate DMA tag - error %d\n",
274 adw_name(adw), error);
275 adw_free(adw);
276 return (error);
277 }
278
279 adw->init_level++;
280
281 error = adw_init(adw);
282 if (error != 0) {
283 adw_free(adw);
284 return (error);
285 }
286
287 /*
288 * If the PCI Configuration Command Register "Parity Error Response
289 * Control" Bit was clear (0), then set the microcode variable
290 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
291 * to ignore DMA parity errors.
292 */
293 if ((command & PCIM_CMD_PERRESPEN) == 0)
294 adw_lram_write_16(adw, ADW_MC_CONTROL_FLAG,
295 adw_lram_read_16(adw, ADW_MC_CONTROL_FLAG)
296 | ADW_MC_CONTROL_IGN_PERR);
297
298 zero = 0;
299 adw->irq_res_type = SYS_RES_IRQ;
300 adw->irq = bus_alloc_resource(dev, adw->irq_res_type, &zero,
301 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
302 if (adw->irq == NULL) {
303 adw_free(adw);
304 return (ENOMEM);
305 }
306
307 error = adw_attach(adw);
308 if (error != 0)
309 adw_free(adw);
310 return (error);
311 }
312
313 static int
314 adw_generic_setup(device_t dev, struct adw_pci_identity *entry,
315 struct adw_softc *adw)
316 {
317 adw->channel = pci_get_function(dev) == 1 ? 'B' : 'A';
318 adw->chip = ADW_CHIP_NONE;
319 adw->features = ADW_FENONE;
320 adw->flags = ADW_FNONE;
321 adw->mcode_data = entry->mcode_data;
322 adw->default_eeprom = entry->default_eeprom;
323 return (0);
324 }
325
326 static int
327 adw_asc3550_setup(device_t dev, struct adw_pci_identity *entry,
328 struct adw_softc *adw)
329 {
330 int error;
331
332 error = adw_generic_setup(dev, entry, adw);
333 if (error != 0)
334 return (error);
335 adw->chip = ADW_CHIP_ASC3550;
336 adw->features = ADW_ASC3550_FE;
337 adw->memsize = ADW_3550_MEMSIZE;
338 /*
339 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits
340 * sets a FIFO threshold of 128 bytes. This register is
341 * only accessible to the host.
342 */
343 adw_outb(adw, ADW_DMA_CFG0,
344 ADW_DMA_CFG0_START_CTL_EM_FU|ADW_DMA_CFG0_READ_CMD_MRM);
345 adw_outb(adw, ADW_MEM_CFG,
346 adw_inb(adw, ADW_MEM_CFG) | ADW_MEM_CFG_RAM_SZ_8KB);
347 return (0);
348 }
349
350 static int
351 adw_asc38C0800_setup(device_t dev, struct adw_pci_identity *entry,
352 struct adw_softc *adw)
353 {
354 int error;
355
356 error = adw_generic_setup(dev, entry, adw);
357 if (error != 0)
358 return (error);
359 /*
360 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and
361 * START_CTL_TH [3:2] bits for the default FIFO threshold.
362 *
363 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
364 *
365 * For DMA Errata #4 set the BC_THRESH_ENB bit.
366 */
367 adw_outb(adw, ADW_DMA_CFG0,
368 ADW_DMA_CFG0_BC_THRESH_ENB|ADW_DMA_CFG0_FIFO_THRESH_80B
369 |ADW_DMA_CFG0_START_CTL_TH|ADW_DMA_CFG0_READ_CMD_MRM);
370 adw_outb(adw, ADW_MEM_CFG,
371 adw_inb(adw, ADW_MEM_CFG) | ADW_MEM_CFG_RAM_SZ_16KB);
372 adw->chip = ADW_CHIP_ASC38C0800;
373 adw->features = ADW_ASC38C0800_FE;
374 adw->memsize = ADW_38C0800_MEMSIZE;
375 return (error);
376 }
377
378 #ifdef NOTYET
379 static int
380 adw_asc38C1600_setup(device_t dev, struct adw_pci_identity *entry,
381 struct adw_softc *adw)
382 {
383 int error;
384
385 error = adw_generic_setup(dev, entry, adw);
386 if (error != 0)
387 return (error);
388 adw->chip = ADW_CHIP_ASC38C1600;
389 adw->features = ADW_ASC38C1600_FE;
390 adw->memsize = ADW_38C1600_MEMSIZE;
391 return (error);
392 }
393 #endif
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