1 /*-
2 * CAM SCSI interface for the the Advanced Systems Inc.
3 * Second Generation SCSI controllers.
4 *
5 * Product specific probe and attach routines can be found in:
6 *
7 * adw_pci.c ABP[3]940UW, ABP950UW, ABP3940U2W
8 *
9 * Copyright (c) 1998, 1999, 2000 Justin Gibbs.
10 * All rights reserved.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions, and the following disclaimer,
17 * without modification.
18 * 2. The name of the author may not be used to endorse or promote products
19 * derived from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 */
33 /*
34 * Ported from:
35 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
36 *
37 * Copyright (c) 1995-1998 Advanced System Products, Inc.
38 * All Rights Reserved.
39 *
40 * Redistribution and use in source and binary forms, with or without
41 * modification, are permitted provided that redistributions of source
42 * code retain the above copyright notice and this comment without
43 * modification.
44 */
45
46 #include <sys/cdefs.h>
47 __FBSDID("$FreeBSD: releng/6.3/sys/dev/advansys/adwcam.c 165194 2006-12-14 02:57:07Z mjacob $");
48
49 #include <sys/param.h>
50 #include <sys/systm.h>
51 #include <sys/kernel.h>
52 #include <sys/malloc.h>
53 #include <sys/lock.h>
54 #include <sys/module.h>
55 #include <sys/mutex.h>
56 #include <sys/bus.h>
57
58 #include <machine/bus.h>
59 #include <machine/resource.h>
60
61 #include <sys/rman.h>
62
63 #include <cam/cam.h>
64 #include <cam/cam_ccb.h>
65 #include <cam/cam_sim.h>
66 #include <cam/cam_xpt_sim.h>
67 #include <cam/cam_debug.h>
68
69 #include <cam/scsi/scsi_message.h>
70
71 #include <dev/advansys/adwvar.h>
72
73 /* Definitions for our use of the SIM private CCB area */
74 #define ccb_acb_ptr spriv_ptr0
75 #define ccb_adw_ptr spriv_ptr1
76
77 u_long adw_unit;
78
79 static __inline cam_status adwccbstatus(union ccb*);
80 static __inline struct acb* adwgetacb(struct adw_softc *adw);
81 static __inline void adwfreeacb(struct adw_softc *adw,
82 struct acb *acb);
83
84 static void adwmapmem(void *arg, bus_dma_segment_t *segs,
85 int nseg, int error);
86 static struct sg_map_node*
87 adwallocsgmap(struct adw_softc *adw);
88 static int adwallocacbs(struct adw_softc *adw);
89
90 static void adwexecuteacb(void *arg, bus_dma_segment_t *dm_segs,
91 int nseg, int error);
92 static void adw_action(struct cam_sim *sim, union ccb *ccb);
93 static void adw_poll(struct cam_sim *sim);
94 static void adw_async(void *callback_arg, u_int32_t code,
95 struct cam_path *path, void *arg);
96 static void adwprocesserror(struct adw_softc *adw, struct acb *acb);
97 static void adwtimeout(void *arg);
98 static void adw_handle_device_reset(struct adw_softc *adw,
99 u_int target);
100 static void adw_handle_bus_reset(struct adw_softc *adw,
101 int initiated);
102
103 static __inline cam_status
104 adwccbstatus(union ccb* ccb)
105 {
106 return (ccb->ccb_h.status & CAM_STATUS_MASK);
107 }
108
109 static __inline struct acb*
110 adwgetacb(struct adw_softc *adw)
111 {
112 struct acb* acb;
113 int s;
114
115 s = splcam();
116 if ((acb = SLIST_FIRST(&adw->free_acb_list)) != NULL) {
117 SLIST_REMOVE_HEAD(&adw->free_acb_list, links);
118 } else if (adw->num_acbs < adw->max_acbs) {
119 adwallocacbs(adw);
120 acb = SLIST_FIRST(&adw->free_acb_list);
121 if (acb == NULL)
122 printf("%s: Can't malloc ACB\n", adw_name(adw));
123 else {
124 SLIST_REMOVE_HEAD(&adw->free_acb_list, links);
125 }
126 }
127 splx(s);
128
129 return (acb);
130 }
131
132 static __inline void
133 adwfreeacb(struct adw_softc *adw, struct acb *acb)
134 {
135 int s;
136
137 s = splcam();
138 if ((acb->state & ACB_ACTIVE) != 0)
139 LIST_REMOVE(&acb->ccb->ccb_h, sim_links.le);
140 if ((acb->state & ACB_RELEASE_SIMQ) != 0)
141 acb->ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
142 else if ((adw->state & ADW_RESOURCE_SHORTAGE) != 0
143 && (acb->ccb->ccb_h.status & CAM_RELEASE_SIMQ) == 0) {
144 acb->ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
145 adw->state &= ~ADW_RESOURCE_SHORTAGE;
146 }
147 acb->state = ACB_FREE;
148 SLIST_INSERT_HEAD(&adw->free_acb_list, acb, links);
149 splx(s);
150 }
151
152 static void
153 adwmapmem(void *arg, bus_dma_segment_t *segs, int nseg, int error)
154 {
155 bus_addr_t *busaddrp;
156
157 busaddrp = (bus_addr_t *)arg;
158 *busaddrp = segs->ds_addr;
159 }
160
161 static struct sg_map_node *
162 adwallocsgmap(struct adw_softc *adw)
163 {
164 struct sg_map_node *sg_map;
165
166 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT);
167
168 if (sg_map == NULL)
169 return (NULL);
170
171 /* Allocate S/G space for the next batch of ACBS */
172 if (bus_dmamem_alloc(adw->sg_dmat, (void **)&sg_map->sg_vaddr,
173 BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) {
174 free(sg_map, M_DEVBUF);
175 return (NULL);
176 }
177
178 SLIST_INSERT_HEAD(&adw->sg_maps, sg_map, links);
179
180 bus_dmamap_load(adw->sg_dmat, sg_map->sg_dmamap, sg_map->sg_vaddr,
181 PAGE_SIZE, adwmapmem, &sg_map->sg_physaddr, /*flags*/0);
182
183 bzero(sg_map->sg_vaddr, PAGE_SIZE);
184 return (sg_map);
185 }
186
187 /*
188 * Allocate another chunk of CCB's. Return count of entries added.
189 * Assumed to be called at splcam().
190 */
191 static int
192 adwallocacbs(struct adw_softc *adw)
193 {
194 struct acb *next_acb;
195 struct sg_map_node *sg_map;
196 bus_addr_t busaddr;
197 struct adw_sg_block *blocks;
198 int newcount;
199 int i;
200
201 next_acb = &adw->acbs[adw->num_acbs];
202 sg_map = adwallocsgmap(adw);
203
204 if (sg_map == NULL)
205 return (0);
206
207 blocks = sg_map->sg_vaddr;
208 busaddr = sg_map->sg_physaddr;
209
210 newcount = (PAGE_SIZE / (ADW_SG_BLOCKCNT * sizeof(*blocks)));
211 for (i = 0; adw->num_acbs < adw->max_acbs && i < newcount; i++) {
212 int error;
213
214 error = bus_dmamap_create(adw->buffer_dmat, /*flags*/0,
215 &next_acb->dmamap);
216 if (error != 0)
217 break;
218 next_acb->queue.scsi_req_baddr = acbvtob(adw, next_acb);
219 next_acb->queue.scsi_req_bo = acbvtobo(adw, next_acb);
220 next_acb->queue.sense_baddr =
221 acbvtob(adw, next_acb) + offsetof(struct acb, sense_data);
222 next_acb->sg_blocks = blocks;
223 next_acb->sg_busaddr = busaddr;
224 next_acb->state = ACB_FREE;
225 SLIST_INSERT_HEAD(&adw->free_acb_list, next_acb, links);
226 blocks += ADW_SG_BLOCKCNT;
227 busaddr += ADW_SG_BLOCKCNT * sizeof(*blocks);
228 next_acb++;
229 adw->num_acbs++;
230 }
231 return (i);
232 }
233
234 static void
235 adwexecuteacb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
236 {
237 struct acb *acb;
238 union ccb *ccb;
239 struct adw_softc *adw;
240 int s;
241
242 acb = (struct acb *)arg;
243 ccb = acb->ccb;
244 adw = (struct adw_softc *)ccb->ccb_h.ccb_adw_ptr;
245
246 if (error != 0) {
247 if (error != EFBIG)
248 printf("%s: Unexepected error 0x%x returned from "
249 "bus_dmamap_load\n", adw_name(adw), error);
250 if (ccb->ccb_h.status == CAM_REQ_INPROG) {
251 xpt_freeze_devq(ccb->ccb_h.path, /*count*/1);
252 ccb->ccb_h.status = CAM_REQ_TOO_BIG|CAM_DEV_QFRZN;
253 }
254 adwfreeacb(adw, acb);
255 xpt_done(ccb);
256 return;
257 }
258
259 if (nseg != 0) {
260 bus_dmasync_op_t op;
261
262 acb->queue.data_addr = dm_segs[0].ds_addr;
263 acb->queue.data_cnt = ccb->csio.dxfer_len;
264 if (nseg > 1) {
265 struct adw_sg_block *sg_block;
266 struct adw_sg_elm *sg;
267 bus_addr_t sg_busaddr;
268 u_int sg_index;
269 bus_dma_segment_t *end_seg;
270
271 end_seg = dm_segs + nseg;
272
273 sg_busaddr = acb->sg_busaddr;
274 sg_index = 0;
275 /* Copy the segments into our SG list */
276 for (sg_block = acb->sg_blocks;; sg_block++) {
277 u_int i;
278
279 sg = sg_block->sg_list;
280 for (i = 0; i < ADW_NO_OF_SG_PER_BLOCK; i++) {
281 if (dm_segs >= end_seg)
282 break;
283
284 sg->sg_addr = dm_segs->ds_addr;
285 sg->sg_count = dm_segs->ds_len;
286 sg++;
287 dm_segs++;
288 }
289 sg_block->sg_cnt = i;
290 sg_index += i;
291 if (dm_segs == end_seg) {
292 sg_block->sg_busaddr_next = 0;
293 break;
294 } else {
295 sg_busaddr +=
296 sizeof(struct adw_sg_block);
297 sg_block->sg_busaddr_next = sg_busaddr;
298 }
299 }
300 acb->queue.sg_real_addr = acb->sg_busaddr;
301 } else {
302 acb->queue.sg_real_addr = 0;
303 }
304
305 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)
306 op = BUS_DMASYNC_PREREAD;
307 else
308 op = BUS_DMASYNC_PREWRITE;
309
310 bus_dmamap_sync(adw->buffer_dmat, acb->dmamap, op);
311
312 } else {
313 acb->queue.data_addr = 0;
314 acb->queue.data_cnt = 0;
315 acb->queue.sg_real_addr = 0;
316 }
317
318 s = splcam();
319
320 /*
321 * Last time we need to check if this CCB needs to
322 * be aborted.
323 */
324 if (ccb->ccb_h.status != CAM_REQ_INPROG) {
325 if (nseg != 0)
326 bus_dmamap_unload(adw->buffer_dmat, acb->dmamap);
327 adwfreeacb(adw, acb);
328 xpt_done(ccb);
329 splx(s);
330 return;
331 }
332
333 acb->state |= ACB_ACTIVE;
334 ccb->ccb_h.status |= CAM_SIM_QUEUED;
335 LIST_INSERT_HEAD(&adw->pending_ccbs, &ccb->ccb_h, sim_links.le);
336 ccb->ccb_h.timeout_ch =
337 timeout(adwtimeout, (caddr_t)acb,
338 (ccb->ccb_h.timeout * hz) / 1000);
339
340 adw_send_acb(adw, acb, acbvtob(adw, acb));
341
342 splx(s);
343 }
344
345 static void
346 adw_action(struct cam_sim *sim, union ccb *ccb)
347 {
348 struct adw_softc *adw;
349
350 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("adw_action\n"));
351
352 adw = (struct adw_softc *)cam_sim_softc(sim);
353
354 switch (ccb->ccb_h.func_code) {
355 /* Common cases first */
356 case XPT_SCSI_IO: /* Execute the requested I/O operation */
357 {
358 struct ccb_scsiio *csio;
359 struct ccb_hdr *ccbh;
360 struct acb *acb;
361
362 csio = &ccb->csio;
363 ccbh = &ccb->ccb_h;
364
365 /* Max supported CDB length is 12 bytes */
366 if (csio->cdb_len > 12) {
367 ccb->ccb_h.status = CAM_REQ_INVALID;
368 xpt_done(ccb);
369 return;
370 }
371
372 if ((acb = adwgetacb(adw)) == NULL) {
373 int s;
374
375 s = splcam();
376 adw->state |= ADW_RESOURCE_SHORTAGE;
377 splx(s);
378 xpt_freeze_simq(sim, /*count*/1);
379 ccb->ccb_h.status = CAM_REQUEUE_REQ;
380 xpt_done(ccb);
381 return;
382 }
383
384 /* Link acb and ccb so we can find one from the other */
385 acb->ccb = ccb;
386 ccb->ccb_h.ccb_acb_ptr = acb;
387 ccb->ccb_h.ccb_adw_ptr = adw;
388
389 acb->queue.cntl = 0;
390 acb->queue.target_cmd = 0;
391 acb->queue.target_id = ccb->ccb_h.target_id;
392 acb->queue.target_lun = ccb->ccb_h.target_lun;
393
394 acb->queue.mflag = 0;
395 acb->queue.sense_len =
396 MIN(csio->sense_len, sizeof(acb->sense_data));
397 acb->queue.cdb_len = csio->cdb_len;
398 if ((ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) != 0) {
399 switch (csio->tag_action) {
400 case MSG_SIMPLE_Q_TAG:
401 acb->queue.scsi_cntl = ADW_QSC_SIMPLE_Q_TAG;
402 break;
403 case MSG_HEAD_OF_Q_TAG:
404 acb->queue.scsi_cntl = ADW_QSC_HEAD_OF_Q_TAG;
405 break;
406 case MSG_ORDERED_Q_TAG:
407 acb->queue.scsi_cntl = ADW_QSC_ORDERED_Q_TAG;
408 break;
409 default:
410 acb->queue.scsi_cntl = ADW_QSC_NO_TAGMSG;
411 break;
412 }
413 } else
414 acb->queue.scsi_cntl = ADW_QSC_NO_TAGMSG;
415
416 if ((ccb->ccb_h.flags & CAM_DIS_DISCONNECT) != 0)
417 acb->queue.scsi_cntl |= ADW_QSC_NO_DISC;
418
419 acb->queue.done_status = 0;
420 acb->queue.scsi_status = 0;
421 acb->queue.host_status = 0;
422 acb->queue.sg_wk_ix = 0;
423 if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0) {
424 if ((ccb->ccb_h.flags & CAM_CDB_PHYS) == 0) {
425 bcopy(csio->cdb_io.cdb_ptr,
426 acb->queue.cdb, csio->cdb_len);
427 } else {
428 /* I guess I could map it in... */
429 ccb->ccb_h.status = CAM_REQ_INVALID;
430 adwfreeacb(adw, acb);
431 xpt_done(ccb);
432 return;
433 }
434 } else {
435 bcopy(csio->cdb_io.cdb_bytes,
436 acb->queue.cdb, csio->cdb_len);
437 }
438
439 /*
440 * If we have any data to send with this command,
441 * map it into bus space.
442 */
443 if ((ccbh->flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
444 if ((ccbh->flags & CAM_SCATTER_VALID) == 0) {
445 /*
446 * We've been given a pointer
447 * to a single buffer.
448 */
449 if ((ccbh->flags & CAM_DATA_PHYS) == 0) {
450 int s;
451 int error;
452
453 s = splsoftvm();
454 error =
455 bus_dmamap_load(adw->buffer_dmat,
456 acb->dmamap,
457 csio->data_ptr,
458 csio->dxfer_len,
459 adwexecuteacb,
460 acb, /*flags*/0);
461 if (error == EINPROGRESS) {
462 /*
463 * So as to maintain ordering,
464 * freeze the controller queue
465 * until our mapping is
466 * returned.
467 */
468 xpt_freeze_simq(sim, 1);
469 acb->state |= CAM_RELEASE_SIMQ;
470 }
471 splx(s);
472 } else {
473 struct bus_dma_segment seg;
474
475 /* Pointer to physical buffer */
476 seg.ds_addr =
477 (bus_addr_t)csio->data_ptr;
478 seg.ds_len = csio->dxfer_len;
479 adwexecuteacb(acb, &seg, 1, 0);
480 }
481 } else {
482 struct bus_dma_segment *segs;
483
484 if ((ccbh->flags & CAM_DATA_PHYS) != 0)
485 panic("adw_action - Physical "
486 "segment pointers "
487 "unsupported");
488
489 if ((ccbh->flags&CAM_SG_LIST_PHYS)==0)
490 panic("adw_action - Virtual "
491 "segment addresses "
492 "unsupported");
493
494 /* Just use the segments provided */
495 segs = (struct bus_dma_segment *)csio->data_ptr;
496 adwexecuteacb(acb, segs, csio->sglist_cnt,
497 (csio->sglist_cnt < ADW_SGSIZE)
498 ? 0 : EFBIG);
499 }
500 } else {
501 adwexecuteacb(acb, NULL, 0, 0);
502 }
503 break;
504 }
505 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
506 {
507 adw_idle_cmd_status_t status;
508
509 status = adw_idle_cmd_send(adw, ADW_IDLE_CMD_DEVICE_RESET,
510 ccb->ccb_h.target_id);
511 if (status == ADW_IDLE_CMD_SUCCESS) {
512 ccb->ccb_h.status = CAM_REQ_CMP;
513 if (bootverbose) {
514 xpt_print_path(ccb->ccb_h.path);
515 printf("BDR Delivered\n");
516 }
517 } else
518 ccb->ccb_h.status = CAM_REQ_CMP_ERR;
519 xpt_done(ccb);
520 break;
521 }
522 case XPT_ABORT: /* Abort the specified CCB */
523 /* XXX Implement */
524 ccb->ccb_h.status = CAM_REQ_INVALID;
525 xpt_done(ccb);
526 break;
527 case XPT_SET_TRAN_SETTINGS:
528 {
529 struct ccb_trans_settings *cts;
530 u_int target_mask;
531 int s;
532
533 cts = &ccb->cts;
534 target_mask = 0x01 << ccb->ccb_h.target_id;
535
536 s = splcam();
537 if ((cts->flags & CCB_TRANS_CURRENT_SETTINGS) != 0) {
538 u_int sdtrdone;
539
540 sdtrdone = adw_lram_read_16(adw, ADW_MC_SDTR_DONE);
541 if ((cts->valid & CCB_TRANS_DISC_VALID) != 0) {
542 u_int discenb;
543
544 discenb =
545 adw_lram_read_16(adw, ADW_MC_DISC_ENABLE);
546
547 if ((cts->flags & CCB_TRANS_DISC_ENB) != 0)
548 discenb |= target_mask;
549 else
550 discenb &= ~target_mask;
551
552 adw_lram_write_16(adw, ADW_MC_DISC_ENABLE,
553 discenb);
554 }
555
556 if ((cts->valid & CCB_TRANS_TQ_VALID) != 0) {
557
558 if ((cts->flags & CCB_TRANS_TAG_ENB) != 0)
559 adw->tagenb |= target_mask;
560 else
561 adw->tagenb &= ~target_mask;
562 }
563
564 if ((cts->valid & CCB_TRANS_BUS_WIDTH_VALID) != 0) {
565 u_int wdtrenb_orig;
566 u_int wdtrenb;
567 u_int wdtrdone;
568
569 wdtrenb_orig =
570 adw_lram_read_16(adw, ADW_MC_WDTR_ABLE);
571 wdtrenb = wdtrenb_orig;
572 wdtrdone = adw_lram_read_16(adw,
573 ADW_MC_WDTR_DONE);
574 switch (cts->bus_width) {
575 case MSG_EXT_WDTR_BUS_32_BIT:
576 case MSG_EXT_WDTR_BUS_16_BIT:
577 wdtrenb |= target_mask;
578 break;
579 case MSG_EXT_WDTR_BUS_8_BIT:
580 default:
581 wdtrenb &= ~target_mask;
582 break;
583 }
584 if (wdtrenb != wdtrenb_orig) {
585 adw_lram_write_16(adw,
586 ADW_MC_WDTR_ABLE,
587 wdtrenb);
588 wdtrdone &= ~target_mask;
589 adw_lram_write_16(adw,
590 ADW_MC_WDTR_DONE,
591 wdtrdone);
592 /* Wide negotiation forces async */
593 sdtrdone &= ~target_mask;
594 adw_lram_write_16(adw,
595 ADW_MC_SDTR_DONE,
596 sdtrdone);
597 }
598 }
599
600 if (((cts->valid & CCB_TRANS_SYNC_RATE_VALID) != 0)
601 || ((cts->valid & CCB_TRANS_SYNC_OFFSET_VALID) != 0)) {
602 u_int sdtr_orig;
603 u_int sdtr;
604 u_int sdtrable_orig;
605 u_int sdtrable;
606
607 sdtr = adw_get_chip_sdtr(adw,
608 ccb->ccb_h.target_id);
609 sdtr_orig = sdtr;
610 sdtrable = adw_lram_read_16(adw,
611 ADW_MC_SDTR_ABLE);
612 sdtrable_orig = sdtrable;
613
614 if ((cts->valid
615 & CCB_TRANS_SYNC_RATE_VALID) != 0) {
616
617 sdtr =
618 adw_find_sdtr(adw,
619 cts->sync_period);
620 }
621
622 if ((cts->valid
623 & CCB_TRANS_SYNC_OFFSET_VALID) != 0) {
624 if (cts->sync_offset == 0)
625 sdtr = ADW_MC_SDTR_ASYNC;
626 }
627
628 if (sdtr == ADW_MC_SDTR_ASYNC)
629 sdtrable &= ~target_mask;
630 else
631 sdtrable |= target_mask;
632 if (sdtr != sdtr_orig
633 || sdtrable != sdtrable_orig) {
634 adw_set_chip_sdtr(adw,
635 ccb->ccb_h.target_id,
636 sdtr);
637 sdtrdone &= ~target_mask;
638 adw_lram_write_16(adw, ADW_MC_SDTR_ABLE,
639 sdtrable);
640 adw_lram_write_16(adw, ADW_MC_SDTR_DONE,
641 sdtrdone);
642
643 }
644 }
645 }
646 splx(s);
647 ccb->ccb_h.status = CAM_REQ_CMP;
648 xpt_done(ccb);
649 break;
650 }
651 case XPT_GET_TRAN_SETTINGS:
652 /* Get default/user set transfer settings for the target */
653 {
654 struct ccb_trans_settings *cts;
655 u_int target_mask;
656
657 cts = &ccb->cts;
658 target_mask = 0x01 << ccb->ccb_h.target_id;
659 if ((cts->flags & CCB_TRANS_USER_SETTINGS) != 0) {
660 u_int mc_sdtr;
661
662 cts->flags = 0;
663 if ((adw->user_discenb & target_mask) != 0)
664 cts->flags |= CCB_TRANS_DISC_ENB;
665
666 if ((adw->user_tagenb & target_mask) != 0)
667 cts->flags |= CCB_TRANS_TAG_ENB;
668
669 if ((adw->user_wdtr & target_mask) != 0)
670 cts->bus_width = MSG_EXT_WDTR_BUS_16_BIT;
671 else
672 cts->bus_width = MSG_EXT_WDTR_BUS_8_BIT;
673
674 mc_sdtr = adw_get_user_sdtr(adw, ccb->ccb_h.target_id);
675 cts->sync_period = adw_find_period(adw, mc_sdtr);
676 if (cts->sync_period != 0)
677 cts->sync_offset = 15; /* XXX ??? */
678 else
679 cts->sync_offset = 0;
680
681 cts->valid = CCB_TRANS_SYNC_RATE_VALID
682 | CCB_TRANS_SYNC_OFFSET_VALID
683 | CCB_TRANS_BUS_WIDTH_VALID
684 | CCB_TRANS_DISC_VALID
685 | CCB_TRANS_TQ_VALID;
686 ccb->ccb_h.status = CAM_REQ_CMP;
687 } else {
688 u_int targ_tinfo;
689
690 cts->flags = 0;
691 if ((adw_lram_read_16(adw, ADW_MC_DISC_ENABLE)
692 & target_mask) != 0)
693 cts->flags |= CCB_TRANS_DISC_ENB;
694
695 if ((adw->tagenb & target_mask) != 0)
696 cts->flags |= CCB_TRANS_TAG_ENB;
697
698 targ_tinfo =
699 adw_lram_read_16(adw,
700 ADW_MC_DEVICE_HSHK_CFG_TABLE
701 + (2 * ccb->ccb_h.target_id));
702
703 if ((targ_tinfo & ADW_HSHK_CFG_WIDE_XFR) != 0)
704 cts->bus_width = MSG_EXT_WDTR_BUS_16_BIT;
705 else
706 cts->bus_width = MSG_EXT_WDTR_BUS_8_BIT;
707
708 cts->sync_period =
709 adw_hshk_cfg_period_factor(targ_tinfo);
710
711 cts->sync_offset = targ_tinfo & ADW_HSHK_CFG_OFFSET;
712 if (cts->sync_period == 0)
713 cts->sync_offset = 0;
714
715 if (cts->sync_offset == 0)
716 cts->sync_period = 0;
717 }
718 cts->valid = CCB_TRANS_SYNC_RATE_VALID
719 | CCB_TRANS_SYNC_OFFSET_VALID
720 | CCB_TRANS_BUS_WIDTH_VALID
721 | CCB_TRANS_DISC_VALID
722 | CCB_TRANS_TQ_VALID;
723 ccb->ccb_h.status = CAM_REQ_CMP;
724 xpt_done(ccb);
725 break;
726 }
727 case XPT_CALC_GEOMETRY:
728 {
729 /*
730 * XXX Use Adaptec translation until I find out how to
731 * get this information from the card.
732 */
733 cam_calc_geometry(&ccb->ccg, /*extended*/1);
734 xpt_done(ccb);
735 break;
736 }
737 case XPT_RESET_BUS: /* Reset the specified SCSI bus */
738 {
739 int failure;
740
741 failure = adw_reset_bus(adw);
742 if (failure != 0) {
743 ccb->ccb_h.status = CAM_REQ_CMP_ERR;
744 } else {
745 if (bootverbose) {
746 xpt_print_path(adw->path);
747 printf("Bus Reset Delivered\n");
748 }
749 ccb->ccb_h.status = CAM_REQ_CMP;
750 }
751 xpt_done(ccb);
752 break;
753 }
754 case XPT_TERM_IO: /* Terminate the I/O process */
755 /* XXX Implement */
756 ccb->ccb_h.status = CAM_REQ_INVALID;
757 xpt_done(ccb);
758 break;
759 case XPT_PATH_INQ: /* Path routing inquiry */
760 {
761 struct ccb_pathinq *cpi = &ccb->cpi;
762
763 cpi->version_num = 1;
764 cpi->hba_inquiry = PI_WIDE_16|PI_SDTR_ABLE|PI_TAG_ABLE;
765 cpi->target_sprt = 0;
766 cpi->hba_misc = 0;
767 cpi->hba_eng_cnt = 0;
768 cpi->max_target = ADW_MAX_TID;
769 cpi->max_lun = ADW_MAX_LUN;
770 cpi->initiator_id = adw->initiator_id;
771 cpi->bus_id = cam_sim_bus(sim);
772 cpi->base_transfer_speed = 3300;
773 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
774 strncpy(cpi->hba_vid, "AdvanSys", HBA_IDLEN);
775 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
776 cpi->unit_number = cam_sim_unit(sim);
777 cpi->ccb_h.status = CAM_REQ_CMP;
778 xpt_done(ccb);
779 break;
780 }
781 default:
782 ccb->ccb_h.status = CAM_REQ_INVALID;
783 xpt_done(ccb);
784 break;
785 }
786 }
787
788 static void
789 adw_poll(struct cam_sim *sim)
790 {
791 adw_intr(cam_sim_softc(sim));
792 }
793
794 static void
795 adw_async(void *callback_arg, u_int32_t code, struct cam_path *path, void *arg)
796 {
797 }
798
799 struct adw_softc *
800 adw_alloc(device_t dev, struct resource *regs, int regs_type, int regs_id)
801 {
802 struct adw_softc *adw;
803 int i;
804
805 /*
806 * Allocate a storage area for us
807 */
808 adw = malloc(sizeof(struct adw_softc), M_DEVBUF, M_NOWAIT | M_ZERO);
809 if (adw == NULL) {
810 printf("adw%d: cannot malloc!\n", device_get_unit(dev));
811 return NULL;
812 }
813 LIST_INIT(&adw->pending_ccbs);
814 SLIST_INIT(&adw->sg_maps);
815 adw->device = dev;
816 adw->unit = device_get_unit(dev);
817 adw->regs_res_type = regs_type;
818 adw->regs_res_id = regs_id;
819 adw->regs = regs;
820 adw->tag = rman_get_bustag(regs);
821 adw->bsh = rman_get_bushandle(regs);
822 i = adw->unit / 10;
823 adw->name = malloc(sizeof("adw") + i + 1, M_DEVBUF, M_NOWAIT);
824 if (adw->name == NULL) {
825 printf("adw%d: cannot malloc name!\n", adw->unit);
826 free(adw, M_DEVBUF);
827 return NULL;
828 }
829 sprintf(adw->name, "adw%d", adw->unit);
830 return(adw);
831 }
832
833 void
834 adw_free(struct adw_softc *adw)
835 {
836 switch (adw->init_level) {
837 case 9:
838 {
839 struct sg_map_node *sg_map;
840
841 while ((sg_map = SLIST_FIRST(&adw->sg_maps)) != NULL) {
842 SLIST_REMOVE_HEAD(&adw->sg_maps, links);
843 bus_dmamap_unload(adw->sg_dmat,
844 sg_map->sg_dmamap);
845 bus_dmamem_free(adw->sg_dmat, sg_map->sg_vaddr,
846 sg_map->sg_dmamap);
847 free(sg_map, M_DEVBUF);
848 }
849 bus_dma_tag_destroy(adw->sg_dmat);
850 }
851 case 8:
852 bus_dmamap_unload(adw->acb_dmat, adw->acb_dmamap);
853 case 7:
854 bus_dmamem_free(adw->acb_dmat, adw->acbs,
855 adw->acb_dmamap);
856 bus_dmamap_destroy(adw->acb_dmat, adw->acb_dmamap);
857 case 6:
858 bus_dma_tag_destroy(adw->acb_dmat);
859 case 5:
860 bus_dmamap_unload(adw->carrier_dmat, adw->carrier_dmamap);
861 case 4:
862 bus_dmamem_free(adw->carrier_dmat, adw->carriers,
863 adw->carrier_dmamap);
864 bus_dmamap_destroy(adw->carrier_dmat, adw->carrier_dmamap);
865 case 3:
866 bus_dma_tag_destroy(adw->carrier_dmat);
867 case 2:
868 bus_dma_tag_destroy(adw->buffer_dmat);
869 case 1:
870 bus_dma_tag_destroy(adw->parent_dmat);
871 case 0:
872 break;
873 }
874
875 if (adw->regs != NULL)
876 bus_release_resource(adw->device,
877 adw->regs_res_type,
878 adw->regs_res_id,
879 adw->regs);
880
881 if (adw->irq != NULL)
882 bus_release_resource(adw->device,
883 adw->irq_res_type,
884 0, adw->irq);
885
886 if (adw->sim != NULL) {
887 if (adw->path != NULL) {
888 xpt_async(AC_LOST_DEVICE, adw->path, NULL);
889 xpt_free_path(adw->path);
890 }
891 xpt_bus_deregister(cam_sim_path(adw->sim));
892 cam_sim_free(adw->sim, /*free_devq*/TRUE);
893 }
894 free(adw->name, M_DEVBUF);
895 free(adw, M_DEVBUF);
896 }
897
898 int
899 adw_init(struct adw_softc *adw)
900 {
901 struct adw_eeprom eep_config;
902 u_int tid;
903 u_int i;
904 u_int16_t checksum;
905 u_int16_t scsicfg1;
906
907 checksum = adw_eeprom_read(adw, &eep_config);
908 bcopy(eep_config.serial_number, adw->serial_number,
909 sizeof(adw->serial_number));
910 if (checksum != eep_config.checksum) {
911 u_int16_t serial_number[3];
912
913 adw->flags |= ADW_EEPROM_FAILED;
914 printf("%s: EEPROM checksum failed. Restoring Defaults\n",
915 adw_name(adw));
916
917 /*
918 * Restore the default EEPROM settings.
919 * Assume the 6 byte board serial number that was read
920 * from EEPROM is correct even if the EEPROM checksum
921 * failed.
922 */
923 bcopy(adw->default_eeprom, &eep_config, sizeof(eep_config));
924 bcopy(adw->serial_number, eep_config.serial_number,
925 sizeof(serial_number));
926 adw_eeprom_write(adw, &eep_config);
927 }
928
929 /* Pull eeprom information into our softc. */
930 adw->bios_ctrl = eep_config.bios_ctrl;
931 adw->user_wdtr = eep_config.wdtr_able;
932 for (tid = 0; tid < ADW_MAX_TID; tid++) {
933 u_int mc_sdtr;
934 u_int16_t tid_mask;
935
936 tid_mask = 0x1 << tid;
937 if ((adw->features & ADW_ULTRA) != 0) {
938 /*
939 * Ultra chips store sdtr and ultraenb
940 * bits in their seeprom, so we must
941 * construct valid mc_sdtr entries for
942 * indirectly.
943 */
944 if (eep_config.sync1.sync_enable & tid_mask) {
945 if (eep_config.sync2.ultra_enable & tid_mask)
946 mc_sdtr = ADW_MC_SDTR_20;
947 else
948 mc_sdtr = ADW_MC_SDTR_10;
949 } else
950 mc_sdtr = ADW_MC_SDTR_ASYNC;
951 } else {
952 switch (ADW_TARGET_GROUP(tid)) {
953 case 3:
954 mc_sdtr = eep_config.sync4.sdtr4;
955 break;
956 case 2:
957 mc_sdtr = eep_config.sync3.sdtr3;
958 break;
959 case 1:
960 mc_sdtr = eep_config.sync2.sdtr2;
961 break;
962 default: /* Shut up compiler */
963 case 0:
964 mc_sdtr = eep_config.sync1.sdtr1;
965 break;
966 }
967 mc_sdtr >>= ADW_TARGET_GROUP_SHIFT(tid);
968 mc_sdtr &= 0xFF;
969 }
970 adw_set_user_sdtr(adw, tid, mc_sdtr);
971 }
972 adw->user_tagenb = eep_config.tagqng_able;
973 adw->user_discenb = eep_config.disc_enable;
974 adw->max_acbs = eep_config.max_host_qng;
975 adw->initiator_id = (eep_config.adapter_scsi_id & ADW_MAX_TID);
976
977 /*
978 * Sanity check the number of host openings.
979 */
980 if (adw->max_acbs > ADW_DEF_MAX_HOST_QNG)
981 adw->max_acbs = ADW_DEF_MAX_HOST_QNG;
982 else if (adw->max_acbs < ADW_DEF_MIN_HOST_QNG) {
983 /* If the value is zero, assume it is uninitialized. */
984 if (adw->max_acbs == 0)
985 adw->max_acbs = ADW_DEF_MAX_HOST_QNG;
986 else
987 adw->max_acbs = ADW_DEF_MIN_HOST_QNG;
988 }
989
990 scsicfg1 = 0;
991 if ((adw->features & ADW_ULTRA2) != 0) {
992 switch (eep_config.termination_lvd) {
993 default:
994 printf("%s: Invalid EEPROM LVD Termination Settings.\n",
995 adw_name(adw));
996 printf("%s: Reverting to Automatic LVD Termination\n",
997 adw_name(adw));
998 /* FALLTHROUGH */
999 case ADW_EEPROM_TERM_AUTO:
1000 break;
1001 case ADW_EEPROM_TERM_BOTH_ON:
1002 scsicfg1 |= ADW2_SCSI_CFG1_TERM_LVD_LO;
1003 /* FALLTHROUGH */
1004 case ADW_EEPROM_TERM_HIGH_ON:
1005 scsicfg1 |= ADW2_SCSI_CFG1_TERM_LVD_HI;
1006 /* FALLTHROUGH */
1007 case ADW_EEPROM_TERM_OFF:
1008 scsicfg1 |= ADW2_SCSI_CFG1_DIS_TERM_DRV;
1009 break;
1010 }
1011 }
1012
1013 switch (eep_config.termination_se) {
1014 default:
1015 printf("%s: Invalid SE EEPROM Termination Settings.\n",
1016 adw_name(adw));
1017 printf("%s: Reverting to Automatic SE Termination\n",
1018 adw_name(adw));
1019 /* FALLTHROUGH */
1020 case ADW_EEPROM_TERM_AUTO:
1021 break;
1022 case ADW_EEPROM_TERM_BOTH_ON:
1023 scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_L;
1024 /* FALLTHROUGH */
1025 case ADW_EEPROM_TERM_HIGH_ON:
1026 scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H;
1027 /* FALLTHROUGH */
1028 case ADW_EEPROM_TERM_OFF:
1029 scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_MANUAL;
1030 break;
1031 }
1032 printf("%s: SCSI ID %d, ", adw_name(adw), adw->initiator_id);
1033
1034 /* DMA tag for mapping buffers into device visible space. */
1035 if (bus_dma_tag_create(
1036 /* parent */ adw->parent_dmat,
1037 /* alignment */ 1,
1038 /* boundary */ 0,
1039 /* lowaddr */ BUS_SPACE_MAXADDR_32BIT,
1040 /* highaddr */ BUS_SPACE_MAXADDR,
1041 /* filter */ NULL,
1042 /* filterarg */ NULL,
1043 /* maxsize */ MAXBSIZE,
1044 /* nsegments */ ADW_SGSIZE,
1045 /* maxsegsz */ BUS_SPACE_MAXSIZE_32BIT,
1046 /* flags */ BUS_DMA_ALLOCNOW,
1047 /* lockfunc */ busdma_lock_mutex,
1048 /* lockarg */ &Giant,
1049 &adw->buffer_dmat) != 0) {
1050 return (ENOMEM);
1051 }
1052
1053 adw->init_level++;
1054
1055 /* DMA tag for our ccb carrier structures */
1056 if (bus_dma_tag_create(
1057 /* parent */ adw->parent_dmat,
1058 /* alignment */ 0x10,
1059 /* boundary */ 0,
1060 /* lowaddr */ BUS_SPACE_MAXADDR_32BIT,
1061 /* highaddr */ BUS_SPACE_MAXADDR,
1062 /* filter */ NULL,
1063 /* filterarg */ NULL,
1064 /* maxsize */ (adw->max_acbs +
1065 ADW_NUM_CARRIER_QUEUES + 1) *
1066 sizeof(struct adw_carrier),
1067 /* nsegments */ 1,
1068 /* maxsegsz */ BUS_SPACE_MAXSIZE_32BIT,
1069 /* flags */ 0,
1070 /* lockfunc */ busdma_lock_mutex,
1071 /* lockarg */ &Giant,
1072 &adw->carrier_dmat) != 0) {
1073 return (ENOMEM);
1074 }
1075
1076 adw->init_level++;
1077
1078 /* Allocation for our ccb carrier structures */
1079 if (bus_dmamem_alloc(adw->carrier_dmat, (void **)&adw->carriers,
1080 BUS_DMA_NOWAIT, &adw->carrier_dmamap) != 0) {
1081 return (ENOMEM);
1082 }
1083
1084 adw->init_level++;
1085
1086 /* And permanently map them */
1087 bus_dmamap_load(adw->carrier_dmat, adw->carrier_dmamap,
1088 adw->carriers,
1089 (adw->max_acbs + ADW_NUM_CARRIER_QUEUES + 1)
1090 * sizeof(struct adw_carrier),
1091 adwmapmem, &adw->carrier_busbase, /*flags*/0);
1092
1093 /* Clear them out. */
1094 bzero(adw->carriers, (adw->max_acbs + ADW_NUM_CARRIER_QUEUES + 1)
1095 * sizeof(struct adw_carrier));
1096
1097 /* Setup our free carrier list */
1098 adw->free_carriers = adw->carriers;
1099 for (i = 0; i < adw->max_acbs + ADW_NUM_CARRIER_QUEUES; i++) {
1100 adw->carriers[i].carr_offset =
1101 carriervtobo(adw, &adw->carriers[i]);
1102 adw->carriers[i].carr_ba =
1103 carriervtob(adw, &adw->carriers[i]);
1104 adw->carriers[i].areq_ba = 0;
1105 adw->carriers[i].next_ba =
1106 carriervtobo(adw, &adw->carriers[i+1]);
1107 }
1108 /* Terminal carrier. Never leaves the freelist */
1109 adw->carriers[i].carr_offset =
1110 carriervtobo(adw, &adw->carriers[i]);
1111 adw->carriers[i].carr_ba =
1112 carriervtob(adw, &adw->carriers[i]);
1113 adw->carriers[i].areq_ba = 0;
1114 adw->carriers[i].next_ba = ~0;
1115
1116 adw->init_level++;
1117
1118 /* DMA tag for our acb structures */
1119 if (bus_dma_tag_create(
1120 /* parent */ adw->parent_dmat,
1121 /* alignment */ 1,
1122 /* boundary */ 0,
1123 /* lowaddr */ BUS_SPACE_MAXADDR,
1124 /* highaddr */ BUS_SPACE_MAXADDR,
1125 /* filter */ NULL,
1126 /* filterarg */ NULL,
1127 /* maxsize */ adw->max_acbs * sizeof(struct acb),
1128 /* nsegments */ 1,
1129 /* maxsegsz */ BUS_SPACE_MAXSIZE_32BIT,
1130 /* flags */ 0,
1131 /* lockfunc */ busdma_lock_mutex,
1132 /* lockarg */ &Giant,
1133 &adw->acb_dmat) != 0) {
1134 return (ENOMEM);
1135 }
1136
1137 adw->init_level++;
1138
1139 /* Allocation for our ccbs */
1140 if (bus_dmamem_alloc(adw->acb_dmat, (void **)&adw->acbs,
1141 BUS_DMA_NOWAIT, &adw->acb_dmamap) != 0)
1142 return (ENOMEM);
1143
1144 adw->init_level++;
1145
1146 /* And permanently map them */
1147 bus_dmamap_load(adw->acb_dmat, adw->acb_dmamap,
1148 adw->acbs,
1149 adw->max_acbs * sizeof(struct acb),
1150 adwmapmem, &adw->acb_busbase, /*flags*/0);
1151
1152 /* Clear them out. */
1153 bzero(adw->acbs, adw->max_acbs * sizeof(struct acb));
1154
1155 /* DMA tag for our S/G structures. We allocate in page sized chunks */
1156 if (bus_dma_tag_create(
1157 /* parent */ adw->parent_dmat,
1158 /* alignment */ 1,
1159 /* boundary */ 0,
1160 /* lowaddr */ BUS_SPACE_MAXADDR,
1161 /* highaddr */ BUS_SPACE_MAXADDR,
1162 /* filter */ NULL,
1163 /* filterarg */ NULL,
1164 /* maxsize */ PAGE_SIZE,
1165 /* nsegments */ 1,
1166 /* maxsegsz */ BUS_SPACE_MAXSIZE_32BIT,
1167 /* flags */ 0,
1168 /* lockfunc */ busdma_lock_mutex,
1169 /* lockarg */ &Giant,
1170 &adw->sg_dmat) != 0) {
1171 return (ENOMEM);
1172 }
1173
1174 adw->init_level++;
1175
1176 /* Allocate our first batch of ccbs */
1177 if (adwallocacbs(adw) == 0)
1178 return (ENOMEM);
1179
1180 if (adw_init_chip(adw, scsicfg1) != 0)
1181 return (ENXIO);
1182
1183 printf("Queue Depth %d\n", adw->max_acbs);
1184
1185 return (0);
1186 }
1187
1188 /*
1189 * Attach all the sub-devices we can find
1190 */
1191 int
1192 adw_attach(struct adw_softc *adw)
1193 {
1194 struct ccb_setasync csa;
1195 struct cam_devq *devq;
1196 int s;
1197 int error;
1198
1199 error = 0;
1200 s = splcam();
1201 /* Hook up our interrupt handler */
1202 if ((error = bus_setup_intr(adw->device, adw->irq,
1203 INTR_TYPE_CAM | INTR_ENTROPY, adw_intr,
1204 adw, &adw->ih)) != 0) {
1205 device_printf(adw->device, "bus_setup_intr() failed: %d\n",
1206 error);
1207 goto fail;
1208 }
1209
1210 /* Start the Risc processor now that we are fully configured. */
1211 adw_outw(adw, ADW_RISC_CSR, ADW_RISC_CSR_RUN);
1212
1213 /*
1214 * Create the device queue for our SIM.
1215 */
1216 devq = cam_simq_alloc(adw->max_acbs);
1217 if (devq == NULL)
1218 return (ENOMEM);
1219
1220 /*
1221 * Construct our SIM entry.
1222 */
1223 adw->sim = cam_sim_alloc(adw_action, adw_poll, "adw", adw, adw->unit,
1224 1, adw->max_acbs, devq);
1225 if (adw->sim == NULL) {
1226 error = ENOMEM;
1227 goto fail;
1228 }
1229
1230 /*
1231 * Register the bus.
1232 */
1233 if (xpt_bus_register(adw->sim, 0) != CAM_SUCCESS) {
1234 cam_sim_free(adw->sim, /*free devq*/TRUE);
1235 error = ENOMEM;
1236 goto fail;
1237 }
1238
1239 if (xpt_create_path(&adw->path, /*periph*/NULL, cam_sim_path(adw->sim),
1240 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD)
1241 == CAM_REQ_CMP) {
1242 xpt_setup_ccb(&csa.ccb_h, adw->path, /*priority*/5);
1243 csa.ccb_h.func_code = XPT_SASYNC_CB;
1244 csa.event_enable = AC_LOST_DEVICE;
1245 csa.callback = adw_async;
1246 csa.callback_arg = adw;
1247 xpt_action((union ccb *)&csa);
1248 }
1249
1250 fail:
1251 splx(s);
1252 return (error);
1253 }
1254
1255 void
1256 adw_intr(void *arg)
1257 {
1258 struct adw_softc *adw;
1259 u_int int_stat;
1260
1261 adw = (struct adw_softc *)arg;
1262 if ((adw_inw(adw, ADW_CTRL_REG) & ADW_CTRL_REG_HOST_INTR) == 0)
1263 return;
1264
1265 /* Reading the register clears the interrupt. */
1266 int_stat = adw_inb(adw, ADW_INTR_STATUS_REG);
1267
1268 if ((int_stat & ADW_INTR_STATUS_INTRB) != 0) {
1269 u_int intrb_code;
1270
1271 /* Async Microcode Event */
1272 intrb_code = adw_lram_read_8(adw, ADW_MC_INTRB_CODE);
1273 switch (intrb_code) {
1274 case ADW_ASYNC_CARRIER_READY_FAILURE:
1275 /*
1276 * The RISC missed our update of
1277 * the commandq.
1278 */
1279 if (LIST_FIRST(&adw->pending_ccbs) != NULL)
1280 adw_tickle_risc(adw, ADW_TICKLE_A);
1281 break;
1282 case ADW_ASYNC_SCSI_BUS_RESET_DET:
1283 /*
1284 * The firmware detected a SCSI Bus reset.
1285 */
1286 printf("Someone Reset the Bus\n");
1287 adw_handle_bus_reset(adw, /*initiated*/FALSE);
1288 break;
1289 case ADW_ASYNC_RDMA_FAILURE:
1290 /*
1291 * Handle RDMA failure by resetting the
1292 * SCSI Bus and chip.
1293 */
1294 #if XXX
1295 AdvResetChipAndSB(adv_dvc_varp);
1296 #endif
1297 break;
1298
1299 case ADW_ASYNC_HOST_SCSI_BUS_RESET:
1300 /*
1301 * Host generated SCSI bus reset occurred.
1302 */
1303 adw_handle_bus_reset(adw, /*initiated*/TRUE);
1304 break;
1305 default:
1306 printf("adw_intr: unknown async code 0x%x\n",
1307 intrb_code);
1308 break;
1309 }
1310 }
1311
1312 /*
1313 * Run down the RequestQ.
1314 */
1315 while ((adw->responseq->next_ba & ADW_RQ_DONE) != 0) {
1316 struct adw_carrier *free_carrier;
1317 struct acb *acb;
1318 union ccb *ccb;
1319
1320 #if 0
1321 printf("0x%x, 0x%x, 0x%x, 0x%x\n",
1322 adw->responseq->carr_offset,
1323 adw->responseq->carr_ba,
1324 adw->responseq->areq_ba,
1325 adw->responseq->next_ba);
1326 #endif
1327 /*
1328 * The firmware copies the adw_scsi_req_q.acb_baddr
1329 * field into the areq_ba field of the carrier.
1330 */
1331 acb = acbbotov(adw, adw->responseq->areq_ba);
1332
1333 /*
1334 * The least significant four bits of the next_ba
1335 * field are used as flags. Mask them out and then
1336 * advance through the list.
1337 */
1338 free_carrier = adw->responseq;
1339 adw->responseq =
1340 carrierbotov(adw, free_carrier->next_ba & ADW_NEXT_BA_MASK);
1341 free_carrier->next_ba = adw->free_carriers->carr_offset;
1342 adw->free_carriers = free_carrier;
1343
1344 /* Process CCB */
1345 ccb = acb->ccb;
1346 untimeout(adwtimeout, acb, ccb->ccb_h.timeout_ch);
1347 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1348 bus_dmasync_op_t op;
1349
1350 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)
1351 op = BUS_DMASYNC_POSTREAD;
1352 else
1353 op = BUS_DMASYNC_POSTWRITE;
1354 bus_dmamap_sync(adw->buffer_dmat, acb->dmamap, op);
1355 bus_dmamap_unload(adw->buffer_dmat, acb->dmamap);
1356 ccb->csio.resid = acb->queue.data_cnt;
1357 } else
1358 ccb->csio.resid = 0;
1359
1360 /* Common Cases inline... */
1361 if (acb->queue.host_status == QHSTA_NO_ERROR
1362 && (acb->queue.done_status == QD_NO_ERROR
1363 || acb->queue.done_status == QD_WITH_ERROR)) {
1364 ccb->csio.scsi_status = acb->queue.scsi_status;
1365 ccb->ccb_h.status = 0;
1366 switch (ccb->csio.scsi_status) {
1367 case SCSI_STATUS_OK:
1368 ccb->ccb_h.status |= CAM_REQ_CMP;
1369 break;
1370 case SCSI_STATUS_CHECK_COND:
1371 case SCSI_STATUS_CMD_TERMINATED:
1372 bcopy(&acb->sense_data, &ccb->csio.sense_data,
1373 ccb->csio.sense_len);
1374 ccb->ccb_h.status |= CAM_AUTOSNS_VALID;
1375 ccb->csio.sense_resid = acb->queue.sense_len;
1376 /* FALLTHROUGH */
1377 default:
1378 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR
1379 | CAM_DEV_QFRZN;
1380 xpt_freeze_devq(ccb->ccb_h.path, /*count*/1);
1381 break;
1382 }
1383 adwfreeacb(adw, acb);
1384 xpt_done(ccb);
1385 } else {
1386 adwprocesserror(adw, acb);
1387 }
1388 }
1389 }
1390
1391 static void
1392 adwprocesserror(struct adw_softc *adw, struct acb *acb)
1393 {
1394 union ccb *ccb;
1395
1396 ccb = acb->ccb;
1397 if (acb->queue.done_status == QD_ABORTED_BY_HOST) {
1398 ccb->ccb_h.status = CAM_REQ_ABORTED;
1399 } else {
1400
1401 switch (acb->queue.host_status) {
1402 case QHSTA_M_SEL_TIMEOUT:
1403 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
1404 break;
1405 case QHSTA_M_SXFR_OFF_UFLW:
1406 case QHSTA_M_SXFR_OFF_OFLW:
1407 case QHSTA_M_DATA_OVER_RUN:
1408 ccb->ccb_h.status = CAM_DATA_RUN_ERR;
1409 break;
1410 case QHSTA_M_SXFR_DESELECTED:
1411 case QHSTA_M_UNEXPECTED_BUS_FREE:
1412 ccb->ccb_h.status = CAM_UNEXP_BUSFREE;
1413 break;
1414 case QHSTA_M_SCSI_BUS_RESET:
1415 case QHSTA_M_SCSI_BUS_RESET_UNSOL:
1416 ccb->ccb_h.status = CAM_SCSI_BUS_RESET;
1417 break;
1418 case QHSTA_M_BUS_DEVICE_RESET:
1419 ccb->ccb_h.status = CAM_BDR_SENT;
1420 break;
1421 case QHSTA_M_QUEUE_ABORTED:
1422 /* BDR or Bus Reset */
1423 printf("Saw Queue Aborted\n");
1424 ccb->ccb_h.status = adw->last_reset;
1425 break;
1426 case QHSTA_M_SXFR_SDMA_ERR:
1427 case QHSTA_M_SXFR_SXFR_PERR:
1428 case QHSTA_M_RDMA_PERR:
1429 ccb->ccb_h.status = CAM_UNCOR_PARITY;
1430 break;
1431 case QHSTA_M_WTM_TIMEOUT:
1432 case QHSTA_M_SXFR_WD_TMO:
1433 {
1434 /* The SCSI bus hung in a phase */
1435 xpt_print_path(adw->path);
1436 printf("Watch Dog timer expired. Reseting bus\n");
1437 adw_reset_bus(adw);
1438 break;
1439 }
1440 case QHSTA_M_SXFR_XFR_PH_ERR:
1441 ccb->ccb_h.status = CAM_SEQUENCE_FAIL;
1442 break;
1443 case QHSTA_M_SXFR_UNKNOWN_ERROR:
1444 break;
1445 case QHSTA_M_BAD_CMPL_STATUS_IN:
1446 /* No command complete after a status message */
1447 ccb->ccb_h.status = CAM_SEQUENCE_FAIL;
1448 break;
1449 case QHSTA_M_AUTO_REQ_SENSE_FAIL:
1450 ccb->ccb_h.status = CAM_AUTOSENSE_FAIL;
1451 break;
1452 case QHSTA_M_INVALID_DEVICE:
1453 ccb->ccb_h.status = CAM_PATH_INVALID;
1454 break;
1455 case QHSTA_M_NO_AUTO_REQ_SENSE:
1456 /*
1457 * User didn't request sense, but we got a
1458 * check condition.
1459 */
1460 ccb->csio.scsi_status = acb->queue.scsi_status;
1461 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
1462 break;
1463 default:
1464 panic("%s: Unhandled Host status error %x",
1465 adw_name(adw), acb->queue.host_status);
1466 /* NOTREACHED */
1467 }
1468 }
1469 if ((acb->state & ACB_RECOVERY_ACB) != 0) {
1470 if (ccb->ccb_h.status == CAM_SCSI_BUS_RESET
1471 || ccb->ccb_h.status == CAM_BDR_SENT)
1472 ccb->ccb_h.status = CAM_CMD_TIMEOUT;
1473 }
1474 if (ccb->ccb_h.status != CAM_REQ_CMP) {
1475 xpt_freeze_devq(ccb->ccb_h.path, /*count*/1);
1476 ccb->ccb_h.status |= CAM_DEV_QFRZN;
1477 }
1478 adwfreeacb(adw, acb);
1479 xpt_done(ccb);
1480 }
1481
1482 static void
1483 adwtimeout(void *arg)
1484 {
1485 struct acb *acb;
1486 union ccb *ccb;
1487 struct adw_softc *adw;
1488 adw_idle_cmd_status_t status;
1489 int target_id;
1490 int s;
1491
1492 acb = (struct acb *)arg;
1493 ccb = acb->ccb;
1494 adw = (struct adw_softc *)ccb->ccb_h.ccb_adw_ptr;
1495 xpt_print_path(ccb->ccb_h.path);
1496 printf("ACB %p - timed out\n", (void *)acb);
1497
1498 s = splcam();
1499
1500 if ((acb->state & ACB_ACTIVE) == 0) {
1501 xpt_print_path(ccb->ccb_h.path);
1502 printf("ACB %p - timed out CCB already completed\n",
1503 (void *)acb);
1504 splx(s);
1505 return;
1506 }
1507
1508 acb->state |= ACB_RECOVERY_ACB;
1509 target_id = ccb->ccb_h.target_id;
1510
1511 /* Attempt a BDR first */
1512 status = adw_idle_cmd_send(adw, ADW_IDLE_CMD_DEVICE_RESET,
1513 ccb->ccb_h.target_id);
1514 splx(s);
1515 if (status == ADW_IDLE_CMD_SUCCESS) {
1516 printf("%s: BDR Delivered. No longer in timeout\n",
1517 adw_name(adw));
1518 adw_handle_device_reset(adw, target_id);
1519 } else {
1520 adw_reset_bus(adw);
1521 xpt_print_path(adw->path);
1522 printf("Bus Reset Delivered. No longer in timeout\n");
1523 }
1524 }
1525
1526 static void
1527 adw_handle_device_reset(struct adw_softc *adw, u_int target)
1528 {
1529 struct cam_path *path;
1530 cam_status error;
1531
1532 error = xpt_create_path(&path, /*periph*/NULL, cam_sim_path(adw->sim),
1533 target, CAM_LUN_WILDCARD);
1534
1535 if (error == CAM_REQ_CMP) {
1536 xpt_async(AC_SENT_BDR, path, NULL);
1537 xpt_free_path(path);
1538 }
1539 adw->last_reset = CAM_BDR_SENT;
1540 }
1541
1542 static void
1543 adw_handle_bus_reset(struct adw_softc *adw, int initiated)
1544 {
1545 if (initiated) {
1546 /*
1547 * The microcode currently sets the SCSI Bus Reset signal
1548 * while handling the AscSendIdleCmd() IDLE_CMD_SCSI_RESET
1549 * command above. But the SCSI Bus Reset Hold Time in the
1550 * microcode is not deterministic (it may in fact be for less
1551 * than the SCSI Spec. minimum of 25 us). Therefore on return
1552 * the Adv Library sets the SCSI Bus Reset signal for
1553 * ADW_SCSI_RESET_HOLD_TIME_US, which is defined to be greater
1554 * than 25 us.
1555 */
1556 u_int scsi_ctrl;
1557
1558 scsi_ctrl = adw_inw(adw, ADW_SCSI_CTRL) & ~ADW_SCSI_CTRL_RSTOUT;
1559 adw_outw(adw, ADW_SCSI_CTRL, scsi_ctrl | ADW_SCSI_CTRL_RSTOUT);
1560 DELAY(ADW_SCSI_RESET_HOLD_TIME_US);
1561 adw_outw(adw, ADW_SCSI_CTRL, scsi_ctrl);
1562
1563 /*
1564 * We will perform the async notification when the
1565 * SCSI Reset interrupt occurs.
1566 */
1567 } else
1568 xpt_async(AC_BUS_RESET, adw->path, NULL);
1569 adw->last_reset = CAM_SCSI_BUS_RESET;
1570 }
1571 MODULE_DEPEND(adw, cam, 1, 1, 1);
1572
Cache object: 091d64f2c6578ae7e67abdd44a571693
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