The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/advansys/adwlib.c

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    1 /*-
    2  * Low level routines for Second Generation
    3  * Advanced Systems Inc. SCSI controllers chips
    4  *
    5  * Copyright (c) 1998, 1999, 2000 Justin Gibbs.
    6  * All rights reserved.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions, and the following disclaimer,
   13  *    without modification.
   14  * 2. Redistributions in binary form must reproduce the above copyright
   15  *    notice, this list of conditions and the following disclaimer in the
   16  *    documentation and/or other materials provided with the distribution.
   17  * 3. The name of the author may not be used to endorse or promote products
   18  *    derived from this software without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
   24  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   30  * SUCH DAMAGE.
   31  */
   32 /*-
   33  * Ported from:
   34  * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
   35  *     
   36  * Copyright (c) 1995-1998 Advanced System Products, Inc.
   37  * All Rights Reserved.
   38  *   
   39  * Redistribution and use in source and binary forms, with or without
   40  * modification, are permitted provided that redistributions of source
   41  * code retain the above copyright notice and this comment without
   42  * modification.
   43  */
   44 
   45 #include <sys/cdefs.h>
   46 __FBSDID("$FreeBSD: stable/11/sys/dev/advansys/adwlib.c 331722 2018-03-29 02:50:57Z eadler $");
   47 
   48 #include <sys/param.h>
   49 #include <sys/conf.h>
   50 #include <sys/lock.h>
   51 #include <sys/mutex.h>
   52 #include <sys/systm.h>
   53 #include <sys/bus.h>
   54 #include <sys/rman.h>
   55 
   56 #include <machine/bus.h>
   57 
   58 #include <cam/cam.h>
   59 #include <cam/cam_ccb.h>
   60 #include <cam/cam_sim.h>
   61 #include <cam/cam_xpt_sim.h>
   62 #include <cam/scsi/scsi_all.h>
   63 
   64 #include <dev/advansys/adwlib.h>
   65 
   66 const struct adw_eeprom adw_asc3550_default_eeprom =
   67 {
   68         ADW_EEPROM_BIOS_ENABLE,         /* cfg_lsw */
   69         0x0000,                         /* cfg_msw */
   70         0xFFFF,                         /* disc_enable */
   71         0xFFFF,                         /* wdtr_able */
   72         { 0xFFFF },                     /* sdtr_able */
   73         0xFFFF,                         /* start_motor */
   74         0xFFFF,                         /* tagqng_able */
   75         0xFFFF,                         /* bios_scan */
   76         0,                              /* scam_tolerant */
   77         7,                              /* adapter_scsi_id */
   78         0,                              /* bios_boot_delay */
   79         3,                              /* scsi_reset_delay */
   80         0,                              /* bios_id_lun */
   81         0,                              /* termination */
   82         0,                              /* reserved1 */
   83         0xFFE7,                         /* bios_ctrl */
   84         { 0xFFFF },                     /* ultra_able */   
   85         { 0 },                          /* reserved2 */
   86         ADW_DEF_MAX_HOST_QNG,           /* max_host_qng */
   87         ADW_DEF_MAX_DVC_QNG,            /* max_dvc_qng */
   88         0,                              /* dvc_cntl */
   89         { 0 },                          /* bug_fix */
   90         { 0, 0, 0 },                    /* serial_number */
   91         0,                              /* check_sum */
   92         {                               /* oem_name[16] */
   93           0, 0, 0, 0, 0, 0, 0, 0,
   94           0, 0, 0, 0, 0, 0, 0, 0
   95         },
   96         0,                              /* dvc_err_code */
   97         0,                              /* adv_err_code */
   98         0,                              /* adv_err_addr */
   99         0,                              /* saved_dvc_err_code */
  100         0,                              /* saved_adv_err_code */
  101         0                               /* saved_adv_err_addr */
  102 };
  103 
  104 const struct adw_eeprom adw_asc38C0800_default_eeprom =
  105 {
  106         ADW_EEPROM_BIOS_ENABLE,         /* 00 cfg_lsw */
  107         0x0000,                         /* 01 cfg_msw */
  108         0xFFFF,                         /* 02 disc_enable */
  109         0xFFFF,                         /* 03 wdtr_able */
  110         { 0x4444 },                     /* 04 sdtr_speed1 */
  111         0xFFFF,                         /* 05 start_motor */
  112         0xFFFF,                         /* 06 tagqng_able */
  113         0xFFFF,                         /* 07 bios_scan */
  114         0,                              /* 08 scam_tolerant */
  115         7,                              /* 09 adapter_scsi_id */
  116         0,                              /*    bios_boot_delay */
  117         3,                              /* 10 scsi_reset_delay */
  118         0,                              /*    bios_id_lun */
  119         0,                              /* 11 termination_se */
  120         0,                              /*    termination_lvd */
  121         0xFFE7,                         /* 12 bios_ctrl */
  122         { 0x4444 },                     /* 13 sdtr_speed2 */
  123         { 0x4444 },                     /* 14 sdtr_speed3 */
  124         ADW_DEF_MAX_HOST_QNG,           /* 15 max_host_qng */
  125         ADW_DEF_MAX_DVC_QNG,            /*    max_dvc_qng */
  126         0,                              /* 16 dvc_cntl */
  127         { 0x4444 } ,                    /* 17 sdtr_speed4 */
  128         { 0, 0, 0 },                    /* 18-20 serial_number */
  129         0,                              /* 21 check_sum */
  130         {                               /* 22-29 oem_name[16] */
  131           0, 0, 0, 0, 0, 0, 0, 0,
  132           0, 0, 0, 0, 0, 0, 0, 0
  133         },
  134         0,                              /* 30 dvc_err_code */
  135         0,                              /* 31 adv_err_code */
  136         0,                              /* 32 adv_err_addr */
  137         0,                              /* 33 saved_dvc_err_code */
  138         0,                              /* 34 saved_adv_err_code */
  139         0,                              /* 35 saved_adv_err_addr */
  140         {                               /* 36 - 55 reserved */
  141           0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  142           0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  143         },
  144         0,                              /* 56 cisptr_lsw */
  145         0,                              /* 57 cisprt_msw */
  146                                         /* 58-59 sub-id */
  147         (PCI_ID_ADVANSYS_38C0800_REV1 & PCI_ID_DEV_VENDOR_MASK) >> 32,
  148 };
  149 
  150 #define ADW_MC_SDTR_OFFSET_ULTRA2_DT    0
  151 #define ADW_MC_SDTR_OFFSET_ULTRA2       1
  152 #define ADW_MC_SDTR_OFFSET_ULTRA        2
  153 const struct adw_syncrate adw_syncrates[] =
  154 {
  155         /*   mc_sdtr              period      rate */
  156         { ADW_MC_SDTR_80,           9,       "80.0"  },
  157         { ADW_MC_SDTR_40,           10,      "40.0"  },
  158         { ADW_MC_SDTR_20,           12,      "20.0"  },
  159         { ADW_MC_SDTR_10,           25,      "10.0"  },
  160         { ADW_MC_SDTR_5,            50,      "5.0"   },
  161         { ADW_MC_SDTR_ASYNC,        0,       "async" }
  162 };
  163 
  164 static u_int16_t        adw_eeprom_read_16(struct adw_softc *adw, int addr);
  165 static void             adw_eeprom_write_16(struct adw_softc *adw, int addr,
  166                                             u_int data);
  167 static void             adw_eeprom_wait(struct adw_softc *adw);
  168 
  169 int
  170 adw_find_signature(struct adw_softc *adw)
  171 {
  172         if (adw_inb(adw, ADW_SIGNATURE_BYTE) == ADW_CHIP_ID_BYTE
  173          && adw_inw(adw, ADW_SIGNATURE_WORD) == ADW_CHIP_ID_WORD)
  174                 return (1);
  175         return (0);
  176 }
  177 
  178 /*
  179  * Reset Chip.
  180  */
  181 void
  182 adw_reset_chip(struct adw_softc *adw)
  183 {
  184         adw_outw(adw, ADW_CTRL_REG, ADW_CTRL_REG_CMD_RESET);
  185         DELAY(1000 * 100);
  186         adw_outw(adw, ADW_CTRL_REG, ADW_CTRL_REG_CMD_WR_IO_REG);
  187 
  188         /*
  189          * Initialize Chip registers.
  190          */
  191         adw_outw(adw, ADW_SCSI_CFG1,
  192                  adw_inw(adw, ADW_SCSI_CFG1) & ~ADW_SCSI_CFG1_BIG_ENDIAN);
  193 }
  194 
  195 /*
  196  * Reset the SCSI bus.
  197  */
  198 int
  199 adw_reset_bus(struct adw_softc *adw)
  200 {
  201         adw_idle_cmd_status_t status;
  202 
  203         if (!dumping)
  204                 mtx_assert(&adw->lock, MA_OWNED);
  205         status =
  206             adw_idle_cmd_send(adw, ADW_IDLE_CMD_SCSI_RESET_START, /*param*/0);
  207         if (status != ADW_IDLE_CMD_SUCCESS) {
  208                 xpt_print_path(adw->path);
  209                 printf("Bus Reset start attempt failed\n");
  210                 return (1);
  211         }
  212         DELAY(ADW_BUS_RESET_HOLD_DELAY_US);
  213         status =
  214             adw_idle_cmd_send(adw, ADW_IDLE_CMD_SCSI_RESET_END, /*param*/0);
  215         if (status != ADW_IDLE_CMD_SUCCESS) {
  216                 xpt_print_path(adw->path);
  217                 printf("Bus Reset end attempt failed\n");
  218                 return (1);
  219         }
  220         return (0);
  221 }
  222 
  223 /*
  224  * Read the specified EEPROM location
  225  */
  226 static u_int16_t
  227 adw_eeprom_read_16(struct adw_softc *adw, int addr)
  228 {
  229         adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_READ | addr);
  230         adw_eeprom_wait(adw);
  231         return (adw_inw(adw, ADW_EEP_DATA));
  232 }
  233 
  234 static void
  235 adw_eeprom_write_16(struct adw_softc *adw, int addr, u_int data)
  236 {
  237         adw_outw(adw, ADW_EEP_DATA, data);
  238         adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE | addr);
  239         adw_eeprom_wait(adw);
  240 }
  241 
  242 /*
  243  * Wait for and EEPROM command to complete
  244  */
  245 static void
  246 adw_eeprom_wait(struct adw_softc *adw)
  247 {
  248         int i;
  249 
  250         for (i = 0; i < ADW_EEP_DELAY_MS; i++) {
  251                 if ((adw_inw(adw, ADW_EEP_CMD) & ADW_EEP_CMD_DONE) != 0)
  252                         break;
  253                 DELAY(1000);
  254         }
  255         if (i == ADW_EEP_DELAY_MS)
  256                 panic("%s: Timedout Reading EEPROM",
  257                     device_get_nameunit(adw->device));
  258 }
  259 
  260 /*
  261  * Read EEPROM configuration into the specified buffer.
  262  *
  263  * Return a checksum based on the EEPROM configuration read.
  264  */
  265 u_int16_t
  266 adw_eeprom_read(struct adw_softc *adw, struct adw_eeprom *eep_buf)
  267 {
  268         u_int16_t *wbuf;
  269         u_int16_t  wval;
  270         u_int16_t  chksum;
  271         int        eep_addr;
  272 
  273         wbuf = (u_int16_t *)eep_buf;
  274         chksum = 0;
  275 
  276         for (eep_addr = ADW_EEP_DVC_CFG_BEGIN;
  277              eep_addr < ADW_EEP_DVC_CFG_END;
  278              eep_addr++, wbuf++) {
  279                 wval = adw_eeprom_read_16(adw, eep_addr);
  280                 chksum += wval;
  281                 *wbuf = wval;
  282         }
  283 
  284         /* checksum field is not counted in the checksum */
  285         *wbuf = adw_eeprom_read_16(adw, eep_addr);
  286         wbuf++;
  287         
  288         /* Driver seeprom variables are not included in the checksum */
  289         for (eep_addr = ADW_EEP_DVC_CTL_BEGIN;
  290              eep_addr < ADW_EEP_MAX_WORD_ADDR;
  291              eep_addr++, wbuf++)
  292                 *wbuf = adw_eeprom_read_16(adw, eep_addr);
  293 
  294         return (chksum);
  295 }
  296 
  297 void
  298 adw_eeprom_write(struct adw_softc *adw, struct adw_eeprom *eep_buf)
  299 {
  300         u_int16_t *wbuf;
  301         u_int16_t  addr;
  302         u_int16_t  chksum;
  303 
  304         wbuf = (u_int16_t *)eep_buf;
  305         chksum = 0;
  306 
  307         adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE_ABLE);
  308         adw_eeprom_wait(adw);
  309 
  310         /*
  311          * Write EEPROM until checksum.
  312          */
  313         for (addr = ADW_EEP_DVC_CFG_BEGIN;
  314              addr < ADW_EEP_DVC_CFG_END; addr++, wbuf++) {
  315                 chksum += *wbuf;
  316                 adw_eeprom_write_16(adw, addr, *wbuf);
  317         }
  318 
  319         /*
  320          * Write calculated EEPROM checksum
  321          */
  322         adw_eeprom_write_16(adw, addr, chksum);
  323 
  324         /* skip over buffer's checksum */
  325         wbuf++;
  326 
  327         /*
  328          * Write the rest.
  329          */
  330         for (addr = ADW_EEP_DVC_CTL_BEGIN;
  331              addr < ADW_EEP_MAX_WORD_ADDR; addr++, wbuf++)
  332                 adw_eeprom_write_16(adw, addr, *wbuf);
  333 
  334         adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE_DISABLE);
  335         adw_eeprom_wait(adw);
  336 }
  337 
  338 int
  339 adw_init_chip(struct adw_softc *adw, u_int term_scsicfg1)
  340 {
  341         u_int8_t            biosmem[ADW_MC_BIOSLEN];
  342         const u_int16_t    *word_table;
  343         const u_int8_t     *byte_codes;
  344         const u_int8_t     *byte_codes_end;
  345         u_int               bios_sig;
  346         u_int               bytes_downloaded;
  347         u_int               addr;
  348         u_int               end_addr;
  349         u_int               checksum;
  350         u_int               scsicfg1;
  351         u_int               tid;
  352 
  353         /*
  354          * Save the RISC memory BIOS region before writing the microcode.
  355          * The BIOS may already be loaded and using its RISC LRAM region
  356          * so its region must be saved and restored.
  357          */
  358         for (addr = 0; addr < ADW_MC_BIOSLEN; addr++)
  359                 biosmem[addr] = adw_lram_read_8(adw, ADW_MC_BIOSMEM + addr);
  360 
  361         /*
  362          * Save current per TID negotiated values if the BIOS has been
  363          * loaded (BIOS signature is present).  These will be used if
  364          * we cannot get information from the EEPROM.
  365          */
  366         addr = ADW_MC_BIOS_SIGNATURE - ADW_MC_BIOSMEM;
  367         bios_sig = biosmem[addr]
  368                  | (biosmem[addr + 1] << 8);
  369         if (bios_sig == 0x55AA
  370          && (adw->flags & ADW_EEPROM_FAILED) != 0) {
  371                 u_int major_ver;
  372                 u_int minor_ver;
  373                 u_int sdtr_able;
  374 
  375                 addr = ADW_MC_BIOS_VERSION - ADW_MC_BIOSMEM;
  376                 minor_ver = biosmem[addr + 1] & 0xF;
  377                 major_ver = (biosmem[addr + 1] >> 4) & 0xF;
  378                 if ((adw->chip == ADW_CHIP_ASC3550)
  379                  && (major_ver <= 3
  380                   || (major_ver == 3 && minor_ver <= 1))) {
  381                         /*
  382                          * BIOS 3.1 and earlier location of
  383                          * 'wdtr_able' variable.
  384                          */
  385                         adw->user_wdtr =
  386                             adw_lram_read_16(adw, ADW_MC_WDTR_ABLE_BIOS_31);
  387                 } else {
  388                         adw->user_wdtr =
  389                             adw_lram_read_16(adw, ADW_MC_WDTR_ABLE);
  390                 }
  391                 sdtr_able = adw_lram_read_16(adw, ADW_MC_SDTR_ABLE);
  392                 for (tid = 0; tid < ADW_MAX_TID; tid++) {
  393                         u_int tid_mask;
  394                         u_int mc_sdtr;
  395 
  396                         tid_mask = 0x1 << tid;
  397                         if ((sdtr_able & tid_mask) == 0)
  398                                 mc_sdtr = ADW_MC_SDTR_ASYNC;
  399                         else if ((adw->features & ADW_DT) != 0)
  400                                 mc_sdtr = ADW_MC_SDTR_80;
  401                         else if ((adw->features & ADW_ULTRA2) != 0)
  402                                 mc_sdtr = ADW_MC_SDTR_40;
  403                         else
  404                                 mc_sdtr = ADW_MC_SDTR_20;
  405                         adw_set_user_sdtr(adw, tid, mc_sdtr);
  406                 }
  407                 adw->user_tagenb = adw_lram_read_16(adw, ADW_MC_TAGQNG_ABLE);
  408         }
  409 
  410         /*
  411          * Load the Microcode.
  412          *
  413          * Assume the following compressed format of the microcode buffer:
  414          *
  415          *      253 word (506 byte) table indexed by byte code followed
  416          *      by the following byte codes:
  417          *
  418          *      1-Byte Code:
  419          *              00: Emit word 0 in table.
  420          *              01: Emit word 1 in table.
  421          *              .
  422          *              FD: Emit word 253 in table.
  423          *
  424          *      Multi-Byte Code:
  425          *              FD RESEVED
  426          *
  427          *              FE WW WW: (3 byte code)
  428          *                      Word to emit is the next word WW WW.
  429          *              FF BB WW WW: (4 byte code)
  430          *                      Emit BB count times next word WW WW.
  431          *
  432          */
  433         bytes_downloaded = 0;
  434         word_table = (const u_int16_t *)adw->mcode_data->mcode_buf;
  435         byte_codes = (const u_int8_t *)&word_table[253];
  436         byte_codes_end = adw->mcode_data->mcode_buf
  437                        + adw->mcode_data->mcode_size;
  438         adw_outw(adw, ADW_RAM_ADDR, 0);
  439         while (byte_codes < byte_codes_end) {
  440                 if (*byte_codes == 0xFF) {
  441                         u_int16_t value;
  442 
  443                         value = byte_codes[2]
  444                               | byte_codes[3] << 8;
  445                         adw_set_multi_2(adw, ADW_RAM_DATA,
  446                                         value, byte_codes[1]);
  447                         bytes_downloaded += byte_codes[1];
  448                         byte_codes += 4;
  449                 } else if (*byte_codes == 0xFE) {
  450                         u_int16_t value;
  451 
  452                         value = byte_codes[1]
  453                               | byte_codes[2] << 8;
  454                         adw_outw(adw, ADW_RAM_DATA, value);
  455                         bytes_downloaded++;
  456                         byte_codes += 3;
  457                 } else {
  458                         adw_outw(adw, ADW_RAM_DATA, word_table[*byte_codes]);
  459                         bytes_downloaded++;
  460                         byte_codes++;
  461                 }
  462         }
  463         /* Convert from words to bytes */
  464         bytes_downloaded *= 2;
  465 
  466         /*
  467          * Clear the rest of LRAM.
  468          */
  469         for (addr = bytes_downloaded; addr < adw->memsize; addr += 2)
  470                 adw_outw(adw, ADW_RAM_DATA, 0);
  471 
  472         /*
  473          * Verify the microcode checksum.
  474          */
  475         checksum = 0;
  476         adw_outw(adw, ADW_RAM_ADDR, 0);
  477         for (addr = 0; addr < bytes_downloaded; addr += 2)
  478                 checksum += adw_inw(adw, ADW_RAM_DATA);
  479 
  480         if (checksum != adw->mcode_data->mcode_chksum) {
  481                 device_printf(adw->device, "Firmware load failed!\n");
  482                 return (EIO);
  483         }
  484 
  485         /*
  486          * Restore the RISC memory BIOS region.
  487          */
  488         for (addr = 0; addr < ADW_MC_BIOSLEN; addr++)
  489                 adw_lram_write_8(adw, addr + ADW_MC_BIOSLEN, biosmem[addr]);
  490 
  491         /*
  492          * Calculate and write the microcode code checksum to
  493          * the microcode code checksum location.
  494          */
  495         addr = adw_lram_read_16(adw, ADW_MC_CODE_BEGIN_ADDR);
  496         end_addr = adw_lram_read_16(adw, ADW_MC_CODE_END_ADDR);
  497         checksum = 0;
  498         adw_outw(adw, ADW_RAM_ADDR, addr);
  499         for (; addr < end_addr; addr += 2)
  500                 checksum += adw_inw(adw, ADW_RAM_DATA);
  501         adw_lram_write_16(adw, ADW_MC_CODE_CHK_SUM, checksum);
  502 
  503         /*
  504          * Tell the microcode what kind of chip it's running on.
  505          */
  506         adw_lram_write_16(adw, ADW_MC_CHIP_TYPE, adw->chip);
  507 
  508         /*
  509          * Leave WDTR and SDTR negotiation disabled until the XPT has
  510          * informed us of device capabilities, but do set the desired
  511          * user rates in case we receive an SDTR request from the target
  512          * before we negotiate.  We turn on tagged queuing at the microcode
  513          * level for all devices, and modulate this on a per command basis.
  514          */
  515         adw_lram_write_16(adw, ADW_MC_SDTR_SPEED1, adw->user_sdtr[0]);
  516         adw_lram_write_16(adw, ADW_MC_SDTR_SPEED2, adw->user_sdtr[1]);
  517         adw_lram_write_16(adw, ADW_MC_SDTR_SPEED3, adw->user_sdtr[2]);
  518         adw_lram_write_16(adw, ADW_MC_SDTR_SPEED4, adw->user_sdtr[3]);
  519         adw_lram_write_16(adw, ADW_MC_DISC_ENABLE, adw->user_discenb);
  520         for (tid = 0; tid < ADW_MAX_TID; tid++) {
  521                 /* Cam limits the maximum number of commands for us */
  522                 adw_lram_write_8(adw, ADW_MC_NUMBER_OF_MAX_CMD + tid,
  523                                  adw->max_acbs);
  524         }
  525         adw_lram_write_16(adw, ADW_MC_TAGQNG_ABLE, ~0);
  526 
  527         /*
  528          * Set SCSI_CFG0 Microcode Default Value.
  529          *
  530          * The microcode will set the SCSI_CFG0 register using this value
  531          * after it is started.
  532          */
  533         adw_lram_write_16(adw, ADW_MC_DEFAULT_SCSI_CFG0,
  534                           ADW_SCSI_CFG0_PARITY_EN|ADW_SCSI_CFG0_SEL_TMO_LONG|
  535                           ADW_SCSI_CFG0_OUR_ID_EN|adw->initiator_id);
  536 
  537         /*
  538          * Tell the MC about the memory size that
  539          * was setup by the probe code.
  540          */
  541         adw_lram_write_16(adw, ADW_MC_DEFAULT_MEM_CFG,
  542                           adw_inb(adw, ADW_MEM_CFG) & ADW_MEM_CFG_RAM_SZ_MASK);
  543 
  544         /*
  545          * Determine SCSI_CFG1 Microcode Default Value.
  546          *
  547          * The microcode will set the SCSI_CFG1 register using this value
  548          * after it is started below.
  549          */
  550         scsicfg1 = adw_inw(adw, ADW_SCSI_CFG1);
  551 
  552         /*
  553          * If the internal narrow cable is reversed all of the SCSI_CTRL
  554          * register signals will be set. Check for and return an error if
  555          * this condition is found.
  556          */
  557         if ((adw_inw(adw, ADW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
  558                 device_printf(adw->device, "Illegal Cable Config!\n");
  559                 device_printf(adw->device, "Internal cable is reversed!\n");
  560                 return (EIO);
  561         }
  562 
  563         /*
  564          * If this is a differential board and a single-ended device
  565          * is attached to one of the connectors, return an error.
  566          */
  567         if ((adw->features & ADW_ULTRA) != 0)  {
  568                 if ((scsicfg1 & ADW_SCSI_CFG1_DIFF_MODE) != 0
  569                  && (scsicfg1 & ADW_SCSI_CFG1_DIFF_SENSE) == 0) {
  570                         device_printf(adw->device, "A Single Ended Device is "
  571                             "attached to our differential bus!\n");
  572                         return (EIO);
  573                 }
  574         } else {
  575                 if ((scsicfg1 & ADW2_SCSI_CFG1_DEV_DETECT_HVD) != 0) {
  576                         device_printf(adw->device,
  577                             "A High Voltage Differential Device "
  578                             "is attached to this controller.\n");
  579                         device_printf(adw->device,
  580                             "HVD devices are not supported.\n");
  581                         return (EIO);
  582                 }
  583         }
  584 
  585         /*
  586          * Perform automatic termination control if desired.
  587          */
  588         if ((adw->features & ADW_ULTRA2) != 0) {
  589                 u_int cable_det;
  590 
  591                 /*
  592                  * Ultra2 Chips require termination disabled to
  593                  * detect cable presence.
  594                  */
  595                 adw_outw(adw, ADW_SCSI_CFG1,
  596                          scsicfg1 | ADW2_SCSI_CFG1_DIS_TERM_DRV);
  597                 cable_det = adw_inw(adw, ADW_SCSI_CFG1);
  598                 adw_outw(adw, ADW_SCSI_CFG1, scsicfg1);
  599 
  600                 /* SE Termination first if auto-term has been specified */
  601                 if ((term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) == 0) {
  602 
  603                         /*
  604                          * For all SE cable configurations, high byte
  605                          * termination is enabled.
  606                          */
  607                         term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H;
  608                         if ((cable_det & ADW_SCSI_CFG1_INT8_MASK) != 0
  609                          || (cable_det & ADW_SCSI_CFG1_INT16_MASK) != 0) {
  610                                 /*
  611                                  * If either cable is not present, the
  612                                  * low byte must be terminated as well.
  613                                  */
  614                                 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_L;
  615                         }
  616                 }
  617 
  618                 /* LVD auto-term */
  619                 if ((term_scsicfg1 & ADW2_SCSI_CFG1_TERM_CTL_LVD) == 0
  620                  && (term_scsicfg1 & ADW2_SCSI_CFG1_DIS_TERM_DRV) == 0) {
  621                         /*
  622                          * If both cables are installed, termination
  623                          * is disabled.  Otherwise it is enabled.
  624                          */
  625                         if ((cable_det & ADW2_SCSI_CFG1_EXTLVD_MASK) != 0
  626                          || (cable_det & ADW2_SCSI_CFG1_INTLVD_MASK) != 0) {
  627 
  628                                 term_scsicfg1 |= ADW2_SCSI_CFG1_TERM_CTL_LVD;
  629                         }
  630                 }
  631                 term_scsicfg1 &= ~ADW2_SCSI_CFG1_DIS_TERM_DRV;
  632         } else {
  633                 /* Ultra Controller Termination */
  634                 if ((term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) == 0) {
  635                         int cable_count;
  636                         int wide_cable_count;
  637 
  638                         cable_count = 0;
  639                         wide_cable_count = 0;
  640                         if ((scsicfg1 & ADW_SCSI_CFG1_INT16_MASK) == 0) {
  641                                 cable_count++;
  642                                 wide_cable_count++;
  643                         }
  644                         if ((scsicfg1 & ADW_SCSI_CFG1_INT8_MASK) == 0)
  645                                 cable_count++;
  646 
  647                         /* There is only one external port */
  648                         if ((scsicfg1 & ADW_SCSI_CFG1_EXT16_MASK) == 0) {
  649                                 cable_count++;
  650                                 wide_cable_count++;
  651                         } else if ((scsicfg1 & ADW_SCSI_CFG1_EXT8_MASK) == 0)
  652                                 cable_count++;
  653 
  654                         if (cable_count == 3) {
  655                                 device_printf(adw->device,
  656                                     "Illegal Cable Config!\n");
  657                                 device_printf(adw->device,
  658                                     "Only Two Ports may be used at a time!\n");
  659                         } else if (cable_count <= 1) {
  660                                 /*
  661                                  * At least two out of three cables missing.
  662                                  * Terminate both bytes.
  663                                  */
  664                                 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H
  665                                               |  ADW_SCSI_CFG1_TERM_CTL_L;
  666                         } else if (wide_cable_count <= 1) {
  667                                 /* No two 16bit cables present.  High on. */
  668                                 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H;
  669                         }
  670                 }
  671         }
  672 
  673         /* Tell the user about our decission */
  674         switch (term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) {
  675         case ADW_SCSI_CFG1_TERM_CTL_MASK:
  676                 printf("High & Low SE Term Enabled, ");
  677                 break;
  678         case ADW_SCSI_CFG1_TERM_CTL_H:
  679                 printf("High SE Termination Enabled, ");
  680                 break;
  681         case ADW_SCSI_CFG1_TERM_CTL_L:
  682                 printf("Low SE Term Enabled, ");
  683                 break;
  684         default:
  685                 break;
  686         }
  687 
  688         if ((adw->features & ADW_ULTRA2) != 0
  689          && (term_scsicfg1 & ADW2_SCSI_CFG1_TERM_CTL_LVD) != 0)
  690                 printf("LVD Term Enabled, ");
  691 
  692         /*
  693          * Invert the TERM_CTL_H and TERM_CTL_L bits and then
  694          * set 'scsicfg1'. The TERM_POL bit does not need to be
  695          * referenced, because the hardware internally inverts
  696          * the Termination High and Low bits if TERM_POL is set.
  697          */
  698         if ((adw->features & ADW_ULTRA2) != 0) {
  699                 term_scsicfg1 = ~term_scsicfg1;
  700                 term_scsicfg1 &= ADW_SCSI_CFG1_TERM_CTL_MASK
  701                               |  ADW2_SCSI_CFG1_TERM_CTL_LVD;
  702                 scsicfg1 &= ~(ADW_SCSI_CFG1_TERM_CTL_MASK
  703                              |ADW2_SCSI_CFG1_TERM_CTL_LVD
  704                              |ADW_SCSI_CFG1_BIG_ENDIAN
  705                              |ADW_SCSI_CFG1_TERM_POL
  706                              |ADW2_SCSI_CFG1_DEV_DETECT);
  707                 scsicfg1 |= term_scsicfg1;
  708         } else {
  709                 term_scsicfg1 = ~term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK;
  710                 scsicfg1 &= ~ADW_SCSI_CFG1_TERM_CTL_MASK;
  711                 scsicfg1 |= term_scsicfg1 | ADW_SCSI_CFG1_TERM_CTL_MANUAL;
  712                 scsicfg1 |= ADW_SCSI_CFG1_FLTR_DISABLE;
  713         }
  714 
  715         /*
  716          * Set SCSI_CFG1 Microcode Default Value
  717          *
  718          * The microcode will set the SCSI_CFG1 register using this value
  719          * after it is started below.
  720          */
  721         adw_lram_write_16(adw, ADW_MC_DEFAULT_SCSI_CFG1, scsicfg1);
  722 
  723         /*
  724          * Only accept selections on our initiator target id.
  725          * This may change in target mode scenarios...
  726          */
  727         adw_lram_write_16(adw, ADW_MC_DEFAULT_SEL_MASK,
  728                           (0x01 << adw->initiator_id));
  729 
  730         /*
  731          * Tell the microcode where it can find our
  732          * Initiator Command Queue (ICQ).  It is
  733          * currently empty hence the "stopper" address.
  734          */
  735         adw->commandq = adw->free_carriers;
  736         adw->free_carriers = carrierbotov(adw, adw->commandq->next_ba);
  737         adw->commandq->next_ba = ADW_CQ_STOPPER;
  738         adw_lram_write_32(adw, ADW_MC_ICQ, adw->commandq->carr_ba);
  739 
  740         /*
  741          * Tell the microcode where it can find our
  742          * Initiator Response Queue (IRQ).  It too
  743          * is currently empty.
  744          */
  745         adw->responseq = adw->free_carriers;
  746         adw->free_carriers = carrierbotov(adw, adw->responseq->next_ba);
  747         adw->responseq->next_ba = ADW_CQ_STOPPER;
  748         adw_lram_write_32(adw, ADW_MC_IRQ, adw->responseq->carr_ba);
  749 
  750         adw_outb(adw, ADW_INTR_ENABLES,
  751                  ADW_INTR_ENABLE_HOST_INTR|ADW_INTR_ENABLE_GLOBAL_INTR);
  752 
  753         adw_outw(adw, ADW_PC, adw_lram_read_16(adw, ADW_MC_CODE_BEGIN_ADDR));
  754 
  755         return (0);
  756 }
  757 
  758 void
  759 adw_set_user_sdtr(struct adw_softc *adw, u_int tid, u_int mc_sdtr)
  760 {
  761         adw->user_sdtr[ADW_TARGET_GROUP(tid)] &= ~ADW_TARGET_GROUP_MASK(tid);
  762         adw->user_sdtr[ADW_TARGET_GROUP(tid)] |=
  763             mc_sdtr << ADW_TARGET_GROUP_SHIFT(tid);
  764 }
  765 
  766 u_int
  767 adw_get_user_sdtr(struct adw_softc *adw, u_int tid)
  768 {
  769         u_int mc_sdtr;
  770 
  771         mc_sdtr = adw->user_sdtr[ADW_TARGET_GROUP(tid)];
  772         mc_sdtr &= ADW_TARGET_GROUP_MASK(tid);
  773         mc_sdtr >>= ADW_TARGET_GROUP_SHIFT(tid);
  774         return (mc_sdtr);
  775 }
  776 
  777 void
  778 adw_set_chip_sdtr(struct adw_softc *adw, u_int tid, u_int sdtr)
  779 {
  780         u_int mc_sdtr_offset;
  781         u_int mc_sdtr;
  782 
  783         mc_sdtr_offset = ADW_MC_SDTR_SPEED1;
  784         mc_sdtr_offset += ADW_TARGET_GROUP(tid) * 2;
  785         mc_sdtr = adw_lram_read_16(adw, mc_sdtr_offset);
  786         mc_sdtr &= ~ADW_TARGET_GROUP_MASK(tid);
  787         mc_sdtr |= sdtr << ADW_TARGET_GROUP_SHIFT(tid);
  788         adw_lram_write_16(adw, mc_sdtr_offset, mc_sdtr);
  789 }
  790 
  791 u_int
  792 adw_get_chip_sdtr(struct adw_softc *adw, u_int tid)
  793 {
  794         u_int mc_sdtr_offset;
  795         u_int mc_sdtr;
  796 
  797         mc_sdtr_offset = ADW_MC_SDTR_SPEED1;
  798         mc_sdtr_offset += ADW_TARGET_GROUP(tid) * 2;
  799         mc_sdtr = adw_lram_read_16(adw, mc_sdtr_offset);
  800         mc_sdtr &= ADW_TARGET_GROUP_MASK(tid);
  801         mc_sdtr >>= ADW_TARGET_GROUP_SHIFT(tid);
  802         return (mc_sdtr);
  803 }
  804 
  805 u_int
  806 adw_find_sdtr(struct adw_softc *adw, u_int period)
  807 {
  808         int i;
  809 
  810         i = 0;
  811         if ((adw->features & ADW_DT) == 0)
  812                 i = ADW_MC_SDTR_OFFSET_ULTRA2;
  813         if ((adw->features & ADW_ULTRA2) == 0)
  814                 i = ADW_MC_SDTR_OFFSET_ULTRA;
  815         if (period == 0)
  816                 return ADW_MC_SDTR_ASYNC;
  817 
  818         for (; i < nitems(adw_syncrates); i++) {
  819                 if (period <= adw_syncrates[i].period)
  820                         return (adw_syncrates[i].mc_sdtr);
  821         }       
  822         return ADW_MC_SDTR_ASYNC;
  823 }
  824 
  825 u_int
  826 adw_find_period(struct adw_softc *adw, u_int mc_sdtr)
  827 {
  828         int i;
  829 
  830         for (i = 0; i < nitems(adw_syncrates); i++) {
  831                 if (mc_sdtr == adw_syncrates[i].mc_sdtr)
  832                         break;
  833         }       
  834         return (adw_syncrates[i].period);
  835 }
  836 
  837 u_int
  838 adw_hshk_cfg_period_factor(u_int tinfo)
  839 {
  840         tinfo &= ADW_HSHK_CFG_RATE_MASK;
  841         tinfo >>= ADW_HSHK_CFG_RATE_SHIFT;
  842         if (tinfo == 0x11)
  843                 /* 80MHz/DT */
  844                 return (9);
  845         else if (tinfo == 0x10)
  846                 /* 40MHz */
  847                 return (10);
  848         else
  849                 return (((tinfo * 25) + 50) / 4);
  850 }
  851 
  852 /*
  853  * Send an idle command to the chip and wait for completion.
  854  */
  855 adw_idle_cmd_status_t
  856 adw_idle_cmd_send(struct adw_softc *adw, adw_idle_cmd_t cmd, u_int parameter)
  857 {
  858         u_int                 timeout;
  859         adw_idle_cmd_status_t status;
  860 
  861         if (!dumping)
  862                 mtx_assert(&adw->lock, MA_OWNED);
  863 
  864         /*
  865          * Clear the idle command status which is set by the microcode
  866          * to a non-zero value to indicate when the command is completed.
  867          */
  868         adw_lram_write_16(adw, ADW_MC_IDLE_CMD_STATUS, 0);
  869 
  870         /*
  871          * Write the idle command value after the idle command parameter
  872          * has been written to avoid a race condition. If the order is not
  873          * followed, the microcode may process the idle command before the
  874          * parameters have been written to LRAM.
  875          */
  876         adw_lram_write_32(adw, ADW_MC_IDLE_CMD_PARAMETER, parameter);
  877         adw_lram_write_16(adw, ADW_MC_IDLE_CMD, cmd);
  878 
  879         /*
  880          * Tickle the RISC to tell it to process the idle command.
  881          */
  882         adw_tickle_risc(adw, ADW_TICKLE_B);
  883 
  884         /* Wait for up to 10 seconds for the command to complete */
  885         timeout = 5000000;
  886         while (--timeout) {
  887                 status = adw_lram_read_16(adw, ADW_MC_IDLE_CMD_STATUS);
  888                 if (status != 0)
  889                         break;
  890                 DELAY(20);
  891         }
  892 
  893         if (timeout == 0)
  894                 panic("%s: Idle Command Timed Out!",
  895                     device_get_nameunit(adw->device));
  896         return (status);
  897 }

Cache object: d41798bd143a55b21c1e02248d18bac6


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