The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/advansys/adwlib.c

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    1 /*
    2  * Low level routines for Second Generation
    3  * Advanced Systems Inc. SCSI controllers chips
    4  *
    5  * Copyright (c) 1998, 1999, 2000 Justin Gibbs.
    6  * All rights reserved.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions, and the following disclaimer,
   13  *    without modification.
   14  * 2. Redistributions in binary form must reproduce the above copyright
   15  *    notice, this list of conditions and the following disclaimer in the
   16  *    documentation and/or other materials provided with the distribution.
   17  * 3. The name of the author may not be used to endorse or promote products
   18  *    derived from this software without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
   24  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   30  * SUCH DAMAGE.
   31  *
   32  * $FreeBSD: releng/5.1/sys/dev/advansys/adwlib.c 67164 2000-10-15 14:19:01Z phk $
   33  */
   34 /*
   35  * Ported from:
   36  * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
   37  *     
   38  * Copyright (c) 1995-1998 Advanced System Products, Inc.
   39  * All Rights Reserved.
   40  *   
   41  * Redistribution and use in source and binary forms, with or without
   42  * modification, are permitted provided that redistributions of source
   43  * code retain the above copyright notice and this comment without
   44  * modification.
   45  */
   46 
   47 #include <sys/param.h>
   48 #include <sys/systm.h>
   49 #include <sys/bus.h>
   50 
   51 #include <machine/bus_pio.h>
   52 #include <machine/bus_memio.h>
   53 #include <machine/bus.h>
   54 
   55 #include <cam/cam.h>
   56 #include <cam/cam_ccb.h>
   57 #include <cam/cam_sim.h>
   58 #include <cam/cam_xpt_sim.h>
   59 #include <cam/scsi/scsi_all.h>
   60 
   61 #include <dev/advansys/adwlib.h>
   62 
   63 const struct adw_eeprom adw_asc3550_default_eeprom =
   64 {
   65         ADW_EEPROM_BIOS_ENABLE,         /* cfg_lsw */
   66         0x0000,                         /* cfg_msw */
   67         0xFFFF,                         /* disc_enable */
   68         0xFFFF,                         /* wdtr_able */
   69         { 0xFFFF },                     /* sdtr_able */
   70         0xFFFF,                         /* start_motor */
   71         0xFFFF,                         /* tagqng_able */
   72         0xFFFF,                         /* bios_scan */
   73         0,                              /* scam_tolerant */
   74         7,                              /* adapter_scsi_id */
   75         0,                              /* bios_boot_delay */
   76         3,                              /* scsi_reset_delay */
   77         0,                              /* bios_id_lun */
   78         0,                              /* termination */
   79         0,                              /* reserved1 */
   80         0xFFE7,                         /* bios_ctrl */
   81         { 0xFFFF },                     /* ultra_able */   
   82         { 0 },                          /* reserved2 */
   83         ADW_DEF_MAX_HOST_QNG,           /* max_host_qng */
   84         ADW_DEF_MAX_DVC_QNG,            /* max_dvc_qng */
   85         0,                              /* dvc_cntl */
   86         { 0 },                          /* bug_fix */
   87         { 0, 0, 0 },                    /* serial_number */
   88         0,                              /* check_sum */
   89         {                               /* oem_name[16] */
   90           0, 0, 0, 0, 0, 0, 0, 0,
   91           0, 0, 0, 0, 0, 0, 0, 0
   92         },
   93         0,                              /* dvc_err_code */
   94         0,                              /* adv_err_code */
   95         0,                              /* adv_err_addr */
   96         0,                              /* saved_dvc_err_code */
   97         0,                              /* saved_adv_err_code */
   98         0                               /* saved_adv_err_addr */
   99 };
  100 
  101 const struct adw_eeprom adw_asc38C0800_default_eeprom =
  102 {
  103         ADW_EEPROM_BIOS_ENABLE,         /* 00 cfg_lsw */
  104         0x0000,                         /* 01 cfg_msw */
  105         0xFFFF,                         /* 02 disc_enable */
  106         0xFFFF,                         /* 03 wdtr_able */
  107         { 0x4444 },                     /* 04 sdtr_speed1 */
  108         0xFFFF,                         /* 05 start_motor */
  109         0xFFFF,                         /* 06 tagqng_able */
  110         0xFFFF,                         /* 07 bios_scan */
  111         0,                              /* 08 scam_tolerant */
  112         7,                              /* 09 adapter_scsi_id */
  113         0,                              /*    bios_boot_delay */
  114         3,                              /* 10 scsi_reset_delay */
  115         0,                              /*    bios_id_lun */
  116         0,                              /* 11 termination_se */
  117         0,                              /*    termination_lvd */
  118         0xFFE7,                         /* 12 bios_ctrl */
  119         { 0x4444 },                     /* 13 sdtr_speed2 */
  120         { 0x4444 },                     /* 14 sdtr_speed3 */
  121         ADW_DEF_MAX_HOST_QNG,           /* 15 max_host_qng */
  122         ADW_DEF_MAX_DVC_QNG,            /*    max_dvc_qng */
  123         0,                              /* 16 dvc_cntl */
  124         { 0x4444 } ,                    /* 17 sdtr_speed4 */
  125         { 0, 0, 0 },                    /* 18-20 serial_number */
  126         0,                              /* 21 check_sum */
  127         {                               /* 22-29 oem_name[16] */
  128           0, 0, 0, 0, 0, 0, 0, 0,
  129           0, 0, 0, 0, 0, 0, 0, 0
  130         },
  131         0,                              /* 30 dvc_err_code */
  132         0,                              /* 31 adv_err_code */
  133         0,                              /* 32 adv_err_addr */
  134         0,                              /* 33 saved_dvc_err_code */
  135         0,                              /* 34 saved_adv_err_code */
  136         0,                              /* 35 saved_adv_err_addr */
  137         {                               /* 36 - 55 reserved */
  138           0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  139           0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  140         },
  141         0,                              /* 56 cisptr_lsw */
  142         0,                              /* 57 cisprt_msw */
  143                                         /* 58-59 sub-id */
  144         (PCI_ID_ADVANSYS_38C0800_REV1 & PCI_ID_DEV_VENDOR_MASK) >> 32,
  145 };
  146 
  147 #define ADW_MC_SDTR_OFFSET_ULTRA2_DT    0
  148 #define ADW_MC_SDTR_OFFSET_ULTRA2       1
  149 #define ADW_MC_SDTR_OFFSET_ULTRA        2
  150 const struct adw_syncrate adw_syncrates[] =
  151 {
  152         /*   mc_sdtr              period      rate */
  153         { ADW_MC_SDTR_80,           9,       "80.0"  },
  154         { ADW_MC_SDTR_40,           10,      "40.0"  },
  155         { ADW_MC_SDTR_20,           12,      "20.0"  },
  156         { ADW_MC_SDTR_10,           25,      "10.0"  },
  157         { ADW_MC_SDTR_5,            50,      "5.0"   },
  158         { ADW_MC_SDTR_ASYNC,        0,       "async" }
  159 };
  160 
  161 const int adw_num_syncrates = sizeof(adw_syncrates) / sizeof(adw_syncrates[0]);
  162 
  163 static u_int16_t        adw_eeprom_read_16(struct adw_softc *adw, int addr);
  164 static void             adw_eeprom_write_16(struct adw_softc *adw, int addr,
  165                                             u_int data);
  166 static void             adw_eeprom_wait(struct adw_softc *adw);
  167 
  168 int
  169 adw_find_signature(struct adw_softc *adw)
  170 {
  171         if (adw_inb(adw, ADW_SIGNATURE_BYTE) == ADW_CHIP_ID_BYTE
  172          && adw_inw(adw, ADW_SIGNATURE_WORD) == ADW_CHIP_ID_WORD)
  173                 return (1);
  174         return (0);
  175 }
  176 
  177 /*
  178  * Reset Chip.
  179  */
  180 void
  181 adw_reset_chip(struct adw_softc *adw)
  182 {
  183         adw_outw(adw, ADW_CTRL_REG, ADW_CTRL_REG_CMD_RESET);
  184         DELAY(1000 * 100);
  185         adw_outw(adw, ADW_CTRL_REG, ADW_CTRL_REG_CMD_WR_IO_REG);
  186 
  187         /*
  188          * Initialize Chip registers.
  189          */
  190         adw_outw(adw, ADW_SCSI_CFG1,
  191                  adw_inw(adw, ADW_SCSI_CFG1) & ~ADW_SCSI_CFG1_BIG_ENDIAN);
  192 }
  193 
  194 /*
  195  * Reset the SCSI bus.
  196  */
  197 int
  198 adw_reset_bus(struct adw_softc *adw)
  199 {
  200         adw_idle_cmd_status_t status;
  201 
  202         status =
  203             adw_idle_cmd_send(adw, ADW_IDLE_CMD_SCSI_RESET_START, /*param*/0);
  204         if (status != ADW_IDLE_CMD_SUCCESS) {
  205                 xpt_print_path(adw->path);
  206                 printf("Bus Reset start attempt failed\n");
  207                 return (1);
  208         }
  209         DELAY(ADW_BUS_RESET_HOLD_DELAY_US);
  210         status =
  211             adw_idle_cmd_send(adw, ADW_IDLE_CMD_SCSI_RESET_END, /*param*/0);
  212         if (status != ADW_IDLE_CMD_SUCCESS) {
  213                 xpt_print_path(adw->path);
  214                 printf("Bus Reset end attempt failed\n");
  215                 return (1);
  216         }
  217         return (0);
  218 }
  219 
  220 /*
  221  * Read the specified EEPROM location
  222  */
  223 static u_int16_t
  224 adw_eeprom_read_16(struct adw_softc *adw, int addr)
  225 {
  226         adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_READ | addr);
  227         adw_eeprom_wait(adw);
  228         return (adw_inw(adw, ADW_EEP_DATA));
  229 }
  230 
  231 static void
  232 adw_eeprom_write_16(struct adw_softc *adw, int addr, u_int data)
  233 {
  234         adw_outw(adw, ADW_EEP_DATA, data);
  235         adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE | addr);
  236         adw_eeprom_wait(adw);
  237 }
  238 
  239 /*
  240  * Wait for and EEPROM command to complete
  241  */
  242 static void
  243 adw_eeprom_wait(struct adw_softc *adw)
  244 {
  245         int i;
  246 
  247         for (i = 0; i < ADW_EEP_DELAY_MS; i++) {
  248                 if ((adw_inw(adw, ADW_EEP_CMD) & ADW_EEP_CMD_DONE) != 0)
  249                         break;
  250                 DELAY(1000);
  251         }
  252         if (i == ADW_EEP_DELAY_MS)
  253                 panic("%s: Timedout Reading EEPROM", adw_name(adw));
  254 }
  255 
  256 /*
  257  * Read EEPROM configuration into the specified buffer.
  258  *
  259  * Return a checksum based on the EEPROM configuration read.
  260  */
  261 u_int16_t
  262 adw_eeprom_read(struct adw_softc *adw, struct adw_eeprom *eep_buf)
  263 {
  264         u_int16_t *wbuf;
  265         u_int16_t  wval;
  266         u_int16_t  chksum;
  267         int        eep_addr;
  268 
  269         wbuf = (u_int16_t *)eep_buf;
  270         chksum = 0;
  271 
  272         for (eep_addr = ADW_EEP_DVC_CFG_BEGIN;
  273              eep_addr < ADW_EEP_DVC_CFG_END;
  274              eep_addr++, wbuf++) {
  275                 wval = adw_eeprom_read_16(adw, eep_addr);
  276                 chksum += wval;
  277                 *wbuf = wval;
  278         }
  279 
  280         /* checksum field is not counted in the checksum */
  281         *wbuf = adw_eeprom_read_16(adw, eep_addr);
  282         wbuf++;
  283         
  284         /* Driver seeprom variables are not included in the checksum */
  285         for (eep_addr = ADW_EEP_DVC_CTL_BEGIN;
  286              eep_addr < ADW_EEP_MAX_WORD_ADDR;
  287              eep_addr++, wbuf++)
  288                 *wbuf = adw_eeprom_read_16(adw, eep_addr);
  289 
  290         return (chksum);
  291 }
  292 
  293 void
  294 adw_eeprom_write(struct adw_softc *adw, struct adw_eeprom *eep_buf)
  295 {
  296         u_int16_t *wbuf;
  297         u_int16_t  addr;
  298         u_int16_t  chksum;
  299 
  300         wbuf = (u_int16_t *)eep_buf;
  301         chksum = 0;
  302 
  303         adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE_ABLE);
  304         adw_eeprom_wait(adw);
  305 
  306         /*
  307          * Write EEPROM until checksum.
  308          */
  309         for (addr = ADW_EEP_DVC_CFG_BEGIN;
  310              addr < ADW_EEP_DVC_CFG_END; addr++, wbuf++) {
  311                 chksum += *wbuf;
  312                 adw_eeprom_write_16(adw, addr, *wbuf);
  313         }
  314 
  315         /*
  316          * Write calculated EEPROM checksum
  317          */
  318         adw_eeprom_write_16(adw, addr, chksum);
  319 
  320         /* skip over buffer's checksum */
  321         wbuf++;
  322 
  323         /*
  324          * Write the rest.
  325          */
  326         for (addr = ADW_EEP_DVC_CTL_BEGIN;
  327              addr < ADW_EEP_MAX_WORD_ADDR; addr++, wbuf++)
  328                 adw_eeprom_write_16(adw, addr, *wbuf);
  329 
  330         adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE_DISABLE);
  331         adw_eeprom_wait(adw);
  332 }
  333 
  334 int
  335 adw_init_chip(struct adw_softc *adw, u_int term_scsicfg1)
  336 {
  337         u_int8_t            biosmem[ADW_MC_BIOSLEN];
  338         const u_int16_t    *word_table;
  339         const u_int8_t     *byte_codes;
  340         const u_int8_t     *byte_codes_end;
  341         u_int               bios_sig;
  342         u_int               bytes_downloaded;
  343         u_int               addr;
  344         u_int               end_addr;
  345         u_int               checksum;
  346         u_int               scsicfg1;
  347         u_int               tid;
  348 
  349         /*
  350          * Save the RISC memory BIOS region before writing the microcode.
  351          * The BIOS may already be loaded and using its RISC LRAM region
  352          * so its region must be saved and restored.
  353          */
  354         for (addr = 0; addr < ADW_MC_BIOSLEN; addr++)
  355                 biosmem[addr] = adw_lram_read_8(adw, ADW_MC_BIOSMEM + addr);
  356 
  357         /*
  358          * Save current per TID negotiated values if the BIOS has been
  359          * loaded (BIOS signature is present).  These will be used if
  360          * we cannot get information from the EEPROM.
  361          */
  362         addr = ADW_MC_BIOS_SIGNATURE - ADW_MC_BIOSMEM;
  363         bios_sig = biosmem[addr]
  364                  | (biosmem[addr + 1] << 8);
  365         if (bios_sig == 0x55AA
  366          && (adw->flags & ADW_EEPROM_FAILED) != 0) {
  367                 u_int major_ver;
  368                 u_int minor_ver;
  369                 u_int sdtr_able;
  370 
  371                 addr = ADW_MC_BIOS_VERSION - ADW_MC_BIOSMEM;
  372                 minor_ver = biosmem[addr + 1] & 0xF;
  373                 major_ver = (biosmem[addr + 1] >> 4) & 0xF;
  374                 if ((adw->chip == ADW_CHIP_ASC3550)
  375                  && (major_ver <= 3
  376                   || (major_ver == 3 && minor_ver == 1))) {
  377                         /*
  378                          * BIOS 3.1 and earlier location of
  379                          * 'wdtr_able' variable.
  380                          */
  381                         adw->user_wdtr =
  382                             adw_lram_read_16(adw, ADW_MC_WDTR_ABLE_BIOS_31);
  383                 } else {
  384                         adw->user_wdtr =
  385                             adw_lram_read_16(adw, ADW_MC_WDTR_ABLE);
  386                 }
  387                 sdtr_able = adw_lram_read_16(adw, ADW_MC_SDTR_ABLE);
  388                 for (tid = 0; tid < ADW_MAX_TID; tid++) {
  389                         u_int tid_mask;
  390                         u_int mc_sdtr;
  391 
  392                         tid_mask = 0x1 << tid;
  393                         if ((sdtr_able & tid_mask) == 0)
  394                                 mc_sdtr = ADW_MC_SDTR_ASYNC;
  395                         else if ((adw->features & ADW_DT) != 0)
  396                                 mc_sdtr = ADW_MC_SDTR_80;
  397                         else if ((adw->features & ADW_ULTRA2) != 0)
  398                                 mc_sdtr = ADW_MC_SDTR_40;
  399                         else
  400                                 mc_sdtr = ADW_MC_SDTR_20;
  401                         adw_set_user_sdtr(adw, tid, mc_sdtr);
  402                 }
  403                 adw->user_tagenb = adw_lram_read_16(adw, ADW_MC_TAGQNG_ABLE);
  404         }
  405 
  406         /*
  407          * Load the Microcode.
  408          *
  409          * Assume the following compressed format of the microcode buffer:
  410          *
  411          *      253 word (506 byte) table indexed by byte code followed
  412          *      by the following byte codes:
  413          *
  414          *      1-Byte Code:
  415          *              00: Emit word 0 in table.
  416          *              01: Emit word 1 in table.
  417          *              .
  418          *              FD: Emit word 253 in table.
  419          *
  420          *      Multi-Byte Code:
  421          *              FD RESEVED
  422          *
  423          *              FE WW WW: (3 byte code)
  424          *                      Word to emit is the next word WW WW.
  425          *              FF BB WW WW: (4 byte code)
  426          *                      Emit BB count times next word WW WW.
  427          *
  428          */
  429         bytes_downloaded = 0;
  430         word_table = (const u_int16_t *)adw->mcode_data->mcode_buf;
  431         byte_codes = (const u_int8_t *)&word_table[253];
  432         byte_codes_end = adw->mcode_data->mcode_buf
  433                        + adw->mcode_data->mcode_size;
  434         adw_outw(adw, ADW_RAM_ADDR, 0);
  435         while (byte_codes < byte_codes_end) {
  436                 if (*byte_codes == 0xFF) {
  437                         u_int16_t value;
  438 
  439                         value = byte_codes[2]
  440                               | byte_codes[3] << 8;
  441                         adw_set_multi_2(adw, ADW_RAM_DATA,
  442                                         value, byte_codes[1]);
  443                         bytes_downloaded += byte_codes[1];
  444                         byte_codes += 4;
  445                 } else if (*byte_codes == 0xFE) {
  446                         u_int16_t value;
  447 
  448                         value = byte_codes[1]
  449                               | byte_codes[2] << 8;
  450                         adw_outw(adw, ADW_RAM_DATA, value);
  451                         bytes_downloaded++;
  452                         byte_codes += 3;
  453                 } else {
  454                         adw_outw(adw, ADW_RAM_DATA, word_table[*byte_codes]);
  455                         bytes_downloaded++;
  456                         byte_codes++;
  457                 }
  458         }
  459         /* Convert from words to bytes */
  460         bytes_downloaded *= 2;
  461 
  462         /*
  463          * Clear the rest of LRAM.
  464          */
  465         for (addr = bytes_downloaded; addr < adw->memsize; addr += 2)
  466                 adw_outw(adw, ADW_RAM_DATA, 0);
  467 
  468         /*
  469          * Verify the microcode checksum.
  470          */
  471         checksum = 0;
  472         adw_outw(adw, ADW_RAM_ADDR, 0);
  473         for (addr = 0; addr < bytes_downloaded; addr += 2)
  474                 checksum += adw_inw(adw, ADW_RAM_DATA);
  475 
  476         if (checksum != adw->mcode_data->mcode_chksum) {
  477                 printf("%s: Firmware load failed!\n", adw_name(adw));
  478                 return (EIO);
  479         }
  480 
  481         /*
  482          * Restore the RISC memory BIOS region.
  483          */
  484         for (addr = 0; addr < ADW_MC_BIOSLEN; addr++)
  485                 adw_lram_write_8(adw, addr + ADW_MC_BIOSLEN, biosmem[addr]);
  486 
  487         /*
  488          * Calculate and write the microcode code checksum to
  489          * the microcode code checksum location.
  490          */
  491         addr = adw_lram_read_16(adw, ADW_MC_CODE_BEGIN_ADDR);
  492         end_addr = adw_lram_read_16(adw, ADW_MC_CODE_END_ADDR);
  493         checksum = 0;
  494         adw_outw(adw, ADW_RAM_ADDR, addr);
  495         for (; addr < end_addr; addr += 2)
  496                 checksum += adw_inw(adw, ADW_RAM_DATA);
  497         adw_lram_write_16(adw, ADW_MC_CODE_CHK_SUM, checksum);
  498 
  499         /*
  500          * Tell the microcode what kind of chip it's running on.
  501          */
  502         adw_lram_write_16(adw, ADW_MC_CHIP_TYPE, adw->chip);
  503 
  504         /*
  505          * Leave WDTR and SDTR negotiation disabled until the XPT has
  506          * informed us of device capabilities, but do set the desired
  507          * user rates in case we receive an SDTR request from the target
  508          * before we negotiate.  We turn on tagged queuing at the microcode
  509          * level for all devices, and modulate this on a per command basis.
  510          */
  511         adw_lram_write_16(adw, ADW_MC_SDTR_SPEED1, adw->user_sdtr[0]);
  512         adw_lram_write_16(adw, ADW_MC_SDTR_SPEED2, adw->user_sdtr[1]);
  513         adw_lram_write_16(adw, ADW_MC_SDTR_SPEED3, adw->user_sdtr[2]);
  514         adw_lram_write_16(adw, ADW_MC_SDTR_SPEED4, adw->user_sdtr[3]);
  515         adw_lram_write_16(adw, ADW_MC_DISC_ENABLE, adw->user_discenb);
  516         for (tid = 0; tid < ADW_MAX_TID; tid++) {
  517                 /* Cam limits the maximum number of commands for us */
  518                 adw_lram_write_8(adw, ADW_MC_NUMBER_OF_MAX_CMD + tid,
  519                                  adw->max_acbs);
  520         }
  521         adw_lram_write_16(adw, ADW_MC_TAGQNG_ABLE, ~0);
  522 
  523         /*
  524          * Set SCSI_CFG0 Microcode Default Value.
  525          *
  526          * The microcode will set the SCSI_CFG0 register using this value
  527          * after it is started.
  528          */
  529         adw_lram_write_16(adw, ADW_MC_DEFAULT_SCSI_CFG0,
  530                           ADW_SCSI_CFG0_PARITY_EN|ADW_SCSI_CFG0_SEL_TMO_LONG|
  531                           ADW_SCSI_CFG0_OUR_ID_EN|adw->initiator_id);
  532 
  533         /*
  534          * Tell the MC about the memory size that
  535          * was setup by the probe code.
  536          */
  537         adw_lram_write_16(adw, ADW_MC_DEFAULT_MEM_CFG,
  538                           adw_inb(adw, ADW_MEM_CFG) & ADW_MEM_CFG_RAM_SZ_MASK);
  539 
  540         /*
  541          * Determine SCSI_CFG1 Microcode Default Value.
  542          *
  543          * The microcode will set the SCSI_CFG1 register using this value
  544          * after it is started below.
  545          */
  546         scsicfg1 = adw_inw(adw, ADW_SCSI_CFG1);
  547 
  548         /*
  549          * If the internal narrow cable is reversed all of the SCSI_CTRL
  550          * register signals will be set. Check for and return an error if
  551          * this condition is found.
  552          */
  553         if ((adw_inw(adw, ADW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
  554                 printf("%s: Illegal Cable Config!\n", adw_name(adw));
  555                 printf("%s: Internal cable is reversed!\n", adw_name(adw));
  556                 return (EIO);
  557         }
  558 
  559         /*
  560          * If this is a differential board and a single-ended device
  561          * is attached to one of the connectors, return an error.
  562          */
  563         if ((adw->features & ADW_ULTRA) != 0)  {
  564                 if ((scsicfg1 & ADW_SCSI_CFG1_DIFF_MODE) != 0
  565                  && (scsicfg1 & ADW_SCSI_CFG1_DIFF_SENSE) == 0) {
  566                         printf("%s: A Single Ended Device is attached to our "
  567                                "differential bus!\n", adw_name(adw));
  568                         return (EIO);
  569                 }
  570         } else {
  571                 if ((scsicfg1 & ADW2_SCSI_CFG1_DEV_DETECT_HVD) != 0) {
  572                         printf("%s: A High Voltage Differential Device "
  573                                "is attached to this controller.\n",
  574                                adw_name(adw));
  575                         printf("%s: HVD devices are not supported.\n",
  576                                adw_name(adw));
  577                         return (EIO);
  578                 }
  579         }
  580 
  581         /*
  582          * Perform automatic termination control if desired.
  583          */
  584         if ((adw->features & ADW_ULTRA2) != 0) {
  585                 u_int cable_det;
  586 
  587                 /*
  588                  * Ultra2 Chips require termination disabled to
  589                  * detect cable presence.
  590                  */
  591                 adw_outw(adw, ADW_SCSI_CFG1,
  592                          scsicfg1 | ADW2_SCSI_CFG1_DIS_TERM_DRV);
  593                 cable_det = adw_inw(adw, ADW_SCSI_CFG1);
  594                 adw_outw(adw, ADW_SCSI_CFG1, scsicfg1);
  595 
  596                 /* SE Termination first if auto-term has been specified */
  597                 if ((term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) == 0) {
  598 
  599                         /*
  600                          * For all SE cable configurations, high byte
  601                          * termination is enabled.
  602                          */
  603                         term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H;
  604                         if ((cable_det & ADW_SCSI_CFG1_INT8_MASK) != 0
  605                          || (cable_det & ADW_SCSI_CFG1_INT16_MASK) != 0) {
  606                                 /*
  607                                  * If either cable is not present, the
  608                                  * low byte must be terminated as well.
  609                                  */
  610                                 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_L;
  611                         }
  612                 }
  613 
  614                 /* LVD auto-term */
  615                 if ((term_scsicfg1 & ADW2_SCSI_CFG1_TERM_CTL_LVD) == 0
  616                  && (term_scsicfg1 & ADW2_SCSI_CFG1_DIS_TERM_DRV) == 0) {
  617                         /*
  618                          * If both cables are installed, termination
  619                          * is disabled.  Otherwise it is enabled.
  620                          */
  621                         if ((cable_det & ADW2_SCSI_CFG1_EXTLVD_MASK) != 0
  622                          || (cable_det & ADW2_SCSI_CFG1_INTLVD_MASK) != 0) {
  623 
  624                                 term_scsicfg1 |= ADW2_SCSI_CFG1_TERM_CTL_LVD;
  625                         }
  626                 }
  627                 term_scsicfg1 &= ~ADW2_SCSI_CFG1_DIS_TERM_DRV;
  628         } else {
  629                 /* Ultra Controller Termination */
  630                 if ((term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) == 0) {
  631                         int cable_count;
  632                         int wide_cable_count;
  633 
  634                         cable_count = 0;
  635                         wide_cable_count = 0;
  636                         if ((scsicfg1 & ADW_SCSI_CFG1_INT16_MASK) == 0) {
  637                                 cable_count++;
  638                                 wide_cable_count++;
  639                         }
  640                         if ((scsicfg1 & ADW_SCSI_CFG1_INT8_MASK) == 0)
  641                                 cable_count++;
  642 
  643                         /* There is only one external port */
  644                         if ((scsicfg1 & ADW_SCSI_CFG1_EXT16_MASK) == 0) {
  645                                 cable_count++;
  646                                 wide_cable_count++;
  647                         } else if ((scsicfg1 & ADW_SCSI_CFG1_EXT8_MASK) == 0)
  648                                 cable_count++;
  649 
  650                         if (cable_count == 3) {
  651                                 printf("%s: Illegal Cable Config!\n",
  652                                        adw_name(adw));
  653                                 printf("%s: Only Two Ports may be used at "
  654                                        "a time!\n", adw_name(adw));
  655                         } else if (cable_count <= 1) {
  656                                 /*
  657                                  * At least two out of three cables missing.
  658                                  * Terminate both bytes.
  659                                  */
  660                                 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H
  661                                               |  ADW_SCSI_CFG1_TERM_CTL_L;
  662                         } else if (wide_cable_count <= 1) {
  663                                 /* No two 16bit cables present.  High on. */
  664                                 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H;
  665                         }
  666                 }
  667         }
  668 
  669         /* Tell the user about our decission */
  670         switch (term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) {
  671         case ADW_SCSI_CFG1_TERM_CTL_MASK:
  672                 printf("High & Low SE Term Enabled, ");
  673                 break;
  674         case ADW_SCSI_CFG1_TERM_CTL_H:
  675                 printf("High SE Termination Enabled, ");
  676                 break;
  677         case ADW_SCSI_CFG1_TERM_CTL_L:
  678                 printf("Low SE Term Enabled, ");
  679                 break;
  680         default:
  681                 break;
  682         }
  683 
  684         if ((adw->features & ADW_ULTRA2) != 0
  685          && (term_scsicfg1 & ADW2_SCSI_CFG1_TERM_CTL_LVD) != 0)
  686                 printf("LVD Term Enabled, ");
  687 
  688         /*
  689          * Invert the TERM_CTL_H and TERM_CTL_L bits and then
  690          * set 'scsicfg1'. The TERM_POL bit does not need to be
  691          * referenced, because the hardware internally inverts
  692          * the Termination High and Low bits if TERM_POL is set.
  693          */
  694         if ((adw->features & ADW_ULTRA2) != 0) {
  695                 term_scsicfg1 = ~term_scsicfg1;
  696                 term_scsicfg1 &= ADW_SCSI_CFG1_TERM_CTL_MASK
  697                               |  ADW2_SCSI_CFG1_TERM_CTL_LVD;
  698                 scsicfg1 &= ~(ADW_SCSI_CFG1_TERM_CTL_MASK
  699                              |ADW2_SCSI_CFG1_TERM_CTL_LVD
  700                              |ADW_SCSI_CFG1_BIG_ENDIAN
  701                              |ADW_SCSI_CFG1_TERM_POL
  702                              |ADW2_SCSI_CFG1_DEV_DETECT);
  703                 scsicfg1 |= term_scsicfg1;
  704         } else {
  705                 term_scsicfg1 = ~term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK;
  706                 scsicfg1 &= ~ADW_SCSI_CFG1_TERM_CTL_MASK;
  707                 scsicfg1 |= term_scsicfg1 | ADW_SCSI_CFG1_TERM_CTL_MANUAL;
  708                 scsicfg1 |= ADW_SCSI_CFG1_FLTR_DISABLE;
  709         }
  710 
  711         /*
  712          * Set SCSI_CFG1 Microcode Default Value
  713          *
  714          * The microcode will set the SCSI_CFG1 register using this value
  715          * after it is started below.
  716          */
  717         adw_lram_write_16(adw, ADW_MC_DEFAULT_SCSI_CFG1, scsicfg1);
  718 
  719         /*
  720          * Only accept selections on our initiator target id.
  721          * This may change in target mode scenarios...
  722          */
  723         adw_lram_write_16(adw, ADW_MC_DEFAULT_SEL_MASK,
  724                           (0x01 << adw->initiator_id));
  725 
  726         /*
  727          * Tell the microcode where it can find our
  728          * Initiator Command Queue (ICQ).  It is
  729          * currently empty hence the "stopper" address.
  730          */
  731         adw->commandq = adw->free_carriers;
  732         adw->free_carriers = carrierbotov(adw, adw->commandq->next_ba);
  733         adw->commandq->next_ba = ADW_CQ_STOPPER;
  734         adw_lram_write_32(adw, ADW_MC_ICQ, adw->commandq->carr_ba);
  735 
  736         /*
  737          * Tell the microcode where it can find our
  738          * Initiator Response Queue (IRQ).  It too
  739          * is currently empty.
  740          */
  741         adw->responseq = adw->free_carriers;
  742         adw->free_carriers = carrierbotov(adw, adw->responseq->next_ba);
  743         adw->responseq->next_ba = ADW_CQ_STOPPER;
  744         adw_lram_write_32(adw, ADW_MC_IRQ, adw->responseq->carr_ba);
  745 
  746         adw_outb(adw, ADW_INTR_ENABLES,
  747                  ADW_INTR_ENABLE_HOST_INTR|ADW_INTR_ENABLE_GLOBAL_INTR);
  748 
  749         adw_outw(adw, ADW_PC, adw_lram_read_16(adw, ADW_MC_CODE_BEGIN_ADDR));
  750 
  751         return (0);
  752 }
  753 
  754 void
  755 adw_set_user_sdtr(struct adw_softc *adw, u_int tid, u_int mc_sdtr)
  756 {
  757         adw->user_sdtr[ADW_TARGET_GROUP(tid)] &= ~ADW_TARGET_GROUP_MASK(tid);
  758         adw->user_sdtr[ADW_TARGET_GROUP(tid)] |=
  759             mc_sdtr << ADW_TARGET_GROUP_SHIFT(tid);
  760 }
  761 
  762 u_int
  763 adw_get_user_sdtr(struct adw_softc *adw, u_int tid)
  764 {
  765         u_int mc_sdtr;
  766 
  767         mc_sdtr = adw->user_sdtr[ADW_TARGET_GROUP(tid)];
  768         mc_sdtr &= ADW_TARGET_GROUP_MASK(tid);
  769         mc_sdtr >>= ADW_TARGET_GROUP_SHIFT(tid);
  770         return (mc_sdtr);
  771 }
  772 
  773 void
  774 adw_set_chip_sdtr(struct adw_softc *adw, u_int tid, u_int sdtr)
  775 {
  776         u_int mc_sdtr_offset;
  777         u_int mc_sdtr;
  778 
  779         mc_sdtr_offset = ADW_MC_SDTR_SPEED1;
  780         mc_sdtr_offset += ADW_TARGET_GROUP(tid) * 2;
  781         mc_sdtr = adw_lram_read_16(adw, mc_sdtr_offset);
  782         mc_sdtr &= ~ADW_TARGET_GROUP_MASK(tid);
  783         mc_sdtr |= sdtr << ADW_TARGET_GROUP_SHIFT(tid);
  784         adw_lram_write_16(adw, mc_sdtr_offset, mc_sdtr);
  785 }
  786 
  787 u_int
  788 adw_get_chip_sdtr(struct adw_softc *adw, u_int tid)
  789 {
  790         u_int mc_sdtr_offset;
  791         u_int mc_sdtr;
  792 
  793         mc_sdtr_offset = ADW_MC_SDTR_SPEED1;
  794         mc_sdtr_offset += ADW_TARGET_GROUP(tid) * 2;
  795         mc_sdtr = adw_lram_read_16(adw, mc_sdtr_offset);
  796         mc_sdtr &= ADW_TARGET_GROUP_MASK(tid);
  797         mc_sdtr >>= ADW_TARGET_GROUP_SHIFT(tid);
  798         return (mc_sdtr);
  799 }
  800 
  801 u_int
  802 adw_find_sdtr(struct adw_softc *adw, u_int period)
  803 {
  804         int i;
  805 
  806         i = 0;
  807         if ((adw->features & ADW_DT) == 0)
  808                 i = ADW_MC_SDTR_OFFSET_ULTRA2;
  809         if ((adw->features & ADW_ULTRA2) == 0)
  810                 i = ADW_MC_SDTR_OFFSET_ULTRA;
  811         if (period == 0)
  812                 return ADW_MC_SDTR_ASYNC;
  813 
  814         for (; i < adw_num_syncrates; i++) {
  815                 if (period <= adw_syncrates[i].period)
  816                         return (adw_syncrates[i].mc_sdtr);
  817         }       
  818         return ADW_MC_SDTR_ASYNC;
  819 }
  820 
  821 u_int
  822 adw_find_period(struct adw_softc *adw, u_int mc_sdtr)
  823 {
  824         int i;
  825 
  826         for (i = 0; i < adw_num_syncrates; i++) {
  827                 if (mc_sdtr == adw_syncrates[i].mc_sdtr)
  828                         break;
  829         }       
  830         return (adw_syncrates[i].period);
  831 }
  832 
  833 u_int
  834 adw_hshk_cfg_period_factor(u_int tinfo)
  835 {
  836         tinfo &= ADW_HSHK_CFG_RATE_MASK;
  837         tinfo >>= ADW_HSHK_CFG_RATE_SHIFT;
  838         if (tinfo == 0x11)
  839                 /* 80MHz/DT */
  840                 return (9);
  841         else if (tinfo == 0x10)
  842                 /* 40MHz */
  843                 return (10);
  844         else
  845                 return (((tinfo * 25) + 50) / 4);
  846 }
  847 
  848 /*
  849  * Send an idle command to the chip and wait for completion.
  850  */
  851 adw_idle_cmd_status_t
  852 adw_idle_cmd_send(struct adw_softc *adw, adw_idle_cmd_t cmd, u_int parameter)
  853 {
  854         u_int                 timeout;
  855         adw_idle_cmd_status_t status;
  856         int                   s;
  857 
  858         s = splcam();   
  859 
  860         /*
  861          * Clear the idle command status which is set by the microcode
  862          * to a non-zero value to indicate when the command is completed.
  863          */
  864         adw_lram_write_16(adw, ADW_MC_IDLE_CMD_STATUS, 0);
  865 
  866         /*
  867          * Write the idle command value after the idle command parameter
  868          * has been written to avoid a race condition. If the order is not
  869          * followed, the microcode may process the idle command before the
  870          * parameters have been written to LRAM.
  871          */
  872         adw_lram_write_32(adw, ADW_MC_IDLE_CMD_PARAMETER, parameter);
  873         adw_lram_write_16(adw, ADW_MC_IDLE_CMD, cmd);
  874 
  875         /*
  876          * Tickle the RISC to tell it to process the idle command.
  877          */
  878         adw_tickle_risc(adw, ADW_TICKLE_B);
  879 
  880         /* Wait for up to 10 seconds for the command to complete */
  881         timeout = 5000000;
  882         while (--timeout) {
  883                 status = adw_lram_read_16(adw, ADW_MC_IDLE_CMD_STATUS);
  884                 if (status != 0)
  885                         break;
  886                 DELAY(20);
  887         }
  888 
  889         if (timeout == 0)
  890                 panic("%s: Idle Command Timed Out!\n", adw_name(adw));
  891         splx(s);
  892         return (status);
  893 }

Cache object: be3919f9649bae0e9793217f22452f58


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