1 /*-
2 * Low level routines for Second Generation
3 * Advanced Systems Inc. SCSI controllers chips
4 *
5 * Copyright (c) 1998, 1999, 2000 Justin Gibbs.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 */
32 /*-
33 * Ported from:
34 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
35 *
36 * Copyright (c) 1995-1998 Advanced System Products, Inc.
37 * All Rights Reserved.
38 *
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that redistributions of source
41 * code retain the above copyright notice and this comment without
42 * modification.
43 */
44
45 #include <sys/cdefs.h>
46 __FBSDID("$FreeBSD: releng/5.4/sys/dev/advansys/adwlib.c 143007 2005-03-02 09:39:24Z obrien $");
47
48 #include <sys/param.h>
49 #include <sys/systm.h>
50 #include <sys/bus.h>
51
52 #include <machine/bus_pio.h>
53 #include <machine/bus_memio.h>
54 #include <machine/bus.h>
55
56 #include <cam/cam.h>
57 #include <cam/cam_ccb.h>
58 #include <cam/cam_sim.h>
59 #include <cam/cam_xpt_sim.h>
60 #include <cam/scsi/scsi_all.h>
61
62 #include <dev/advansys/adwlib.h>
63
64 const struct adw_eeprom adw_asc3550_default_eeprom =
65 {
66 ADW_EEPROM_BIOS_ENABLE, /* cfg_lsw */
67 0x0000, /* cfg_msw */
68 0xFFFF, /* disc_enable */
69 0xFFFF, /* wdtr_able */
70 { 0xFFFF }, /* sdtr_able */
71 0xFFFF, /* start_motor */
72 0xFFFF, /* tagqng_able */
73 0xFFFF, /* bios_scan */
74 0, /* scam_tolerant */
75 7, /* adapter_scsi_id */
76 0, /* bios_boot_delay */
77 3, /* scsi_reset_delay */
78 0, /* bios_id_lun */
79 0, /* termination */
80 0, /* reserved1 */
81 0xFFE7, /* bios_ctrl */
82 { 0xFFFF }, /* ultra_able */
83 { 0 }, /* reserved2 */
84 ADW_DEF_MAX_HOST_QNG, /* max_host_qng */
85 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */
86 0, /* dvc_cntl */
87 { 0 }, /* bug_fix */
88 { 0, 0, 0 }, /* serial_number */
89 0, /* check_sum */
90 { /* oem_name[16] */
91 0, 0, 0, 0, 0, 0, 0, 0,
92 0, 0, 0, 0, 0, 0, 0, 0
93 },
94 0, /* dvc_err_code */
95 0, /* adv_err_code */
96 0, /* adv_err_addr */
97 0, /* saved_dvc_err_code */
98 0, /* saved_adv_err_code */
99 0 /* saved_adv_err_addr */
100 };
101
102 const struct adw_eeprom adw_asc38C0800_default_eeprom =
103 {
104 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
105 0x0000, /* 01 cfg_msw */
106 0xFFFF, /* 02 disc_enable */
107 0xFFFF, /* 03 wdtr_able */
108 { 0x4444 }, /* 04 sdtr_speed1 */
109 0xFFFF, /* 05 start_motor */
110 0xFFFF, /* 06 tagqng_able */
111 0xFFFF, /* 07 bios_scan */
112 0, /* 08 scam_tolerant */
113 7, /* 09 adapter_scsi_id */
114 0, /* bios_boot_delay */
115 3, /* 10 scsi_reset_delay */
116 0, /* bios_id_lun */
117 0, /* 11 termination_se */
118 0, /* termination_lvd */
119 0xFFE7, /* 12 bios_ctrl */
120 { 0x4444 }, /* 13 sdtr_speed2 */
121 { 0x4444 }, /* 14 sdtr_speed3 */
122 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
123 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */
124 0, /* 16 dvc_cntl */
125 { 0x4444 } , /* 17 sdtr_speed4 */
126 { 0, 0, 0 }, /* 18-20 serial_number */
127 0, /* 21 check_sum */
128 { /* 22-29 oem_name[16] */
129 0, 0, 0, 0, 0, 0, 0, 0,
130 0, 0, 0, 0, 0, 0, 0, 0
131 },
132 0, /* 30 dvc_err_code */
133 0, /* 31 adv_err_code */
134 0, /* 32 adv_err_addr */
135 0, /* 33 saved_dvc_err_code */
136 0, /* 34 saved_adv_err_code */
137 0, /* 35 saved_adv_err_addr */
138 { /* 36 - 55 reserved */
139 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
140 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
141 },
142 0, /* 56 cisptr_lsw */
143 0, /* 57 cisprt_msw */
144 /* 58-59 sub-id */
145 (PCI_ID_ADVANSYS_38C0800_REV1 & PCI_ID_DEV_VENDOR_MASK) >> 32,
146 };
147
148 #define ADW_MC_SDTR_OFFSET_ULTRA2_DT 0
149 #define ADW_MC_SDTR_OFFSET_ULTRA2 1
150 #define ADW_MC_SDTR_OFFSET_ULTRA 2
151 const struct adw_syncrate adw_syncrates[] =
152 {
153 /* mc_sdtr period rate */
154 { ADW_MC_SDTR_80, 9, "80.0" },
155 { ADW_MC_SDTR_40, 10, "40.0" },
156 { ADW_MC_SDTR_20, 12, "20.0" },
157 { ADW_MC_SDTR_10, 25, "10.0" },
158 { ADW_MC_SDTR_5, 50, "5.0" },
159 { ADW_MC_SDTR_ASYNC, 0, "async" }
160 };
161
162 const int adw_num_syncrates = sizeof(adw_syncrates) / sizeof(adw_syncrates[0]);
163
164 static u_int16_t adw_eeprom_read_16(struct adw_softc *adw, int addr);
165 static void adw_eeprom_write_16(struct adw_softc *adw, int addr,
166 u_int data);
167 static void adw_eeprom_wait(struct adw_softc *adw);
168
169 int
170 adw_find_signature(struct adw_softc *adw)
171 {
172 if (adw_inb(adw, ADW_SIGNATURE_BYTE) == ADW_CHIP_ID_BYTE
173 && adw_inw(adw, ADW_SIGNATURE_WORD) == ADW_CHIP_ID_WORD)
174 return (1);
175 return (0);
176 }
177
178 /*
179 * Reset Chip.
180 */
181 void
182 adw_reset_chip(struct adw_softc *adw)
183 {
184 adw_outw(adw, ADW_CTRL_REG, ADW_CTRL_REG_CMD_RESET);
185 DELAY(1000 * 100);
186 adw_outw(adw, ADW_CTRL_REG, ADW_CTRL_REG_CMD_WR_IO_REG);
187
188 /*
189 * Initialize Chip registers.
190 */
191 adw_outw(adw, ADW_SCSI_CFG1,
192 adw_inw(adw, ADW_SCSI_CFG1) & ~ADW_SCSI_CFG1_BIG_ENDIAN);
193 }
194
195 /*
196 * Reset the SCSI bus.
197 */
198 int
199 adw_reset_bus(struct adw_softc *adw)
200 {
201 adw_idle_cmd_status_t status;
202
203 status =
204 adw_idle_cmd_send(adw, ADW_IDLE_CMD_SCSI_RESET_START, /*param*/0);
205 if (status != ADW_IDLE_CMD_SUCCESS) {
206 xpt_print_path(adw->path);
207 printf("Bus Reset start attempt failed\n");
208 return (1);
209 }
210 DELAY(ADW_BUS_RESET_HOLD_DELAY_US);
211 status =
212 adw_idle_cmd_send(adw, ADW_IDLE_CMD_SCSI_RESET_END, /*param*/0);
213 if (status != ADW_IDLE_CMD_SUCCESS) {
214 xpt_print_path(adw->path);
215 printf("Bus Reset end attempt failed\n");
216 return (1);
217 }
218 return (0);
219 }
220
221 /*
222 * Read the specified EEPROM location
223 */
224 static u_int16_t
225 adw_eeprom_read_16(struct adw_softc *adw, int addr)
226 {
227 adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_READ | addr);
228 adw_eeprom_wait(adw);
229 return (adw_inw(adw, ADW_EEP_DATA));
230 }
231
232 static void
233 adw_eeprom_write_16(struct adw_softc *adw, int addr, u_int data)
234 {
235 adw_outw(adw, ADW_EEP_DATA, data);
236 adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE | addr);
237 adw_eeprom_wait(adw);
238 }
239
240 /*
241 * Wait for and EEPROM command to complete
242 */
243 static void
244 adw_eeprom_wait(struct adw_softc *adw)
245 {
246 int i;
247
248 for (i = 0; i < ADW_EEP_DELAY_MS; i++) {
249 if ((adw_inw(adw, ADW_EEP_CMD) & ADW_EEP_CMD_DONE) != 0)
250 break;
251 DELAY(1000);
252 }
253 if (i == ADW_EEP_DELAY_MS)
254 panic("%s: Timedout Reading EEPROM", adw_name(adw));
255 }
256
257 /*
258 * Read EEPROM configuration into the specified buffer.
259 *
260 * Return a checksum based on the EEPROM configuration read.
261 */
262 u_int16_t
263 adw_eeprom_read(struct adw_softc *adw, struct adw_eeprom *eep_buf)
264 {
265 u_int16_t *wbuf;
266 u_int16_t wval;
267 u_int16_t chksum;
268 int eep_addr;
269
270 wbuf = (u_int16_t *)eep_buf;
271 chksum = 0;
272
273 for (eep_addr = ADW_EEP_DVC_CFG_BEGIN;
274 eep_addr < ADW_EEP_DVC_CFG_END;
275 eep_addr++, wbuf++) {
276 wval = adw_eeprom_read_16(adw, eep_addr);
277 chksum += wval;
278 *wbuf = wval;
279 }
280
281 /* checksum field is not counted in the checksum */
282 *wbuf = adw_eeprom_read_16(adw, eep_addr);
283 wbuf++;
284
285 /* Driver seeprom variables are not included in the checksum */
286 for (eep_addr = ADW_EEP_DVC_CTL_BEGIN;
287 eep_addr < ADW_EEP_MAX_WORD_ADDR;
288 eep_addr++, wbuf++)
289 *wbuf = adw_eeprom_read_16(adw, eep_addr);
290
291 return (chksum);
292 }
293
294 void
295 adw_eeprom_write(struct adw_softc *adw, struct adw_eeprom *eep_buf)
296 {
297 u_int16_t *wbuf;
298 u_int16_t addr;
299 u_int16_t chksum;
300
301 wbuf = (u_int16_t *)eep_buf;
302 chksum = 0;
303
304 adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE_ABLE);
305 adw_eeprom_wait(adw);
306
307 /*
308 * Write EEPROM until checksum.
309 */
310 for (addr = ADW_EEP_DVC_CFG_BEGIN;
311 addr < ADW_EEP_DVC_CFG_END; addr++, wbuf++) {
312 chksum += *wbuf;
313 adw_eeprom_write_16(adw, addr, *wbuf);
314 }
315
316 /*
317 * Write calculated EEPROM checksum
318 */
319 adw_eeprom_write_16(adw, addr, chksum);
320
321 /* skip over buffer's checksum */
322 wbuf++;
323
324 /*
325 * Write the rest.
326 */
327 for (addr = ADW_EEP_DVC_CTL_BEGIN;
328 addr < ADW_EEP_MAX_WORD_ADDR; addr++, wbuf++)
329 adw_eeprom_write_16(adw, addr, *wbuf);
330
331 adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE_DISABLE);
332 adw_eeprom_wait(adw);
333 }
334
335 int
336 adw_init_chip(struct adw_softc *adw, u_int term_scsicfg1)
337 {
338 u_int8_t biosmem[ADW_MC_BIOSLEN];
339 const u_int16_t *word_table;
340 const u_int8_t *byte_codes;
341 const u_int8_t *byte_codes_end;
342 u_int bios_sig;
343 u_int bytes_downloaded;
344 u_int addr;
345 u_int end_addr;
346 u_int checksum;
347 u_int scsicfg1;
348 u_int tid;
349
350 /*
351 * Save the RISC memory BIOS region before writing the microcode.
352 * The BIOS may already be loaded and using its RISC LRAM region
353 * so its region must be saved and restored.
354 */
355 for (addr = 0; addr < ADW_MC_BIOSLEN; addr++)
356 biosmem[addr] = adw_lram_read_8(adw, ADW_MC_BIOSMEM + addr);
357
358 /*
359 * Save current per TID negotiated values if the BIOS has been
360 * loaded (BIOS signature is present). These will be used if
361 * we cannot get information from the EEPROM.
362 */
363 addr = ADW_MC_BIOS_SIGNATURE - ADW_MC_BIOSMEM;
364 bios_sig = biosmem[addr]
365 | (biosmem[addr + 1] << 8);
366 if (bios_sig == 0x55AA
367 && (adw->flags & ADW_EEPROM_FAILED) != 0) {
368 u_int major_ver;
369 u_int minor_ver;
370 u_int sdtr_able;
371
372 addr = ADW_MC_BIOS_VERSION - ADW_MC_BIOSMEM;
373 minor_ver = biosmem[addr + 1] & 0xF;
374 major_ver = (biosmem[addr + 1] >> 4) & 0xF;
375 if ((adw->chip == ADW_CHIP_ASC3550)
376 && (major_ver <= 3
377 || (major_ver == 3 && minor_ver <= 1))) {
378 /*
379 * BIOS 3.1 and earlier location of
380 * 'wdtr_able' variable.
381 */
382 adw->user_wdtr =
383 adw_lram_read_16(adw, ADW_MC_WDTR_ABLE_BIOS_31);
384 } else {
385 adw->user_wdtr =
386 adw_lram_read_16(adw, ADW_MC_WDTR_ABLE);
387 }
388 sdtr_able = adw_lram_read_16(adw, ADW_MC_SDTR_ABLE);
389 for (tid = 0; tid < ADW_MAX_TID; tid++) {
390 u_int tid_mask;
391 u_int mc_sdtr;
392
393 tid_mask = 0x1 << tid;
394 if ((sdtr_able & tid_mask) == 0)
395 mc_sdtr = ADW_MC_SDTR_ASYNC;
396 else if ((adw->features & ADW_DT) != 0)
397 mc_sdtr = ADW_MC_SDTR_80;
398 else if ((adw->features & ADW_ULTRA2) != 0)
399 mc_sdtr = ADW_MC_SDTR_40;
400 else
401 mc_sdtr = ADW_MC_SDTR_20;
402 adw_set_user_sdtr(adw, tid, mc_sdtr);
403 }
404 adw->user_tagenb = adw_lram_read_16(adw, ADW_MC_TAGQNG_ABLE);
405 }
406
407 /*
408 * Load the Microcode.
409 *
410 * Assume the following compressed format of the microcode buffer:
411 *
412 * 253 word (506 byte) table indexed by byte code followed
413 * by the following byte codes:
414 *
415 * 1-Byte Code:
416 * 00: Emit word 0 in table.
417 * 01: Emit word 1 in table.
418 * .
419 * FD: Emit word 253 in table.
420 *
421 * Multi-Byte Code:
422 * FD RESEVED
423 *
424 * FE WW WW: (3 byte code)
425 * Word to emit is the next word WW WW.
426 * FF BB WW WW: (4 byte code)
427 * Emit BB count times next word WW WW.
428 *
429 */
430 bytes_downloaded = 0;
431 word_table = (const u_int16_t *)adw->mcode_data->mcode_buf;
432 byte_codes = (const u_int8_t *)&word_table[253];
433 byte_codes_end = adw->mcode_data->mcode_buf
434 + adw->mcode_data->mcode_size;
435 adw_outw(adw, ADW_RAM_ADDR, 0);
436 while (byte_codes < byte_codes_end) {
437 if (*byte_codes == 0xFF) {
438 u_int16_t value;
439
440 value = byte_codes[2]
441 | byte_codes[3] << 8;
442 adw_set_multi_2(adw, ADW_RAM_DATA,
443 value, byte_codes[1]);
444 bytes_downloaded += byte_codes[1];
445 byte_codes += 4;
446 } else if (*byte_codes == 0xFE) {
447 u_int16_t value;
448
449 value = byte_codes[1]
450 | byte_codes[2] << 8;
451 adw_outw(adw, ADW_RAM_DATA, value);
452 bytes_downloaded++;
453 byte_codes += 3;
454 } else {
455 adw_outw(adw, ADW_RAM_DATA, word_table[*byte_codes]);
456 bytes_downloaded++;
457 byte_codes++;
458 }
459 }
460 /* Convert from words to bytes */
461 bytes_downloaded *= 2;
462
463 /*
464 * Clear the rest of LRAM.
465 */
466 for (addr = bytes_downloaded; addr < adw->memsize; addr += 2)
467 adw_outw(adw, ADW_RAM_DATA, 0);
468
469 /*
470 * Verify the microcode checksum.
471 */
472 checksum = 0;
473 adw_outw(adw, ADW_RAM_ADDR, 0);
474 for (addr = 0; addr < bytes_downloaded; addr += 2)
475 checksum += adw_inw(adw, ADW_RAM_DATA);
476
477 if (checksum != adw->mcode_data->mcode_chksum) {
478 printf("%s: Firmware load failed!\n", adw_name(adw));
479 return (EIO);
480 }
481
482 /*
483 * Restore the RISC memory BIOS region.
484 */
485 for (addr = 0; addr < ADW_MC_BIOSLEN; addr++)
486 adw_lram_write_8(adw, addr + ADW_MC_BIOSLEN, biosmem[addr]);
487
488 /*
489 * Calculate and write the microcode code checksum to
490 * the microcode code checksum location.
491 */
492 addr = adw_lram_read_16(adw, ADW_MC_CODE_BEGIN_ADDR);
493 end_addr = adw_lram_read_16(adw, ADW_MC_CODE_END_ADDR);
494 checksum = 0;
495 adw_outw(adw, ADW_RAM_ADDR, addr);
496 for (; addr < end_addr; addr += 2)
497 checksum += adw_inw(adw, ADW_RAM_DATA);
498 adw_lram_write_16(adw, ADW_MC_CODE_CHK_SUM, checksum);
499
500 /*
501 * Tell the microcode what kind of chip it's running on.
502 */
503 adw_lram_write_16(adw, ADW_MC_CHIP_TYPE, adw->chip);
504
505 /*
506 * Leave WDTR and SDTR negotiation disabled until the XPT has
507 * informed us of device capabilities, but do set the desired
508 * user rates in case we receive an SDTR request from the target
509 * before we negotiate. We turn on tagged queuing at the microcode
510 * level for all devices, and modulate this on a per command basis.
511 */
512 adw_lram_write_16(adw, ADW_MC_SDTR_SPEED1, adw->user_sdtr[0]);
513 adw_lram_write_16(adw, ADW_MC_SDTR_SPEED2, adw->user_sdtr[1]);
514 adw_lram_write_16(adw, ADW_MC_SDTR_SPEED3, adw->user_sdtr[2]);
515 adw_lram_write_16(adw, ADW_MC_SDTR_SPEED4, adw->user_sdtr[3]);
516 adw_lram_write_16(adw, ADW_MC_DISC_ENABLE, adw->user_discenb);
517 for (tid = 0; tid < ADW_MAX_TID; tid++) {
518 /* Cam limits the maximum number of commands for us */
519 adw_lram_write_8(adw, ADW_MC_NUMBER_OF_MAX_CMD + tid,
520 adw->max_acbs);
521 }
522 adw_lram_write_16(adw, ADW_MC_TAGQNG_ABLE, ~0);
523
524 /*
525 * Set SCSI_CFG0 Microcode Default Value.
526 *
527 * The microcode will set the SCSI_CFG0 register using this value
528 * after it is started.
529 */
530 adw_lram_write_16(adw, ADW_MC_DEFAULT_SCSI_CFG0,
531 ADW_SCSI_CFG0_PARITY_EN|ADW_SCSI_CFG0_SEL_TMO_LONG|
532 ADW_SCSI_CFG0_OUR_ID_EN|adw->initiator_id);
533
534 /*
535 * Tell the MC about the memory size that
536 * was setup by the probe code.
537 */
538 adw_lram_write_16(adw, ADW_MC_DEFAULT_MEM_CFG,
539 adw_inb(adw, ADW_MEM_CFG) & ADW_MEM_CFG_RAM_SZ_MASK);
540
541 /*
542 * Determine SCSI_CFG1 Microcode Default Value.
543 *
544 * The microcode will set the SCSI_CFG1 register using this value
545 * after it is started below.
546 */
547 scsicfg1 = adw_inw(adw, ADW_SCSI_CFG1);
548
549 /*
550 * If the internal narrow cable is reversed all of the SCSI_CTRL
551 * register signals will be set. Check for and return an error if
552 * this condition is found.
553 */
554 if ((adw_inw(adw, ADW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
555 printf("%s: Illegal Cable Config!\n", adw_name(adw));
556 printf("%s: Internal cable is reversed!\n", adw_name(adw));
557 return (EIO);
558 }
559
560 /*
561 * If this is a differential board and a single-ended device
562 * is attached to one of the connectors, return an error.
563 */
564 if ((adw->features & ADW_ULTRA) != 0) {
565 if ((scsicfg1 & ADW_SCSI_CFG1_DIFF_MODE) != 0
566 && (scsicfg1 & ADW_SCSI_CFG1_DIFF_SENSE) == 0) {
567 printf("%s: A Single Ended Device is attached to our "
568 "differential bus!\n", adw_name(adw));
569 return (EIO);
570 }
571 } else {
572 if ((scsicfg1 & ADW2_SCSI_CFG1_DEV_DETECT_HVD) != 0) {
573 printf("%s: A High Voltage Differential Device "
574 "is attached to this controller.\n",
575 adw_name(adw));
576 printf("%s: HVD devices are not supported.\n",
577 adw_name(adw));
578 return (EIO);
579 }
580 }
581
582 /*
583 * Perform automatic termination control if desired.
584 */
585 if ((adw->features & ADW_ULTRA2) != 0) {
586 u_int cable_det;
587
588 /*
589 * Ultra2 Chips require termination disabled to
590 * detect cable presence.
591 */
592 adw_outw(adw, ADW_SCSI_CFG1,
593 scsicfg1 | ADW2_SCSI_CFG1_DIS_TERM_DRV);
594 cable_det = adw_inw(adw, ADW_SCSI_CFG1);
595 adw_outw(adw, ADW_SCSI_CFG1, scsicfg1);
596
597 /* SE Termination first if auto-term has been specified */
598 if ((term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) == 0) {
599
600 /*
601 * For all SE cable configurations, high byte
602 * termination is enabled.
603 */
604 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H;
605 if ((cable_det & ADW_SCSI_CFG1_INT8_MASK) != 0
606 || (cable_det & ADW_SCSI_CFG1_INT16_MASK) != 0) {
607 /*
608 * If either cable is not present, the
609 * low byte must be terminated as well.
610 */
611 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_L;
612 }
613 }
614
615 /* LVD auto-term */
616 if ((term_scsicfg1 & ADW2_SCSI_CFG1_TERM_CTL_LVD) == 0
617 && (term_scsicfg1 & ADW2_SCSI_CFG1_DIS_TERM_DRV) == 0) {
618 /*
619 * If both cables are installed, termination
620 * is disabled. Otherwise it is enabled.
621 */
622 if ((cable_det & ADW2_SCSI_CFG1_EXTLVD_MASK) != 0
623 || (cable_det & ADW2_SCSI_CFG1_INTLVD_MASK) != 0) {
624
625 term_scsicfg1 |= ADW2_SCSI_CFG1_TERM_CTL_LVD;
626 }
627 }
628 term_scsicfg1 &= ~ADW2_SCSI_CFG1_DIS_TERM_DRV;
629 } else {
630 /* Ultra Controller Termination */
631 if ((term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) == 0) {
632 int cable_count;
633 int wide_cable_count;
634
635 cable_count = 0;
636 wide_cable_count = 0;
637 if ((scsicfg1 & ADW_SCSI_CFG1_INT16_MASK) == 0) {
638 cable_count++;
639 wide_cable_count++;
640 }
641 if ((scsicfg1 & ADW_SCSI_CFG1_INT8_MASK) == 0)
642 cable_count++;
643
644 /* There is only one external port */
645 if ((scsicfg1 & ADW_SCSI_CFG1_EXT16_MASK) == 0) {
646 cable_count++;
647 wide_cable_count++;
648 } else if ((scsicfg1 & ADW_SCSI_CFG1_EXT8_MASK) == 0)
649 cable_count++;
650
651 if (cable_count == 3) {
652 printf("%s: Illegal Cable Config!\n",
653 adw_name(adw));
654 printf("%s: Only Two Ports may be used at "
655 "a time!\n", adw_name(adw));
656 } else if (cable_count <= 1) {
657 /*
658 * At least two out of three cables missing.
659 * Terminate both bytes.
660 */
661 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H
662 | ADW_SCSI_CFG1_TERM_CTL_L;
663 } else if (wide_cable_count <= 1) {
664 /* No two 16bit cables present. High on. */
665 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H;
666 }
667 }
668 }
669
670 /* Tell the user about our decission */
671 switch (term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) {
672 case ADW_SCSI_CFG1_TERM_CTL_MASK:
673 printf("High & Low SE Term Enabled, ");
674 break;
675 case ADW_SCSI_CFG1_TERM_CTL_H:
676 printf("High SE Termination Enabled, ");
677 break;
678 case ADW_SCSI_CFG1_TERM_CTL_L:
679 printf("Low SE Term Enabled, ");
680 break;
681 default:
682 break;
683 }
684
685 if ((adw->features & ADW_ULTRA2) != 0
686 && (term_scsicfg1 & ADW2_SCSI_CFG1_TERM_CTL_LVD) != 0)
687 printf("LVD Term Enabled, ");
688
689 /*
690 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
691 * set 'scsicfg1'. The TERM_POL bit does not need to be
692 * referenced, because the hardware internally inverts
693 * the Termination High and Low bits if TERM_POL is set.
694 */
695 if ((adw->features & ADW_ULTRA2) != 0) {
696 term_scsicfg1 = ~term_scsicfg1;
697 term_scsicfg1 &= ADW_SCSI_CFG1_TERM_CTL_MASK
698 | ADW2_SCSI_CFG1_TERM_CTL_LVD;
699 scsicfg1 &= ~(ADW_SCSI_CFG1_TERM_CTL_MASK
700 |ADW2_SCSI_CFG1_TERM_CTL_LVD
701 |ADW_SCSI_CFG1_BIG_ENDIAN
702 |ADW_SCSI_CFG1_TERM_POL
703 |ADW2_SCSI_CFG1_DEV_DETECT);
704 scsicfg1 |= term_scsicfg1;
705 } else {
706 term_scsicfg1 = ~term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK;
707 scsicfg1 &= ~ADW_SCSI_CFG1_TERM_CTL_MASK;
708 scsicfg1 |= term_scsicfg1 | ADW_SCSI_CFG1_TERM_CTL_MANUAL;
709 scsicfg1 |= ADW_SCSI_CFG1_FLTR_DISABLE;
710 }
711
712 /*
713 * Set SCSI_CFG1 Microcode Default Value
714 *
715 * The microcode will set the SCSI_CFG1 register using this value
716 * after it is started below.
717 */
718 adw_lram_write_16(adw, ADW_MC_DEFAULT_SCSI_CFG1, scsicfg1);
719
720 /*
721 * Only accept selections on our initiator target id.
722 * This may change in target mode scenarios...
723 */
724 adw_lram_write_16(adw, ADW_MC_DEFAULT_SEL_MASK,
725 (0x01 << adw->initiator_id));
726
727 /*
728 * Tell the microcode where it can find our
729 * Initiator Command Queue (ICQ). It is
730 * currently empty hence the "stopper" address.
731 */
732 adw->commandq = adw->free_carriers;
733 adw->free_carriers = carrierbotov(adw, adw->commandq->next_ba);
734 adw->commandq->next_ba = ADW_CQ_STOPPER;
735 adw_lram_write_32(adw, ADW_MC_ICQ, adw->commandq->carr_ba);
736
737 /*
738 * Tell the microcode where it can find our
739 * Initiator Response Queue (IRQ). It too
740 * is currently empty.
741 */
742 adw->responseq = adw->free_carriers;
743 adw->free_carriers = carrierbotov(adw, adw->responseq->next_ba);
744 adw->responseq->next_ba = ADW_CQ_STOPPER;
745 adw_lram_write_32(adw, ADW_MC_IRQ, adw->responseq->carr_ba);
746
747 adw_outb(adw, ADW_INTR_ENABLES,
748 ADW_INTR_ENABLE_HOST_INTR|ADW_INTR_ENABLE_GLOBAL_INTR);
749
750 adw_outw(adw, ADW_PC, adw_lram_read_16(adw, ADW_MC_CODE_BEGIN_ADDR));
751
752 return (0);
753 }
754
755 void
756 adw_set_user_sdtr(struct adw_softc *adw, u_int tid, u_int mc_sdtr)
757 {
758 adw->user_sdtr[ADW_TARGET_GROUP(tid)] &= ~ADW_TARGET_GROUP_MASK(tid);
759 adw->user_sdtr[ADW_TARGET_GROUP(tid)] |=
760 mc_sdtr << ADW_TARGET_GROUP_SHIFT(tid);
761 }
762
763 u_int
764 adw_get_user_sdtr(struct adw_softc *adw, u_int tid)
765 {
766 u_int mc_sdtr;
767
768 mc_sdtr = adw->user_sdtr[ADW_TARGET_GROUP(tid)];
769 mc_sdtr &= ADW_TARGET_GROUP_MASK(tid);
770 mc_sdtr >>= ADW_TARGET_GROUP_SHIFT(tid);
771 return (mc_sdtr);
772 }
773
774 void
775 adw_set_chip_sdtr(struct adw_softc *adw, u_int tid, u_int sdtr)
776 {
777 u_int mc_sdtr_offset;
778 u_int mc_sdtr;
779
780 mc_sdtr_offset = ADW_MC_SDTR_SPEED1;
781 mc_sdtr_offset += ADW_TARGET_GROUP(tid) * 2;
782 mc_sdtr = adw_lram_read_16(adw, mc_sdtr_offset);
783 mc_sdtr &= ~ADW_TARGET_GROUP_MASK(tid);
784 mc_sdtr |= sdtr << ADW_TARGET_GROUP_SHIFT(tid);
785 adw_lram_write_16(adw, mc_sdtr_offset, mc_sdtr);
786 }
787
788 u_int
789 adw_get_chip_sdtr(struct adw_softc *adw, u_int tid)
790 {
791 u_int mc_sdtr_offset;
792 u_int mc_sdtr;
793
794 mc_sdtr_offset = ADW_MC_SDTR_SPEED1;
795 mc_sdtr_offset += ADW_TARGET_GROUP(tid) * 2;
796 mc_sdtr = adw_lram_read_16(adw, mc_sdtr_offset);
797 mc_sdtr &= ADW_TARGET_GROUP_MASK(tid);
798 mc_sdtr >>= ADW_TARGET_GROUP_SHIFT(tid);
799 return (mc_sdtr);
800 }
801
802 u_int
803 adw_find_sdtr(struct adw_softc *adw, u_int period)
804 {
805 int i;
806
807 i = 0;
808 if ((adw->features & ADW_DT) == 0)
809 i = ADW_MC_SDTR_OFFSET_ULTRA2;
810 if ((adw->features & ADW_ULTRA2) == 0)
811 i = ADW_MC_SDTR_OFFSET_ULTRA;
812 if (period == 0)
813 return ADW_MC_SDTR_ASYNC;
814
815 for (; i < adw_num_syncrates; i++) {
816 if (period <= adw_syncrates[i].period)
817 return (adw_syncrates[i].mc_sdtr);
818 }
819 return ADW_MC_SDTR_ASYNC;
820 }
821
822 u_int
823 adw_find_period(struct adw_softc *adw, u_int mc_sdtr)
824 {
825 int i;
826
827 for (i = 0; i < adw_num_syncrates; i++) {
828 if (mc_sdtr == adw_syncrates[i].mc_sdtr)
829 break;
830 }
831 return (adw_syncrates[i].period);
832 }
833
834 u_int
835 adw_hshk_cfg_period_factor(u_int tinfo)
836 {
837 tinfo &= ADW_HSHK_CFG_RATE_MASK;
838 tinfo >>= ADW_HSHK_CFG_RATE_SHIFT;
839 if (tinfo == 0x11)
840 /* 80MHz/DT */
841 return (9);
842 else if (tinfo == 0x10)
843 /* 40MHz */
844 return (10);
845 else
846 return (((tinfo * 25) + 50) / 4);
847 }
848
849 /*
850 * Send an idle command to the chip and wait for completion.
851 */
852 adw_idle_cmd_status_t
853 adw_idle_cmd_send(struct adw_softc *adw, adw_idle_cmd_t cmd, u_int parameter)
854 {
855 u_int timeout;
856 adw_idle_cmd_status_t status;
857 int s;
858
859 s = splcam();
860
861 /*
862 * Clear the idle command status which is set by the microcode
863 * to a non-zero value to indicate when the command is completed.
864 */
865 adw_lram_write_16(adw, ADW_MC_IDLE_CMD_STATUS, 0);
866
867 /*
868 * Write the idle command value after the idle command parameter
869 * has been written to avoid a race condition. If the order is not
870 * followed, the microcode may process the idle command before the
871 * parameters have been written to LRAM.
872 */
873 adw_lram_write_32(adw, ADW_MC_IDLE_CMD_PARAMETER, parameter);
874 adw_lram_write_16(adw, ADW_MC_IDLE_CMD, cmd);
875
876 /*
877 * Tickle the RISC to tell it to process the idle command.
878 */
879 adw_tickle_risc(adw, ADW_TICKLE_B);
880
881 /* Wait for up to 10 seconds for the command to complete */
882 timeout = 5000000;
883 while (--timeout) {
884 status = adw_lram_read_16(adw, ADW_MC_IDLE_CMD_STATUS);
885 if (status != 0)
886 break;
887 DELAY(20);
888 }
889
890 if (timeout == 0)
891 panic("%s: Idle Command Timed Out!\n", adw_name(adw));
892 splx(s);
893 return (status);
894 }
Cache object: acd14e96d675a93cb3b3ca71fab55b62
|