The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/advansys/adwlib.h

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    1 /*
    2  * Definitions for low level routines and data structures
    3  * for the Advanced Systems Inc. SCSI controllers chips.
    4  *
    5  * Copyright (c) 1998, 1999, 2000 Justin T. Gibbs.
    6  * All rights reserved.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions, and the following disclaimer,
   13  *    without modification.
   14  * 2. Redistributions in binary form must reproduce the above copyright
   15  *    notice, this list of conditions and the following disclaimer in the
   16  *    documentation and/or other materials provided with the distribution.
   17  * 3. The name of the author may not be used to endorse or promote products
   18  *    derived from this software without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
   24  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   30  * SUCH DAMAGE.
   31  *
   32  * $FreeBSD: stable/4/sys/dev/advansys/adwlib.h 57679 2000-03-02 00:08:35Z gibbs $
   33  */
   34 /*
   35  * Ported from:
   36  * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
   37  *     
   38  * Copyright (c) 1995-1998 Advanced System Products, Inc.
   39  * All Rights Reserved.
   40  *   
   41  * Redistribution and use in source and binary forms, with or without
   42  * modification, are permitted provided that redistributions of source
   43  * code retain the above copyright notice and this comment without
   44  * modification.
   45  */
   46 
   47 #ifndef _ADWLIB_H_
   48 #define _ADWLIB_H_
   49 
   50 #include "opt_adw.h"
   51 
   52 #include <stddef.h>     /* for offsetof */
   53 
   54 #include <dev/advansys/adwmcode.h>
   55 
   56 #define ADW_DEF_MAX_HOST_QNG    253
   57 #define ADW_DEF_MIN_HOST_QNG    16
   58 #define ADW_DEF_MAX_DVC_QNG     63
   59 #define ADW_DEF_MIN_DVC_QNG     4
   60 
   61 #define ADW_MAX_TID             15
   62 #define ADW_MAX_LUN             7
   63 
   64 #define ADW_ALL_TARGETS         0xFFFF
   65 
   66 #define ADW_TARGET_GROUP(tid)           ((tid) & ~0x3)
   67 #define ADW_TARGET_GROUP_SHIFT(tid)     (((tid) & 0x3) * 4)
   68 #define ADW_TARGET_GROUP_MASK(tid)      (0xF << ADW_TARGET_GROUP_SHIFT(tid))
   69 
   70 /*
   71  * Board Register offsets.
   72  */
   73 #define ADW_INTR_STATUS_REG                     0x0000
   74 #define         ADW_INTR_STATUS_INTRA           0x01
   75 #define         ADW_INTR_STATUS_INTRB           0x02
   76 #define         ADW_INTR_STATUS_INTRC           0x04
   77 #define         ADW_INTR_STATUS_INTRALL         0x07
   78 
   79 
   80 #define ADW_SIGNATURE_WORD                      0x0000
   81 #define          ADW_CHIP_ID_WORD               0x04C1
   82 
   83 #define ADW_SIGNATURE_BYTE                      0x0001
   84 #define          ADW_CHIP_ID_BYTE               0x25    
   85 
   86 #define ADW_INTR_ENABLES                        0x0002  /*8 bit */
   87 #define         ADW_INTR_ENABLE_HOST_INTR       0x01
   88 #define         ADW_INTR_ENABLE_SEL_INTR        0x02
   89 #define         ADW_INTR_ENABLE_DPR_INTR        0x04
   90 #define         ADW_INTR_ENABLE_RTA_INTR        0x08
   91 #define         ADW_INTR_ENABLE_RMA_INTR        0x10
   92 #define         ADW_INTR_ENABLE_RST_INTR        0x20
   93 #define         ADW_INTR_ENABLE_DPE_INTR        0x40
   94 #define         ADW_INTR_ENABLE_GLOBAL_INTR     0x80
   95 
   96 #define ADW_CTRL_REG                            0x0002  /*16 bit*/
   97 #define         ADW_CTRL_REG_HOST_INTR          0x0100
   98 #define         ADW_CTRL_REG_SEL_INTR           0x0200
   99 #define         ADW_CTRL_REG_DPR_INTR           0x0400
  100 #define         ADW_CTRL_REG_RTA_INTR           0x0800
  101 #define         ADW_CTRL_REG_RMA_INTR           0x1000
  102 #define         ADW_CTRL_REG_RES_BIT14          0x2000
  103 #define         ADW_CTRL_REG_DPE_INTR           0x4000
  104 #define         ADW_CTRL_REG_POWER_DONE         0x8000
  105 #define         ADW_CTRL_REG_ANY_INTR           0xFF00
  106 #define         ADW_CTRL_REG_CMD_RESET          0x00C6
  107 #define         ADW_CTRL_REG_CMD_WR_IO_REG      0x00C5
  108 #define         ADW_CTRL_REG_CMD_RD_IO_REG      0x00C4
  109 #define         ADW_CTRL_REG_CMD_WR_PCI_CFG     0x00C3
  110 #define         ADW_CTRL_REG_CMD_RD_PCI_CFG     0x00C2
  111 
  112 #define ADW_RAM_ADDR                            0x0004
  113 #define ADW_RAM_DATA                            0x0006
  114 
  115 #define ADW_RISC_CSR                            0x000A
  116 #define         ADW_RISC_CSR_STOP               0x0000
  117 #define         ADW_RISC_TEST_COND              0x2000
  118 #define         ADW_RISC_CSR_RUN                0x4000
  119 #define         ADW_RISC_CSR_SINGLE_STEP        0x8000
  120 
  121 #define ADW_SCSI_CFG0                           0x000C
  122 #define         ADW_SCSI_CFG0_TIMER_MODEAB      0xC000  /*
  123                                                          * Watchdog, Second,
  124                                                          * and Selto timer CFG
  125                                                          */
  126 #define         ADW_SCSI_CFG0_PARITY_EN         0x2000
  127 #define         ADW_SCSI_CFG0_EVEN_PARITY       0x1000
  128 #define         ADW_SCSI_CFG0_WD_LONG           0x0800  /*
  129                                                          * Watchdog Interval,
  130                                                          * 1: 57 min, 0: 13 sec
  131                                                          */
  132 #define         ADW_SCSI_CFG0_QUEUE_128         0x0400  /*
  133                                                          * Queue Size,
  134                                                          * 1: 128 byte,
  135                                                          * 0: 64 byte
  136                                                          */
  137 #define         ADW_SCSI_CFG0_PRIM_MODE         0x0100
  138 #define         ADW_SCSI_CFG0_SCAM_EN           0x0080
  139 #define         ADW_SCSI_CFG0_SEL_TMO_LONG      0x0040  /*
  140                                                          * Sel/Resel Timeout,
  141                                                          * 1: 400 ms,
  142                                                          * 0: 1.6 ms
  143                                                          */
  144 #define         ADW_SCSI_CFG0_CFRM_ID           0x0020  /* SCAM id sel. */
  145 #define         ADW_SCSI_CFG0_OUR_ID_EN         0x0010
  146 #define         ADW_SCSI_CFG0_OUR_ID            0x000F
  147 
  148 
  149 #define ADW_SCSI_CFG1                           0x000E
  150 #define         ADW_SCSI_CFG1_BIG_ENDIAN        0x8000
  151 #define         ADW_SCSI_CFG1_TERM_POL          0x2000
  152 #define         ADW_SCSI_CFG1_SLEW_RATE         0x1000
  153 #define         ADW_SCSI_CFG1_FILTER_MASK       0x0C00
  154 #define         ADW_SCSI_CFG1_FLTR_DISABLE      0x0000
  155 #define         ADW_SCSI_CFG1_FLTR_11_TO_20NS   0x0800
  156 #define         ADW_SCSI_CFG1_FLTR_21_TO_39NS   0x0C00
  157 #define         ADW_SCSI_CFG1_DIS_ACTIVE_NEG    0x0200
  158 #define         ADW_SCSI_CFG1_DIFF_MODE         0x0100
  159 #define         ADW_SCSI_CFG1_DIFF_SENSE        0x0080
  160 #define         ADW_SCSI_CFG1_TERM_CTL_MANUAL   0x0040  /* Global Term Switch */
  161 #define         ADW_SCSI_CFG1_TERM_CTL_MASK     0x0030
  162 #define         ADW_SCSI_CFG1_TERM_CTL_H        0x0020  /* Enable SCSI-H */
  163 #define         ADW_SCSI_CFG1_TERM_CTL_L        0x0010  /* Enable SCSI-L */
  164 #define         ADW_SCSI_CFG1_CABLE_DETECT      0x000F
  165 #define         ADW_SCSI_CFG1_EXT16_MASK        0x0008  /* Ext16 cable pres */
  166 #define         ADW_SCSI_CFG1_EXT8_MASK         0x0004  /* Ext8 cable pres */
  167 #define         ADW_SCSI_CFG1_INT8_MASK         0x0002  /* Int8 cable pres */
  168 #define         ADW_SCSI_CFG1_INT16_MASK        0x0001  /* Int16 cable pres */
  169 #define         ADW_SCSI_CFG1_ILLEGAL_CABLE_CONF_A_MASK \
  170 (ADW_SCSI_CFG1_EXT16_MASK|ADW_SCSI_CFG1_INT8_MASK|ADW_SCSI_CFG1_INT16_MASK)
  171 #define         ADW_SCSI_CFG1_ILLEGAL_CABLE_CONF_B_MASK \
  172 (ADW_SCSI_CFG1_EXT8_MASK|ADW_SCSI_CFG1_INT8_MASK|ADW_SCSI_CFG1_INT16_MASK)
  173 
  174 /*
  175  * Addendum for ASC-38C0800 Chip
  176  */
  177 #define         ADW2_SCSI_CFG1_DIS_TERM_DRV     0x4000  /*
  178                                                          * The Terminators
  179                                                          * must be disabled
  180                                                          * in order to detect
  181                                                          * cable presence
  182                                                          */
  183 
  184 #define         ADW2_SCSI_CFG1_DEV_DETECT       0x1C00
  185 #define         ADW2_SCSI_CFG1_DEV_DETECT_HVD   0x1000
  186 #define         ADW2_SCSI_CFG1_DEV_DETECT_LVD   0x0800
  187 #define         ADW2_SCSI_CFG1_DEV_DETECT_SE    0x0400
  188 
  189 #define         ADW2_SCSI_CFG1_TERM_CTL_LVD     0x00C0  /* Ultra2 Only */
  190 #define         ADW2_SCSI_CFG1_TERM_LVD_HI      0x0080 
  191 #define         ADW2_SCSI_CFG1_TERM_LVD_LO      0x0040
  192 #define         ADW2_SCSI_CFG1_EXTLVD_MASK      0x0008  /* ExtLVD cable pres */
  193 #define         ADW2_SCSI_CFG1_INTLVD_MASK      0x0004  /* IntLVD cable pres */
  194 
  195 #define ADW_MEM_CFG                             0x0010
  196 #define         ADW_MEM_CFG_BIOS_EN             0x40
  197 #define         ADW_MEM_CFG_FAST_EE_CLK         0x20    /* Diagnostic Bit */
  198 #define         ADW_MEM_CFG_RAM_SZ_MASK         0x1C    /* RISC RAM Size */
  199 #define         ADW_MEM_CFG_RAM_SZ_2KB          0x00
  200 #define         ADW_MEM_CFG_RAM_SZ_4KB          0x04
  201 #define         ADW_MEM_CFG_RAM_SZ_8KB          0x08
  202 #define         ADW_MEM_CFG_RAM_SZ_16KB         0x0C
  203 #define         ADW_MEM_CFG_RAM_SZ_32KB         0x10
  204 #define         ADW_MEM_CFG_RAM_SZ_64KB         0x14
  205 
  206 #define ADW_GPIO_CNTL                           0x0011
  207 #define ADW_GPIO_DATA                           0x0012
  208 
  209 #define ADW_COMMA                               0x0014
  210 #define ADW_COMMB                               0x0018  
  211 
  212 #define ADW_EEP_CMD                             0x001A
  213 #define         ADW_EEP_CMD_READ                0x0080  /* or in address */
  214 #define         ADW_EEP_CMD_WRITE               0x0040  /* or in address */
  215 #define         ADW_EEP_CMD_WRITE_ABLE          0x0030
  216 #define         ADW_EEP_CMD_WRITE_DISABLE       0x0000
  217 #define         ADW_EEP_CMD_DONE                0x0200
  218 #define         ADW_EEP_CMD_DONE_ERR            0x0001
  219 #define         ADW_EEP_DELAY_MS                100
  220 
  221 #define ADW_EEP_DATA                            0x001C
  222 
  223 #define ADW_DMA_CFG0                            0x0020
  224 #define         ADW_DMA_CFG0_BC_THRESH_ENB      0x80
  225 #define         ADW_DMA_CFG0_FIFO_THRESH        0x70
  226 #define         ADW_DMA_CFG0_FIFO_THRESH_16B    0x00
  227 #define         ADW_DMA_CFG0_FIFO_THRESH_32B    0x20
  228 #define         ADW_DMA_CFG0_FIFO_THRESH_48B    0x30
  229 #define         ADW_DMA_CFG0_FIFO_THRESH_64B    0x40
  230 #define         ADW_DMA_CFG0_FIFO_THRESH_80B    0x50
  231 #define         ADW_DMA_CFG0_FIFO_THRESH_96B    0x60
  232 #define         ADW_DMA_CFG0_FIFO_THRESH_112B   0x70
  233 #define         ADW_DMA_CFG0_START_CTL_MASK     0x0C
  234 #define         ADW_DMA_CFG0_START_CTL_TH       0x00 /* Start on thresh */
  235 #define         ADW_DMA_CFG0_START_CTL_IDLE     0x04 /* Start when idle */
  236 #define         ADW_DMA_CFG0_START_CTL_TH_IDLE  0x08 /* Either */
  237 #define         ADW_DMA_CFG0_START_CTL_EM_FU    0x0C /* Start on full/empty */
  238 #define         ADW_DMA_CFG0_READ_CMD_MASK      0x03
  239 #define         ADW_DMA_CFG0_READ_CMD_MR        0x00
  240 #define         ADW_DMA_CFG0_READ_CMD_MRL       0x02
  241 #define         ADW_DMA_CFG0_READ_CMD_MRM       0x03
  242 
  243 #define ADW_TICKLE                              0x0022
  244 #define         ADW_TICKLE_NOP                  0x00
  245 #define         ADW_TICKLE_A                    0x01
  246 #define         ADW_TICKLE_B                    0x02
  247 #define         ADW_TICKLE_C                    0x03
  248 
  249 /* Program Counter */
  250 #define ADW_PC                                  0x2A
  251 
  252 #define ADW_SCSI_CTRL                           0x0034
  253 #define         ADW_SCSI_CTRL_RSTOUT            0x2000
  254 
  255 /*
  256  * ASC-38C0800 RAM BIST Register bit definitions
  257  */
  258 #define ADW_RAM_BIST                            0x0038
  259 #define         ADW_RAM_BIST_RAM_TEST_MODE      0x80
  260 #define         ADW_RAM_BIST_PRE_TEST_MODE      0x40
  261 #define         ADW_RAM_BIST_NORMAL_MODE        0x00
  262 #define         ADW_RAM_BIST_RAM_TEST_DONE      0x10
  263 #define         ADW_RAM_BIST_RAM_TEST_STATUS    0x0F
  264 #define         ADW_RAM_BIST_RAM_TEST_HOST_ERR  0x08
  265 #define         ADW_RAM_BIST_RAM_TEST_RAM_ERR   0x04
  266 #define         ADW_RAM_BIST_RAM_TEST_RISC_ERR  0x02
  267 #define         ADW_RAM_BIST_RAM_TEST_SCSI_ERR  0x01
  268 #define         ADW_RAM_BIST_RAM_TEST_SUCCESS   0x00
  269 #define         ADW_RAM_BIST_PRE_TEST_VALUE     0x05
  270 #define         ADW_RAM_BIST_NORMAL_VALUE       0x00 
  271 #define ADW_PLL_TEST                            0x0039
  272 
  273 #define ADW_SCSI_RESET_HOLD_TIME_US             60
  274 
  275 /* LRAM Constants */
  276 #define ADW_3550_MEMSIZE        0x2000  /* 8 KB Internal Memory */
  277 #define ADW_3550_IOLEN          0x40    /* I/O Port Range in bytes */
  278 
  279 #define ADW_38C0800_MEMSIZE     0x4000  /* 16 KB Internal Memory */
  280 #define ADW_38C0800_IOLEN       0x100   /* I/O Port Range in bytes */
  281 
  282 #define ADW_38C1600_MEMSIZE     0x4000  /* 16 KB Internal Memory */
  283 #define ADW_38C1600_IOLEN       0x100   /* I/O Port Range in bytes */
  284 #define ADW_38C1600_MEMLEN      0x1000  /* Memory Range 4KB */
  285 
  286 #define ADW_MC_BIOSMEM          0x0040  /* BIOS RISC Memory Start */
  287 #define ADW_MC_BIOSLEN          0x0050  /* BIOS RISC Memory Length */
  288 
  289 #define PCI_ID_ADVANSYS_3550            0x230010CD00000000ull
  290 #define PCI_ID_ADVANSYS_38C0800_REV1    0x250010CD00000000ull
  291 #define PCI_ID_ADVANSYS_38C1600_REV1    0x270010CD00000000ull
  292 #define PCI_ID_ALL_MASK                 0xFFFFFFFFFFFFFFFFull
  293 #define PCI_ID_DEV_VENDOR_MASK          0xFFFFFFFF00000000ull
  294 
  295 /* ====================== SCSI Request Structures =========================== */
  296 
  297 #define ADW_NO_OF_SG_PER_BLOCK  15
  298 
  299 /*
  300  * Although the adapter can deal with S/G lists of indefinite size,
  301  * we limit the list to 30 to conserve space as the kernel can only send
  302  * us buffers of at most 64KB currently.
  303  */
  304 #define ADW_SG_BLOCKCNT         2
  305 #define ADW_SGSIZE              (ADW_NO_OF_SG_PER_BLOCK * ADW_SG_BLOCKCNT)
  306 
  307 struct adw_sg_elm {
  308         u_int32_t sg_addr;
  309         u_int32_t sg_count;
  310 };
  311 
  312 /* sg block structure used by the microcode */
  313 struct adw_sg_block {   
  314         u_int8_t  reserved1;
  315         u_int8_t  reserved2;
  316         u_int8_t  reserved3;
  317         u_int8_t  sg_cnt;       /* Valid entries in this block */
  318         u_int32_t sg_busaddr_next; /* link to the next sg block */
  319         struct    adw_sg_elm sg_list[ADW_NO_OF_SG_PER_BLOCK];
  320 };
  321 
  322 /* Structure representing a single allocation block of adw sg blocks */
  323 struct sg_map_node {
  324         bus_dmamap_t             sg_dmamap;
  325         bus_addr_t               sg_physaddr;
  326         struct adw_sg_block*     sg_vaddr;
  327         SLIST_ENTRY(sg_map_node) links;
  328 };
  329 
  330 typedef enum {
  331         QHSTA_NO_ERROR              = 0x00,
  332         QHSTA_M_SEL_TIMEOUT         = 0x11,
  333         QHSTA_M_DATA_OVER_RUN       = 0x12,
  334         QHSTA_M_UNEXPECTED_BUS_FREE = 0x13,
  335         QHSTA_M_QUEUE_ABORTED       = 0x15,
  336         QHSTA_M_SXFR_SDMA_ERR       = 0x16, /* SCSI DMA Error */
  337         QHSTA_M_SXFR_SXFR_PERR      = 0x17, /* SCSI Bus Parity Error */
  338         QHSTA_M_RDMA_PERR           = 0x18, /* RISC PCI DMA parity error */
  339         QHSTA_M_SXFR_OFF_UFLW       = 0x19, /* Offset Underflow */
  340         QHSTA_M_SXFR_OFF_OFLW       = 0x20, /* Offset Overflow */
  341         QHSTA_M_SXFR_WD_TMO         = 0x21, /* Watchdog Timeout */
  342         QHSTA_M_SXFR_DESELECTED     = 0x22, /* Deselected */
  343         QHSTA_M_SXFR_XFR_PH_ERR     = 0x24, /* Transfer Phase Error */
  344         QHSTA_M_SXFR_UNKNOWN_ERROR  = 0x25, /* SXFR_STATUS Unknown Error */
  345         QHSTA_M_SCSI_BUS_RESET      = 0x30, /* Request aborted from SBR */
  346         QHSTA_M_SCSI_BUS_RESET_UNSOL= 0x31, /* Request aborted from unsol. SBR*/
  347         QHSTA_M_BUS_DEVICE_RESET    = 0x32, /* Request aborted from BDR */
  348         QHSTA_M_DIRECTION_ERR       = 0x35, /* Data Phase mismatch */
  349         QHSTA_M_DIRECTION_ERR_HUNG  = 0x36, /* Data Phase mismatch - bus hang */
  350         QHSTA_M_WTM_TIMEOUT         = 0x41,
  351         QHSTA_M_BAD_CMPL_STATUS_IN  = 0x42,
  352         QHSTA_M_NO_AUTO_REQ_SENSE   = 0x43,
  353         QHSTA_M_AUTO_REQ_SENSE_FAIL = 0x44,
  354         QHSTA_M_INVALID_DEVICE      = 0x45, /* Bad target ID */
  355         QHSTA_M_FROZEN_TIDQ         = 0x46, /* TID Queue frozen. */
  356         QHSTA_M_SGBACKUP_ERROR      = 0x47  /* Scatter-Gather backup error */
  357 } host_status_t;
  358 
  359 typedef enum {
  360         QD_NO_STATUS       = 0x00, /* Request not completed yet. */
  361         QD_NO_ERROR        = 0x01,
  362         QD_ABORTED_BY_HOST = 0x02,
  363         QD_WITH_ERROR      = 0x04
  364 } done_status_t;
  365 
  366 /*
  367  * Microcode request structure
  368  *
  369  * All fields in this structure are used by the microcode so their
  370  * size and ordering cannot be changed.
  371  */
  372 struct adw_scsi_req_q {
  373         u_int8_t  cntl;           /* Ucode flags and state. */
  374         u_int8_t  target_cmd;
  375         u_int8_t  target_id;      /* Device target identifier. */
  376         u_int8_t  target_lun;     /* Device target logical unit number. */
  377         u_int32_t data_addr;      /* Data buffer physical address. */
  378         u_int32_t data_cnt;       /* Data count. Ucode sets to residual. */
  379         u_int32_t sense_baddr;    /* Sense buffer bus address. */
  380         u_int32_t carrier_baddr;  /* Carrier bus address. */
  381         u_int8_t  mflag;          /* microcode flag field. */
  382         u_int8_t  sense_len;      /* Auto-sense length. Residual on complete. */
  383         u_int8_t  cdb_len;        /* SCSI CDB length. */
  384         u_int8_t  scsi_cntl;      /* SCSI command control flags (tags, nego) */
  385 #define         ADW_QSC_NO_DISC         0x01
  386 #define         ADW_QSC_NO_TAGMSG       0x02
  387 #define         ADW_QSC_NO_SYNC         0x04
  388 #define         ADW_QSC_NO_WIDE         0x08
  389 #define         ADW_QSC_REDO_DTR        0x10 /* Renegotiate WDTR/SDTR */
  390 #define         ADW_QSC_SIMPLE_Q_TAG    0x00
  391 #define         ADW_QSC_HEAD_OF_Q_TAG   0x40
  392 #define         ADW_QSC_ORDERED_Q_TAG   0x80
  393         u_int8_t  done_status;    /* Completion status. */
  394         u_int8_t  scsi_status;    /* SCSI status byte. */
  395         u_int8_t  host_status;    /* Ucode host status. */
  396         u_int8_t  sg_wk_ix;       /* Microcode working SG index. */
  397         u_int8_t  cdb[12];        /* SCSI command block. */
  398         u_int32_t sg_real_addr;   /* SG list physical address. */ 
  399         u_int32_t scsi_req_baddr; /* Bus address of this structure. */
  400         u_int32_t sg_wk_data_cnt; /* Saved data count at disconnection. */
  401         /*
  402          * The 'tokens' placed in these two fields are
  403          * used to identify the scsi request and the next
  404          * carrier in the response queue, *not* physical
  405          * addresses.  This driver uses byte offsets for
  406          * portability and speed of mapping back to either
  407          * a virtual or physical address.
  408          */
  409         u_int32_t scsi_req_bo;    /* byte offset of this structure */
  410         u_int32_t carrier_bo;     /* byte offst of our carrier. */
  411 };
  412 
  413 typedef enum {
  414         ACB_FREE                = 0x00,
  415         ACB_ACTIVE              = 0x01,
  416         ACB_RELEASE_SIMQ        = 0x02,
  417         ACB_RECOVERY_ACB        = 0x04
  418 } acb_state;
  419 
  420 struct acb {
  421         struct          adw_scsi_req_q queue;
  422         bus_dmamap_t    dmamap;
  423         acb_state       state;
  424         union           ccb *ccb;
  425         struct          adw_sg_block* sg_blocks;
  426         bus_addr_t      sg_busaddr;
  427         struct          scsi_sense_data sense_data;
  428         SLIST_ENTRY(acb) links;
  429 };
  430 
  431 /*
  432  * EEPROM configuration format
  433  *
  434  * Field naming convention: 
  435  *
  436  *  *_enable indicates the field enables or disables the feature. The
  437  *  value is never reset.
  438  *
  439  *  *_able indicates both whether a feature should be enabled or disabled
  440  *  and whether a device is capable of the feature. At initialization
  441  *  this field may be set, but later if a device is found to be incapable
  442  *  of the feature, the field is cleared.
  443  *
  444  * Default values are maintained in a_init.c in the structure
  445  * Default_EEPROM_Config.
  446  */
  447 struct adw_eeprom
  448 {                              
  449         u_int16_t cfg_lsw;      /* 00 power up initialization */
  450 #define         ADW_EEPROM_BIG_ENDIAN   0x8000
  451 #define         ADW_EEPROM_BIOS_ENABLE  0x4000
  452 #define         ADW_EEPROM_TERM_POL     0x2000
  453 #define         ADW_EEPROM_CIS_LD       0x1000
  454 
  455                                 /* bit 13 set - Term Polarity Control */
  456                                 /* bit 14 set - BIOS Enable */
  457                                 /* bit 15 set - Big Endian Mode */
  458         u_int16_t cfg_msw;      /* unused */
  459         u_int16_t disc_enable;
  460         u_int16_t wdtr_able;
  461         union {
  462                 /*
  463                  * sync enable bits for UW cards,
  464                  * actual sync rate for TID 0-3
  465                  * on U2W and U160 cards.
  466                  */
  467                 u_int16_t sync_enable;
  468                 u_int16_t sdtr1;
  469         } sync1;
  470         u_int16_t start_motor;
  471         u_int16_t tagqng_able;
  472         u_int16_t bios_scan;
  473         u_int16_t scam_tolerant;
  474  
  475         u_int8_t  adapter_scsi_id;
  476         u_int8_t  bios_boot_delay;
  477  
  478         u_int8_t  scsi_reset_delay;
  479         u_int8_t  bios_id_lun;  /*    high nibble is lun */  
  480                                 /*    low nibble is scsi id */
  481 
  482         u_int8_t  termination_se;       /* 0 - automatic */
  483 #define         ADW_EEPROM_TERM_AUTO            0
  484 #define         ADW_EEPROM_TERM_OFF             1
  485 #define         ADW_EEPROM_TERM_HIGH_ON         2
  486 #define         ADW_EEPROM_TERM_BOTH_ON         3
  487 
  488         u_int8_t  termination_lvd;
  489         u_int16_t bios_ctrl;
  490 #define         ADW_BIOS_INIT_DIS     0x0001 /* Don't act as initiator */
  491 #define         ADW_BIOS_EXT_TRANS    0x0002 /* > 1 GB support */
  492 #define         ADW_BIOS_MORE_2DISK   0x0004 /* > 1 GB support */
  493 #define         ADW_BIOS_NO_REMOVABLE 0x0008 /* don't support removable media */
  494 #define         ADW_BIOS_CD_BOOT      0x0010 /* support bootable CD */
  495 #define         ADW_BIOS_SCAN_EN      0x0020 /* BIOS SCAN enabled */
  496 #define         ADW_BIOS_MULTI_LUN    0x0040 /* probe luns */
  497 #define         ADW_BIOS_MESSAGE      0x0080 /* display BIOS message */
  498 #define         ADW_BIOS_RESET_BUS    0x0200 /* reset SCSI bus durint init */
  499 #define         ADW_BIOS_QUIET        0x0800 /* No verbose initialization */
  500 #define         ADW_BIOS_SCSI_PAR_EN  0x1000 /* SCSI parity enabled */
  501 
  502         union {
  503                 /* 13
  504                  * ultra enable bits for UW cards,
  505                  * actual sync rate for TID 4-7
  506                  * on U2W and U160 cards.
  507                  */
  508                 u_int16_t ultra_enable;
  509                 u_int16_t sdtr2;
  510         } sync2;
  511         union {
  512                 /* 14
  513                  * reserved for UW cards,
  514                  * actual sync rate for TID 8-11
  515                  * on U2W and U160 cards.
  516                  */
  517                 u_int16_t reserved;
  518                 u_int16_t sdtr3;
  519         } sync3;
  520         u_int8_t  max_host_qng; /* 15 maximum host queuing */
  521         u_int8_t  max_dvc_qng;  /*    maximum per device queuing */
  522         u_int16_t dvc_cntl;     /* 16 control bit for driver */
  523         union {
  524                 /* 17
  525                  * reserved for UW cards,
  526                  * actual sync rate for TID 12-15
  527                  * on U2W and U160 cards.
  528                  */
  529                 u_int16_t reserved;
  530                 u_int16_t sdtr4;
  531         } sync4;
  532         u_int16_t serial_number[3]; /* 18-20 */
  533         u_int16_t checksum;     /* 21 */
  534         u_int8_t  oem_name[16]; /* 22 - 29 */
  535         u_int16_t dvc_err_code; /* 30 */
  536         u_int16_t adv_err_code; /* 31 */
  537         u_int16_t adv_err_addr; /* 32 */
  538         u_int16_t saved_dvc_err_code; /* 33 */
  539         u_int16_t saved_adv_err_code; /* 34 */
  540         u_int16_t saved_adv_err_addr; /* 35 */
  541         u_int16_t reserved[20];       /* 36 - 55 */
  542         u_int16_t cisptr_lsw;   /* 56 CIS data */
  543         u_int16_t cisptr_msw;   /* 57 CIS data */
  544         u_int32_t subid;        /* 58-59 SubSystem Vendor/Dev ID */
  545         u_int16_t reserved2[4];
  546 };
  547 
  548 /* EEProm Addresses */
  549 #define ADW_EEP_DVC_CFG_BEGIN           0x00
  550 #define ADW_EEP_DVC_CFG_END     (offsetof(struct adw_eeprom, checksum)/2)
  551 #define ADW_EEP_DVC_CTL_BEGIN   (offsetof(struct adw_eeprom, oem_name)/2)
  552 #define ADW_EEP_MAX_WORD_ADDR   (sizeof(struct adw_eeprom)/2)
  553 
  554 #define ADW_BUS_RESET_HOLD_DELAY_US 100
  555 
  556 typedef enum {
  557         ADW_CHIP_NONE,
  558         ADW_CHIP_ASC3550,       /* Ultra-Wide IC */
  559         ADW_CHIP_ASC38C0800,    /* Ultra2-Wide/LVD IC */
  560         ADW_CHIP_ASC38C1600     /* Ultra3-Wide/LVD2 IC */
  561 } adw_chip;
  562 
  563 typedef enum {
  564         ADW_FENONE        = 0x0000,
  565         ADW_ULTRA         = 0x0001,     /* Supports 20MHz Transfers */
  566         ADW_ULTRA2        = 0x0002,     /* Supports 40MHz Transfers */
  567         ADW_DT            = 0x0004,     /* Supports Double Transistion REQ/ACK*/
  568         ADW_WIDE          = 0x0008,     /* Wide Channel */
  569         ADW_ASC3550_FE    = ADW_ULTRA,  
  570         ADW_ASC38C0800_FE = ADW_ULTRA2,
  571         ADW_ASC38C1600_FE = ADW_ULTRA2|ADW_DT
  572 } adw_feature;
  573 
  574 typedef enum {
  575         ADW_FNONE         = 0x0000,
  576         ADW_EEPROM_FAILED = 0x0001
  577 } adw_flag;
  578 
  579 typedef enum {
  580         ADW_STATE_NORMAL        = 0x00,
  581         ADW_RESOURCE_SHORTAGE   = 0x01
  582 } adw_state;
  583 
  584 typedef enum {
  585         ADW_MC_SDTR_ASYNC,
  586         ADW_MC_SDTR_5,
  587         ADW_MC_SDTR_10,
  588         ADW_MC_SDTR_20,
  589         ADW_MC_SDTR_40,
  590         ADW_MC_SDTR_80
  591 } adw_mc_sdtr;
  592 
  593 struct adw_syncrate
  594 {
  595         adw_mc_sdtr mc_sdtr;
  596         u_int8_t    period;
  597         char       *rate;
  598 };
  599 
  600 /* We have an input and output queue for our carrier structures */
  601 #define ADW_OUTPUT_QUEUE 0      /* Offset into carriers member */
  602 #define ADW_INPUT_QUEUE 1       /* Offset into carriers member */
  603 #define ADW_NUM_CARRIER_QUEUES 2
  604 struct adw_softc
  605 {
  606         bus_space_tag_t           tag;
  607         bus_space_handle_t        bsh;
  608         adw_state                 state;
  609         bus_dma_tag_t             buffer_dmat;
  610         struct acb               *acbs;
  611         struct adw_carrier       *carriers;
  612         struct adw_carrier       *free_carriers;
  613         struct adw_carrier       *commandq;
  614         struct adw_carrier       *responseq;
  615         LIST_HEAD(, ccb_hdr)      pending_ccbs;
  616         SLIST_HEAD(, acb)         free_acb_list;
  617         bus_dma_tag_t             parent_dmat;
  618         bus_dma_tag_t             carrier_dmat; /* dmat for our acb carriers*/
  619         bus_dmamap_t              carrier_dmamap;
  620         bus_dma_tag_t             acb_dmat;     /* dmat for our ccb array */
  621         bus_dmamap_t              acb_dmamap;
  622         bus_dma_tag_t             sg_dmat;      /* dmat for our sg maps */
  623         SLIST_HEAD(, sg_map_node) sg_maps;
  624         bus_addr_t                acb_busbase;
  625         bus_addr_t                carrier_busbase;
  626         adw_chip                  chip;
  627         adw_feature               features;
  628         adw_flag                  flags;
  629         u_int                     memsize;
  630         char                      channel;
  631         struct cam_path          *path;
  632         struct cam_sim           *sim;
  633         struct resource          *regs;
  634         struct resource          *irq;
  635         void                     *ih;
  636         const struct adw_mcode   *mcode_data;
  637         const struct adw_eeprom  *default_eeprom;
  638         device_t                  device;
  639         int                       regs_res_type;
  640         int                       regs_res_id;
  641         int                       irq_res_type;
  642         u_int                     max_acbs;
  643         u_int                     num_acbs;
  644         u_int                     initiator_id;
  645         u_int                     init_level;
  646         u_int                     unit;
  647         char*                     name;
  648         cam_status                last_reset;   /* Last reset type */
  649         u_int16_t                 bios_ctrl;
  650         u_int16_t                 user_wdtr;
  651         u_int16_t                 user_sdtr[4]; /* A nibble per-device */
  652         u_int16_t                 user_tagenb;
  653         u_int16_t                 tagenb;
  654         u_int16_t                 user_discenb;
  655         u_int16_t                 serial_number[3];
  656 };
  657 
  658 extern const struct adw_eeprom adw_asc3550_default_eeprom;
  659 extern const struct adw_eeprom adw_asc38C0800_default_eeprom;
  660 extern const struct adw_syncrate adw_syncrates[];
  661 extern const int adw_num_syncrates;
  662 
  663 #define adw_inb(adw, port)                              \
  664         bus_space_read_1((adw)->tag, (adw)->bsh, port)
  665 #define adw_inw(adw, port)                              \
  666         bus_space_read_2((adw)->tag, (adw)->bsh, port)
  667 #define adw_inl(adw, port)                              \
  668         bus_space_read_4((adw)->tag, (adw)->bsh, port)
  669 
  670 #define adw_outb(adw, port, value)                      \
  671         bus_space_write_1((adw)->tag, (adw)->bsh, port, value)
  672 #define adw_outw(adw, port, value)                      \
  673         bus_space_write_2((adw)->tag, (adw)->bsh, port, value)
  674 #define adw_outl(adw, port, value)                      \
  675         bus_space_write_4((adw)->tag, (adw)->bsh, port, value)
  676 
  677 #define adw_set_multi_2(adw, port, value, count)        \
  678         bus_space_set_multi_2((adw)->tag, (adw)->bsh, port, value, count)
  679 
  680 static __inline const char*     adw_name(struct adw_softc *adw);
  681 static __inline u_int   adw_lram_read_8(struct adw_softc *adw, u_int addr);
  682 static __inline u_int   adw_lram_read_16(struct adw_softc *adw, u_int addr);
  683 static __inline u_int   adw_lram_read_32(struct adw_softc *adw, u_int addr);
  684 static __inline void    adw_lram_write_8(struct adw_softc *adw, u_int addr,
  685                                          u_int value);
  686 static __inline void    adw_lram_write_16(struct adw_softc *adw, u_int addr,
  687                                           u_int value);
  688 static __inline void    adw_lram_write_32(struct adw_softc *adw, u_int addr,
  689                                           u_int value);
  690 
  691 static __inline u_int32_t       acbvtobo(struct adw_softc *adw,
  692                                            struct acb *acb);
  693 static __inline u_int32_t       acbvtob(struct adw_softc *adw,
  694                                            struct acb *acb);
  695 static __inline struct acb *    acbbotov(struct adw_softc *adw,
  696                                         u_int32_t busaddr);
  697 static __inline struct acb *    acbbtov(struct adw_softc *adw,
  698                                         u_int32_t busaddr);
  699 static __inline u_int32_t       carriervtobo(struct adw_softc *adw,
  700                                              struct adw_carrier *carrier);
  701 static __inline u_int32_t       carriervtob(struct adw_softc *adw,
  702                                             struct adw_carrier *carrier);
  703 static __inline struct adw_carrier *
  704                                 carrierbotov(struct adw_softc *adw,
  705                                              u_int32_t byte_offset);
  706 static __inline struct adw_carrier *
  707                                 carrierbtov(struct adw_softc *adw,
  708                                             u_int32_t baddr);
  709 
  710 static __inline const char*
  711 adw_name(struct adw_softc *adw)
  712 {
  713         return (adw->name);
  714 }
  715 
  716 static __inline u_int
  717 adw_lram_read_8(struct adw_softc *adw, u_int addr)
  718 {
  719         adw_outw(adw, ADW_RAM_ADDR, addr);
  720         return (adw_inb(adw, ADW_RAM_DATA));
  721 }
  722 
  723 static __inline u_int
  724 adw_lram_read_16(struct adw_softc *adw, u_int addr)
  725 {
  726         adw_outw(adw, ADW_RAM_ADDR, addr);
  727         return (adw_inw(adw, ADW_RAM_DATA));
  728 }
  729 
  730 static __inline u_int
  731 adw_lram_read_32(struct adw_softc *adw, u_int addr)
  732 {
  733         u_int retval;
  734 
  735         adw_outw(adw, ADW_RAM_ADDR, addr);
  736         retval = adw_inw(adw, ADW_RAM_DATA);
  737         retval |= (adw_inw(adw, ADW_RAM_DATA) << 16);
  738         return (retval);
  739 }
  740 
  741 static __inline void
  742 adw_lram_write_8(struct adw_softc *adw, u_int addr, u_int value)
  743 {
  744         adw_outw(adw, ADW_RAM_ADDR, addr);
  745         adw_outb(adw, ADW_RAM_DATA, value);
  746 }
  747 
  748 static __inline void
  749 adw_lram_write_16(struct adw_softc *adw, u_int addr, u_int value)
  750 {
  751         adw_outw(adw, ADW_RAM_ADDR, addr);
  752         adw_outw(adw, ADW_RAM_DATA, value);
  753 }
  754 
  755 static __inline void
  756 adw_lram_write_32(struct adw_softc *adw, u_int addr, u_int value)
  757 {
  758         adw_outw(adw, ADW_RAM_ADDR, addr);
  759         adw_outw(adw, ADW_RAM_DATA, value);
  760         adw_outw(adw, ADW_RAM_DATA, value >> 16);
  761 }
  762 
  763 static __inline u_int32_t
  764 acbvtobo(struct adw_softc *adw, struct acb *acb)
  765 {
  766         return ((u_int32_t)((caddr_t)acb - (caddr_t)adw->acbs));
  767 }
  768 
  769 static __inline u_int32_t
  770 acbvtob(struct adw_softc *adw, struct acb *acb)
  771 {
  772         return (adw->acb_busbase + acbvtobo(adw, acb));
  773 }
  774 
  775 static __inline struct acb *
  776 acbbotov(struct adw_softc *adw, u_int32_t byteoffset)
  777 {
  778         return ((struct acb *)((caddr_t)adw->acbs + byteoffset));
  779 }
  780 
  781 static __inline struct acb *
  782 acbbtov(struct adw_softc *adw, u_int32_t busaddr)
  783 {
  784         return (acbbotov(adw, busaddr - adw->acb_busbase));
  785 }
  786 
  787 /*
  788  * Return the byte offset for a carrier relative to our array of carriers.
  789  */
  790 static __inline u_int32_t
  791 carriervtobo(struct adw_softc *adw, struct adw_carrier *carrier)
  792 {
  793         return ((u_int32_t)((caddr_t)carrier - (caddr_t)adw->carriers));
  794 }
  795 
  796 static __inline u_int32_t
  797 carriervtob(struct adw_softc *adw, struct adw_carrier *carrier)
  798 {
  799         return (adw->carrier_busbase + carriervtobo(adw, carrier));
  800 }
  801 
  802 static __inline struct adw_carrier *
  803 carrierbotov(struct adw_softc *adw, u_int32_t byte_offset)
  804 {
  805         return ((struct adw_carrier *)((caddr_t)adw->carriers + byte_offset));
  806 }
  807 
  808 static __inline struct adw_carrier *
  809 carrierbtov(struct adw_softc *adw, u_int32_t baddr)
  810 {
  811         return (carrierbotov(adw, baddr - adw->carrier_busbase));
  812 }
  813 
  814 /* Intialization */
  815 int             adw_find_signature(struct adw_softc *adw);
  816 void            adw_reset_chip(struct adw_softc *adw);
  817 int             adw_reset_bus(struct adw_softc *adw);
  818 u_int16_t       adw_eeprom_read(struct adw_softc *adw, struct adw_eeprom *buf);
  819 void            adw_eeprom_write(struct adw_softc *adw, struct adw_eeprom *buf);
  820 int             adw_init_chip(struct adw_softc *adw, u_int term_scsicfg1);
  821 void            adw_set_user_sdtr(struct adw_softc *adw,
  822                                   u_int tid, u_int mc_sdtr);
  823 u_int           adw_get_user_sdtr(struct adw_softc *adw, u_int tid);
  824 void            adw_set_chip_sdtr(struct adw_softc *adw, u_int tid, u_int sdtr);
  825 u_int           adw_get_chip_sdtr(struct adw_softc *adw, u_int tid);
  826 u_int           adw_find_sdtr(struct adw_softc *adw, u_int period);
  827 u_int           adw_find_period(struct adw_softc *adw, u_int mc_sdtr);
  828 u_int           adw_hshk_cfg_period_factor(u_int tinfo);
  829 
  830 /* Idle Commands */
  831 adw_idle_cmd_status_t   adw_idle_cmd_send(struct adw_softc *adw, u_int cmd,
  832                                           u_int parameter);
  833 
  834 /* SCSI Transaction Processing */
  835 static __inline void    adw_send_acb(struct adw_softc *adw, struct acb *acb,
  836                                      u_int32_t acb_baddr);
  837 
  838 static __inline void    adw_tickle_risc(struct adw_softc *adw, u_int value)
  839 {
  840         /*
  841          * Tickle the RISC to tell it to read its Command Queue Head pointer.
  842          */
  843         adw_outb(adw, ADW_TICKLE, value);
  844         if (adw->chip == ADW_CHIP_ASC3550) {
  845                 /*
  846                  * Clear the tickle value. In the ASC-3550 the RISC flag
  847                  * command 'clr_tickle_a' does not work unless the host
  848                  * value is cleared.
  849                  */
  850                 adw_outb(adw, ADW_TICKLE, ADW_TICKLE_NOP);
  851         }
  852 }
  853 
  854 static __inline void
  855 adw_send_acb(struct adw_softc *adw, struct acb *acb, u_int32_t acb_baddr)
  856 {
  857         struct adw_carrier *new_cq;
  858 
  859         new_cq = adw->free_carriers;
  860         adw->free_carriers = carrierbotov(adw, new_cq->next_ba);
  861         new_cq->next_ba = ADW_CQ_STOPPER;
  862 
  863         acb->queue.carrier_baddr = adw->commandq->carr_ba;
  864         acb->queue.carrier_bo = adw->commandq->carr_offset;
  865         adw->commandq->areq_ba = acbvtob(adw, acb);
  866         adw->commandq->next_ba = new_cq->carr_ba;
  867 #if 0
  868         printf("EnQ 0x%x 0x%x 0x%x 0x%x\n",
  869                adw->commandq->carr_offset,
  870                adw->commandq->carr_ba,
  871                adw->commandq->areq_ba,
  872                adw->commandq->next_ba);
  873 #endif
  874         adw->commandq = new_cq;
  875 
  876         
  877         adw_tickle_risc(adw, ADW_TICKLE_A);
  878 }
  879      
  880 #endif /* _ADWLIB_H_ */

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