1 /*-
2 * Copyright (c) 2004, 2005 Jung-uk Kim <jkim@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD: releng/10.3/sys/dev/agp/agp_amd64.c 275406 2014-12-02 13:46:13Z tijl $");
29
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/malloc.h>
33 #include <sys/kernel.h>
34 #include <sys/module.h>
35 #include <sys/bus.h>
36 #include <sys/lock.h>
37 #include <sys/mutex.h>
38 #include <sys/proc.h>
39
40 #include <dev/agp/agppriv.h>
41 #include <dev/agp/agpreg.h>
42 #include <dev/pci/pcivar.h>
43 #include <dev/pci/pcireg.h>
44
45 #include <vm/vm.h>
46 #include <vm/vm_object.h>
47 #include <vm/pmap.h>
48 #include <machine/bus.h>
49 #include <machine/resource.h>
50 #include <sys/rman.h>
51
52 /* XXX */
53 extern void pci_cfgregwrite(int, int, int, int, uint32_t, int);
54 extern uint32_t pci_cfgregread(int, int, int, int, int);
55
56 static void agp_amd64_apbase_fixup(device_t);
57
58 static void agp_amd64_uli_init(device_t);
59 static int agp_amd64_uli_set_aperture(device_t, uint32_t);
60
61 static int agp_amd64_nvidia_match(uint16_t);
62 static void agp_amd64_nvidia_init(device_t);
63 static int agp_amd64_nvidia_set_aperture(device_t, uint32_t);
64
65 static int agp_amd64_via_match(void);
66 static void agp_amd64_via_init(device_t);
67 static int agp_amd64_via_set_aperture(device_t, uint32_t);
68
69 MALLOC_DECLARE(M_AGP);
70
71 #define AMD64_MAX_MCTRL 8
72
73 struct agp_amd64_softc {
74 struct agp_softc agp;
75 uint32_t initial_aperture;
76 struct agp_gatt *gatt;
77 uint32_t apbase;
78 int mctrl[AMD64_MAX_MCTRL];
79 int n_mctrl;
80 int via_agp;
81 };
82
83 static const char*
84 agp_amd64_match(device_t dev)
85 {
86 if (pci_get_class(dev) != PCIC_BRIDGE ||
87 pci_get_subclass(dev) != PCIS_BRIDGE_HOST ||
88 agp_find_caps(dev) == 0)
89 return (NULL);
90
91 switch (pci_get_devid(dev)) {
92 case 0x74541022:
93 return ("AMD 8151 AGP graphics tunnel");
94 case 0x07551039:
95 return ("SiS 755 host to AGP bridge");
96 case 0x07601039:
97 return ("SiS 760 host to AGP bridge");
98 case 0x168910b9:
99 return ("ULi M1689 AGP Controller");
100 case 0x00d110de:
101 if (agp_amd64_nvidia_match(0x00d2))
102 return (NULL);
103 return ("NVIDIA nForce3 AGP Controller");
104 case 0x00e110de:
105 if (agp_amd64_nvidia_match(0x00e2))
106 return (NULL);
107 return ("NVIDIA nForce3-250 AGP Controller");
108 case 0x02041106:
109 return ("VIA 8380 host to PCI bridge");
110 case 0x02381106:
111 return ("VIA 3238 host to PCI bridge");
112 case 0x02821106:
113 return ("VIA K8T800Pro host to PCI bridge");
114 case 0x31881106:
115 return ("VIA 8385 host to PCI bridge");
116 }
117
118 return (NULL);
119 }
120
121 static int
122 agp_amd64_nvidia_match(uint16_t devid)
123 {
124 /* XXX nForce3 requires secondary AGP bridge at 0:11:0. */
125 if (pci_cfgregread(0, 11, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
126 pci_cfgregread(0, 11, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
127 pci_cfgregread(0, 11, 0, PCIR_VENDOR, 2) != 0x10de ||
128 pci_cfgregread(0, 11, 0, PCIR_DEVICE, 2) != devid)
129 return (ENXIO);
130
131 return (0);
132 }
133
134 static int
135 agp_amd64_via_match(void)
136 {
137 /* XXX Some VIA bridge requires secondary AGP bridge at 0:1:0. */
138 if (pci_cfgregread(0, 1, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
139 pci_cfgregread(0, 1, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
140 pci_cfgregread(0, 1, 0, PCIR_VENDOR, 2) != 0x1106 ||
141 pci_cfgregread(0, 1, 0, PCIR_DEVICE, 2) != 0xb188 ||
142 (pci_cfgregread(0, 1, 0, AGP_VIA_AGPSEL, 1) & 2))
143 return (0);
144
145 return (1);
146 }
147
148 static int
149 agp_amd64_probe(device_t dev)
150 {
151 const char *desc;
152
153 if (resource_disabled("agp", device_get_unit(dev)))
154 return (ENXIO);
155 if ((desc = agp_amd64_match(dev))) {
156 device_set_desc(dev, desc);
157 return (BUS_PROBE_DEFAULT);
158 }
159
160 return (ENXIO);
161 }
162
163 static int
164 agp_amd64_attach(device_t dev)
165 {
166 struct agp_amd64_softc *sc = device_get_softc(dev);
167 struct agp_gatt *gatt;
168 uint32_t devid;
169 int i, n, error;
170
171 for (i = 0, n = 0; i < PCI_SLOTMAX && n < AMD64_MAX_MCTRL; i++) {
172 devid = pci_cfgregread(0, i, 3, 0, 4);
173 if (devid == 0x11031022 || devid == 0x12031022) {
174 sc->mctrl[n] = i;
175 n++;
176 }
177 }
178 if (n == 0)
179 return (ENXIO);
180
181 sc->n_mctrl = n;
182
183 if (bootverbose)
184 device_printf(dev, "%d Miscellaneous Control unit(s) found.\n",
185 sc->n_mctrl);
186
187 if ((error = agp_generic_attach(dev)))
188 return (error);
189
190 sc->initial_aperture = AGP_GET_APERTURE(dev);
191
192 for (;;) {
193 gatt = agp_alloc_gatt(dev);
194 if (gatt)
195 break;
196
197 /*
198 * Probably contigmalloc failure. Try reducing the
199 * aperture so that the gatt size reduces.
200 */
201 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) {
202 agp_generic_detach(dev);
203 return (ENOMEM);
204 }
205 }
206 sc->gatt = gatt;
207
208 switch (pci_get_vendor(dev)) {
209 case 0x10b9: /* ULi */
210 agp_amd64_uli_init(dev);
211 if (agp_amd64_uli_set_aperture(dev, sc->initial_aperture))
212 return (ENXIO);
213 break;
214
215 case 0x10de: /* nVidia */
216 agp_amd64_nvidia_init(dev);
217 if (agp_amd64_nvidia_set_aperture(dev, sc->initial_aperture))
218 return (ENXIO);
219 break;
220
221 case 0x1106: /* VIA */
222 sc->via_agp = agp_amd64_via_match();
223 if (sc->via_agp) {
224 agp_amd64_via_init(dev);
225 if (agp_amd64_via_set_aperture(dev,
226 sc->initial_aperture))
227 return (ENXIO);
228 }
229 break;
230 }
231
232 /* Install the gatt and enable aperture. */
233 for (i = 0; i < sc->n_mctrl; i++) {
234 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_ATTBASE,
235 (uint32_t)(gatt->ag_physical >> 8) & AGP_AMD64_ATTBASE_MASK,
236 4);
237 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
238 (pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) |
239 AGP_AMD64_APCTRL_GARTEN) &
240 ~(AGP_AMD64_APCTRL_DISGARTCPU | AGP_AMD64_APCTRL_DISGARTIO),
241 4);
242 }
243
244 return (0);
245 }
246
247 static int
248 agp_amd64_detach(device_t dev)
249 {
250 struct agp_amd64_softc *sc = device_get_softc(dev);
251 int i;
252
253 agp_free_cdev(dev);
254
255 for (i = 0; i < sc->n_mctrl; i++)
256 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
257 pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) &
258 ~AGP_AMD64_APCTRL_GARTEN, 4);
259
260 AGP_SET_APERTURE(dev, sc->initial_aperture);
261 agp_free_gatt(sc->gatt);
262 agp_free_res(dev);
263
264 return (0);
265 }
266
267 static uint32_t agp_amd64_table[] = {
268 0x02000000, /* 32 MB */
269 0x04000000, /* 64 MB */
270 0x08000000, /* 128 MB */
271 0x10000000, /* 256 MB */
272 0x20000000, /* 512 MB */
273 0x40000000, /* 1024 MB */
274 0x80000000, /* 2048 MB */
275 };
276
277 #define AGP_AMD64_TABLE_SIZE \
278 (sizeof(agp_amd64_table) / sizeof(agp_amd64_table[0]))
279
280 static uint32_t
281 agp_amd64_get_aperture(device_t dev)
282 {
283 struct agp_amd64_softc *sc = device_get_softc(dev);
284 uint32_t i;
285
286 i = (pci_cfgregread(0, sc->mctrl[0], 3, AGP_AMD64_APCTRL, 4) &
287 AGP_AMD64_APCTRL_SIZE_MASK) >> 1;
288
289 if (i >= AGP_AMD64_TABLE_SIZE)
290 return (0);
291
292 return (agp_amd64_table[i]);
293 }
294
295 static int
296 agp_amd64_set_aperture(device_t dev, uint32_t aperture)
297 {
298 struct agp_amd64_softc *sc = device_get_softc(dev);
299 uint32_t i;
300 int j;
301
302 for (i = 0; i < AGP_AMD64_TABLE_SIZE; i++)
303 if (agp_amd64_table[i] == aperture)
304 break;
305 if (i >= AGP_AMD64_TABLE_SIZE)
306 return (EINVAL);
307
308 for (j = 0; j < sc->n_mctrl; j++)
309 pci_cfgregwrite(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL,
310 (pci_cfgregread(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL, 4) &
311 ~(AGP_AMD64_APCTRL_SIZE_MASK)) | (i << 1), 4);
312
313 switch (pci_get_vendor(dev)) {
314 case 0x10b9: /* ULi */
315 return (agp_amd64_uli_set_aperture(dev, aperture));
316 break;
317
318 case 0x10de: /* nVidia */
319 return (agp_amd64_nvidia_set_aperture(dev, aperture));
320 break;
321
322 case 0x1106: /* VIA */
323 if (sc->via_agp)
324 return (agp_amd64_via_set_aperture(dev, aperture));
325 break;
326 }
327
328 return (0);
329 }
330
331 static int
332 agp_amd64_bind_page(device_t dev, vm_offset_t offset, vm_offset_t physical)
333 {
334 struct agp_amd64_softc *sc = device_get_softc(dev);
335
336 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
337 return (EINVAL);
338
339 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] =
340 (physical & 0xfffff000) | ((physical >> 28) & 0x00000ff0) | 3;
341
342 return (0);
343 }
344
345 static int
346 agp_amd64_unbind_page(device_t dev, vm_offset_t offset)
347 {
348 struct agp_amd64_softc *sc = device_get_softc(dev);
349
350 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
351 return (EINVAL);
352
353 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
354
355 return (0);
356 }
357
358 static void
359 agp_amd64_flush_tlb(device_t dev)
360 {
361 struct agp_amd64_softc *sc = device_get_softc(dev);
362 int i;
363
364 for (i = 0; i < sc->n_mctrl; i++)
365 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL,
366 pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL, 4) |
367 AGP_AMD64_CACHECTRL_INVGART, 4);
368 }
369
370 static void
371 agp_amd64_apbase_fixup(device_t dev)
372 {
373 struct agp_amd64_softc *sc = device_get_softc(dev);
374 uint32_t apbase;
375 int i;
376
377 sc->apbase = rman_get_start(sc->agp.as_aperture);
378 apbase = (sc->apbase >> 25) & AGP_AMD64_APBASE_MASK;
379 for (i = 0; i < sc->n_mctrl; i++)
380 pci_cfgregwrite(0, sc->mctrl[i], 3,
381 AGP_AMD64_APBASE, apbase, 4);
382 }
383
384 static void
385 agp_amd64_uli_init(device_t dev)
386 {
387 struct agp_amd64_softc *sc = device_get_softc(dev);
388
389 agp_amd64_apbase_fixup(dev);
390 pci_write_config(dev, AGP_AMD64_ULI_APBASE,
391 (pci_read_config(dev, AGP_AMD64_ULI_APBASE, 4) & 0x0000000f) |
392 sc->apbase, 4);
393 pci_write_config(dev, AGP_AMD64_ULI_HTT_FEATURE, sc->apbase, 4);
394 }
395
396 static int
397 agp_amd64_uli_set_aperture(device_t dev, uint32_t aperture)
398 {
399 struct agp_amd64_softc *sc = device_get_softc(dev);
400
401 switch (aperture) {
402 case 0x02000000: /* 32 MB */
403 case 0x04000000: /* 64 MB */
404 case 0x08000000: /* 128 MB */
405 case 0x10000000: /* 256 MB */
406 break;
407 default:
408 return (EINVAL);
409 }
410
411 pci_write_config(dev, AGP_AMD64_ULI_ENU_SCR,
412 sc->apbase + aperture - 1, 4);
413
414 return (0);
415 }
416
417 static void
418 agp_amd64_nvidia_init(device_t dev)
419 {
420 struct agp_amd64_softc *sc = device_get_softc(dev);
421
422 agp_amd64_apbase_fixup(dev);
423 pci_write_config(dev, AGP_AMD64_NVIDIA_0_APBASE,
424 (pci_read_config(dev, AGP_AMD64_NVIDIA_0_APBASE, 4) & 0x0000000f) |
425 sc->apbase, 4);
426 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE1, sc->apbase, 4);
427 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE2, sc->apbase, 4);
428 }
429
430 static int
431 agp_amd64_nvidia_set_aperture(device_t dev, uint32_t aperture)
432 {
433 struct agp_amd64_softc *sc = device_get_softc(dev);
434 uint32_t apsize;
435
436 switch (aperture) {
437 case 0x02000000: apsize = 0x0f; break; /* 32 MB */
438 case 0x04000000: apsize = 0x0e; break; /* 64 MB */
439 case 0x08000000: apsize = 0x0c; break; /* 128 MB */
440 case 0x10000000: apsize = 0x08; break; /* 256 MB */
441 case 0x20000000: apsize = 0x00; break; /* 512 MB */
442 default:
443 return (EINVAL);
444 }
445
446 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE,
447 (pci_cfgregread(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE, 4) &
448 0xfffffff0) | apsize, 4);
449 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT1,
450 sc->apbase + aperture - 1, 4);
451 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT2,
452 sc->apbase + aperture - 1, 4);
453
454 return (0);
455 }
456
457 static void
458 agp_amd64_via_init(device_t dev)
459 {
460 struct agp_amd64_softc *sc = device_get_softc(dev);
461
462 agp_amd64_apbase_fixup(dev);
463 pci_cfgregwrite(0, 1, 0, AGP3_VIA_ATTBASE, sc->gatt->ag_physical, 4);
464 pci_cfgregwrite(0, 1, 0, AGP3_VIA_GARTCTRL,
465 pci_cfgregread(0, 1, 0, AGP3_VIA_ATTBASE, 4) | 0x180, 4);
466 }
467
468 static int
469 agp_amd64_via_set_aperture(device_t dev, uint32_t aperture)
470 {
471 uint32_t apsize;
472
473 apsize = ((aperture - 1) >> 20) ^ 0xff;
474 if ((((apsize ^ 0xff) << 20) | ((1 << 20) - 1)) + 1 != aperture)
475 return (EINVAL);
476 pci_cfgregwrite(0, 1, 0, AGP3_VIA_APSIZE, apsize, 1);
477
478 return (0);
479 }
480
481 static device_method_t agp_amd64_methods[] = {
482 /* Device interface */
483 DEVMETHOD(device_probe, agp_amd64_probe),
484 DEVMETHOD(device_attach, agp_amd64_attach),
485 DEVMETHOD(device_detach, agp_amd64_detach),
486 DEVMETHOD(device_shutdown, bus_generic_shutdown),
487 DEVMETHOD(device_suspend, bus_generic_suspend),
488 DEVMETHOD(device_resume, bus_generic_resume),
489
490 /* AGP interface */
491 DEVMETHOD(agp_get_aperture, agp_amd64_get_aperture),
492 DEVMETHOD(agp_set_aperture, agp_amd64_set_aperture),
493 DEVMETHOD(agp_bind_page, agp_amd64_bind_page),
494 DEVMETHOD(agp_unbind_page, agp_amd64_unbind_page),
495 DEVMETHOD(agp_flush_tlb, agp_amd64_flush_tlb),
496 DEVMETHOD(agp_enable, agp_generic_enable),
497 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
498 DEVMETHOD(agp_free_memory, agp_generic_free_memory),
499 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
500 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
501
502 { 0, 0 }
503 };
504
505 static driver_t agp_amd64_driver = {
506 "agp",
507 agp_amd64_methods,
508 sizeof(struct agp_amd64_softc),
509 };
510
511 static devclass_t agp_devclass;
512
513 DRIVER_MODULE(agp_amd64, hostb, agp_amd64_driver, agp_devclass, 0, 0);
514 MODULE_DEPEND(agp_amd64, agp, 1, 1, 1);
515 MODULE_DEPEND(agp_amd64, pci, 1, 1, 1);
Cache object: 1babd8d5082b79c7cecd43380e1f707e
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