Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/agp/agp_amd64.c
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1 /*- 2 * Copyright (c) 2004, 2005 Jung-uk Kim <jkim@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD: releng/11.2/sys/dev/agp/agp_amd64.c 331722 2018-03-29 02:50:57Z eadler $"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/malloc.h> 33 #include <sys/kernel.h> 34 #include <sys/module.h> 35 #include <sys/bus.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/proc.h> 39 40 #include <dev/agp/agppriv.h> 41 #include <dev/agp/agpreg.h> 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcireg.h> 44 45 #include <vm/vm.h> 46 #include <vm/vm_object.h> 47 #include <vm/pmap.h> 48 #include <machine/bus.h> 49 #include <machine/resource.h> 50 #include <sys/rman.h> 51 52 /* XXX */ 53 extern void pci_cfgregwrite(int, int, int, int, uint32_t, int); 54 extern uint32_t pci_cfgregread(int, int, int, int, int); 55 56 static void agp_amd64_apbase_fixup(device_t); 57 58 static void agp_amd64_uli_init(device_t); 59 static int agp_amd64_uli_set_aperture(device_t, uint32_t); 60 61 static int agp_amd64_nvidia_match(uint16_t); 62 static void agp_amd64_nvidia_init(device_t); 63 static int agp_amd64_nvidia_set_aperture(device_t, uint32_t); 64 65 static int agp_amd64_via_match(void); 66 static void agp_amd64_via_init(device_t); 67 static int agp_amd64_via_set_aperture(device_t, uint32_t); 68 69 MALLOC_DECLARE(M_AGP); 70 71 #define AMD64_MAX_MCTRL 8 72 73 struct agp_amd64_softc { 74 struct agp_softc agp; 75 uint32_t initial_aperture; 76 struct agp_gatt *gatt; 77 uint32_t apbase; 78 int mctrl[AMD64_MAX_MCTRL]; 79 int n_mctrl; 80 int via_agp; 81 }; 82 83 static const char* 84 agp_amd64_match(device_t dev) 85 { 86 if (pci_get_class(dev) != PCIC_BRIDGE || 87 pci_get_subclass(dev) != PCIS_BRIDGE_HOST || 88 agp_find_caps(dev) == 0) 89 return (NULL); 90 91 switch (pci_get_devid(dev)) { 92 case 0x74541022: 93 return ("AMD 8151 AGP graphics tunnel"); 94 case 0x07551039: 95 return ("SiS 755 host to AGP bridge"); 96 case 0x07601039: 97 return ("SiS 760 host to AGP bridge"); 98 case 0x168910b9: 99 return ("ULi M1689 AGP Controller"); 100 case 0x00d110de: 101 if (agp_amd64_nvidia_match(0x00d2)) 102 return (NULL); 103 return ("NVIDIA nForce3 AGP Controller"); 104 case 0x00e110de: 105 if (agp_amd64_nvidia_match(0x00e2)) 106 return (NULL); 107 return ("NVIDIA nForce3-250 AGP Controller"); 108 case 0x02041106: 109 return ("VIA 8380 host to PCI bridge"); 110 case 0x02381106: 111 return ("VIA 3238 host to PCI bridge"); 112 case 0x02821106: 113 return ("VIA K8T800Pro host to PCI bridge"); 114 case 0x31881106: 115 return ("VIA 8385 host to PCI bridge"); 116 } 117 118 return (NULL); 119 } 120 121 static int 122 agp_amd64_nvidia_match(uint16_t devid) 123 { 124 /* XXX nForce3 requires secondary AGP bridge at 0:11:0. */ 125 if (pci_cfgregread(0, 11, 0, PCIR_CLASS, 1) != PCIC_BRIDGE || 126 pci_cfgregread(0, 11, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI || 127 pci_cfgregread(0, 11, 0, PCIR_VENDOR, 2) != 0x10de || 128 pci_cfgregread(0, 11, 0, PCIR_DEVICE, 2) != devid) 129 return (ENXIO); 130 131 return (0); 132 } 133 134 static int 135 agp_amd64_via_match(void) 136 { 137 /* XXX Some VIA bridge requires secondary AGP bridge at 0:1:0. */ 138 if (pci_cfgregread(0, 1, 0, PCIR_CLASS, 1) != PCIC_BRIDGE || 139 pci_cfgregread(0, 1, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI || 140 pci_cfgregread(0, 1, 0, PCIR_VENDOR, 2) != 0x1106 || 141 pci_cfgregread(0, 1, 0, PCIR_DEVICE, 2) != 0xb188 || 142 (pci_cfgregread(0, 1, 0, AGP_VIA_AGPSEL, 1) & 2)) 143 return (0); 144 145 return (1); 146 } 147 148 static int 149 agp_amd64_probe(device_t dev) 150 { 151 const char *desc; 152 153 if (resource_disabled("agp", device_get_unit(dev))) 154 return (ENXIO); 155 if ((desc = agp_amd64_match(dev))) { 156 device_set_desc(dev, desc); 157 return (BUS_PROBE_DEFAULT); 158 } 159 160 return (ENXIO); 161 } 162 163 static int 164 agp_amd64_attach(device_t dev) 165 { 166 struct agp_amd64_softc *sc = device_get_softc(dev); 167 struct agp_gatt *gatt; 168 uint32_t devid; 169 int i, n, error; 170 171 for (i = 0, n = 0; i < PCI_SLOTMAX && n < AMD64_MAX_MCTRL; i++) { 172 devid = pci_cfgregread(0, i, 3, 0, 4); 173 if (devid == 0x11031022 || devid == 0x12031022) { 174 sc->mctrl[n] = i; 175 n++; 176 } 177 } 178 if (n == 0) 179 return (ENXIO); 180 181 sc->n_mctrl = n; 182 183 if (bootverbose) 184 device_printf(dev, "%d Miscellaneous Control unit(s) found.\n", 185 sc->n_mctrl); 186 187 if ((error = agp_generic_attach(dev))) 188 return (error); 189 190 sc->initial_aperture = AGP_GET_APERTURE(dev); 191 192 for (;;) { 193 gatt = agp_alloc_gatt(dev); 194 if (gatt) 195 break; 196 197 /* 198 * Probably contigmalloc failure. Try reducing the 199 * aperture so that the gatt size reduces. 200 */ 201 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) { 202 agp_generic_detach(dev); 203 return (ENOMEM); 204 } 205 } 206 sc->gatt = gatt; 207 208 switch (pci_get_vendor(dev)) { 209 case 0x10b9: /* ULi */ 210 agp_amd64_uli_init(dev); 211 if (agp_amd64_uli_set_aperture(dev, sc->initial_aperture)) 212 return (ENXIO); 213 break; 214 215 case 0x10de: /* nVidia */ 216 agp_amd64_nvidia_init(dev); 217 if (agp_amd64_nvidia_set_aperture(dev, sc->initial_aperture)) 218 return (ENXIO); 219 break; 220 221 case 0x1106: /* VIA */ 222 sc->via_agp = agp_amd64_via_match(); 223 if (sc->via_agp) { 224 agp_amd64_via_init(dev); 225 if (agp_amd64_via_set_aperture(dev, 226 sc->initial_aperture)) 227 return (ENXIO); 228 } 229 break; 230 } 231 232 /* Install the gatt and enable aperture. */ 233 for (i = 0; i < sc->n_mctrl; i++) { 234 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_ATTBASE, 235 (uint32_t)(gatt->ag_physical >> 8) & AGP_AMD64_ATTBASE_MASK, 236 4); 237 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 238 (pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) | 239 AGP_AMD64_APCTRL_GARTEN) & 240 ~(AGP_AMD64_APCTRL_DISGARTCPU | AGP_AMD64_APCTRL_DISGARTIO), 241 4); 242 } 243 244 return (0); 245 } 246 247 static int 248 agp_amd64_detach(device_t dev) 249 { 250 struct agp_amd64_softc *sc = device_get_softc(dev); 251 int i; 252 253 agp_free_cdev(dev); 254 255 for (i = 0; i < sc->n_mctrl; i++) 256 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 257 pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) & 258 ~AGP_AMD64_APCTRL_GARTEN, 4); 259 260 AGP_SET_APERTURE(dev, sc->initial_aperture); 261 agp_free_gatt(sc->gatt); 262 agp_free_res(dev); 263 264 return (0); 265 } 266 267 static uint32_t agp_amd64_table[] = { 268 0x02000000, /* 32 MB */ 269 0x04000000, /* 64 MB */ 270 0x08000000, /* 128 MB */ 271 0x10000000, /* 256 MB */ 272 0x20000000, /* 512 MB */ 273 0x40000000, /* 1024 MB */ 274 0x80000000, /* 2048 MB */ 275 }; 276 277 #define AGP_AMD64_TABLE_SIZE nitems(agp_amd64_table) 278 279 static uint32_t 280 agp_amd64_get_aperture(device_t dev) 281 { 282 struct agp_amd64_softc *sc = device_get_softc(dev); 283 uint32_t i; 284 285 i = (pci_cfgregread(0, sc->mctrl[0], 3, AGP_AMD64_APCTRL, 4) & 286 AGP_AMD64_APCTRL_SIZE_MASK) >> 1; 287 288 if (i >= AGP_AMD64_TABLE_SIZE) 289 return (0); 290 291 return (agp_amd64_table[i]); 292 } 293 294 static int 295 agp_amd64_set_aperture(device_t dev, uint32_t aperture) 296 { 297 struct agp_amd64_softc *sc = device_get_softc(dev); 298 uint32_t i; 299 int j; 300 301 for (i = 0; i < AGP_AMD64_TABLE_SIZE; i++) 302 if (agp_amd64_table[i] == aperture) 303 break; 304 if (i >= AGP_AMD64_TABLE_SIZE) 305 return (EINVAL); 306 307 for (j = 0; j < sc->n_mctrl; j++) 308 pci_cfgregwrite(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL, 309 (pci_cfgregread(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL, 4) & 310 ~(AGP_AMD64_APCTRL_SIZE_MASK)) | (i << 1), 4); 311 312 switch (pci_get_vendor(dev)) { 313 case 0x10b9: /* ULi */ 314 return (agp_amd64_uli_set_aperture(dev, aperture)); 315 break; 316 317 case 0x10de: /* nVidia */ 318 return (agp_amd64_nvidia_set_aperture(dev, aperture)); 319 break; 320 321 case 0x1106: /* VIA */ 322 if (sc->via_agp) 323 return (agp_amd64_via_set_aperture(dev, aperture)); 324 break; 325 } 326 327 return (0); 328 } 329 330 static int 331 agp_amd64_bind_page(device_t dev, vm_offset_t offset, vm_offset_t physical) 332 { 333 struct agp_amd64_softc *sc = device_get_softc(dev); 334 335 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 336 return (EINVAL); 337 338 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 339 (physical & 0xfffff000) | ((physical >> 28) & 0x00000ff0) | 3; 340 341 return (0); 342 } 343 344 static int 345 agp_amd64_unbind_page(device_t dev, vm_offset_t offset) 346 { 347 struct agp_amd64_softc *sc = device_get_softc(dev); 348 349 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 350 return (EINVAL); 351 352 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 353 354 return (0); 355 } 356 357 static void 358 agp_amd64_flush_tlb(device_t dev) 359 { 360 struct agp_amd64_softc *sc = device_get_softc(dev); 361 int i; 362 363 for (i = 0; i < sc->n_mctrl; i++) 364 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL, 365 pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL, 4) | 366 AGP_AMD64_CACHECTRL_INVGART, 4); 367 } 368 369 static void 370 agp_amd64_apbase_fixup(device_t dev) 371 { 372 struct agp_amd64_softc *sc = device_get_softc(dev); 373 uint32_t apbase; 374 int i; 375 376 sc->apbase = rman_get_start(sc->agp.as_aperture); 377 apbase = (sc->apbase >> 25) & AGP_AMD64_APBASE_MASK; 378 for (i = 0; i < sc->n_mctrl; i++) 379 pci_cfgregwrite(0, sc->mctrl[i], 3, 380 AGP_AMD64_APBASE, apbase, 4); 381 } 382 383 static void 384 agp_amd64_uli_init(device_t dev) 385 { 386 struct agp_amd64_softc *sc = device_get_softc(dev); 387 388 agp_amd64_apbase_fixup(dev); 389 pci_write_config(dev, AGP_AMD64_ULI_APBASE, 390 (pci_read_config(dev, AGP_AMD64_ULI_APBASE, 4) & 0x0000000f) | 391 sc->apbase, 4); 392 pci_write_config(dev, AGP_AMD64_ULI_HTT_FEATURE, sc->apbase, 4); 393 } 394 395 static int 396 agp_amd64_uli_set_aperture(device_t dev, uint32_t aperture) 397 { 398 struct agp_amd64_softc *sc = device_get_softc(dev); 399 400 switch (aperture) { 401 case 0x02000000: /* 32 MB */ 402 case 0x04000000: /* 64 MB */ 403 case 0x08000000: /* 128 MB */ 404 case 0x10000000: /* 256 MB */ 405 break; 406 default: 407 return (EINVAL); 408 } 409 410 pci_write_config(dev, AGP_AMD64_ULI_ENU_SCR, 411 sc->apbase + aperture - 1, 4); 412 413 return (0); 414 } 415 416 static void 417 agp_amd64_nvidia_init(device_t dev) 418 { 419 struct agp_amd64_softc *sc = device_get_softc(dev); 420 421 agp_amd64_apbase_fixup(dev); 422 pci_write_config(dev, AGP_AMD64_NVIDIA_0_APBASE, 423 (pci_read_config(dev, AGP_AMD64_NVIDIA_0_APBASE, 4) & 0x0000000f) | 424 sc->apbase, 4); 425 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE1, sc->apbase, 4); 426 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE2, sc->apbase, 4); 427 } 428 429 static int 430 agp_amd64_nvidia_set_aperture(device_t dev, uint32_t aperture) 431 { 432 struct agp_amd64_softc *sc = device_get_softc(dev); 433 uint32_t apsize; 434 435 switch (aperture) { 436 case 0x02000000: apsize = 0x0f; break; /* 32 MB */ 437 case 0x04000000: apsize = 0x0e; break; /* 64 MB */ 438 case 0x08000000: apsize = 0x0c; break; /* 128 MB */ 439 case 0x10000000: apsize = 0x08; break; /* 256 MB */ 440 case 0x20000000: apsize = 0x00; break; /* 512 MB */ 441 default: 442 return (EINVAL); 443 } 444 445 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE, 446 (pci_cfgregread(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE, 4) & 447 0xfffffff0) | apsize, 4); 448 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT1, 449 sc->apbase + aperture - 1, 4); 450 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT2, 451 sc->apbase + aperture - 1, 4); 452 453 return (0); 454 } 455 456 static void 457 agp_amd64_via_init(device_t dev) 458 { 459 struct agp_amd64_softc *sc = device_get_softc(dev); 460 461 agp_amd64_apbase_fixup(dev); 462 pci_cfgregwrite(0, 1, 0, AGP3_VIA_ATTBASE, sc->gatt->ag_physical, 4); 463 pci_cfgregwrite(0, 1, 0, AGP3_VIA_GARTCTRL, 464 pci_cfgregread(0, 1, 0, AGP3_VIA_ATTBASE, 4) | 0x180, 4); 465 } 466 467 static int 468 agp_amd64_via_set_aperture(device_t dev, uint32_t aperture) 469 { 470 uint32_t apsize; 471 472 apsize = ((aperture - 1) >> 20) ^ 0xff; 473 if ((((apsize ^ 0xff) << 20) | ((1 << 20) - 1)) + 1 != aperture) 474 return (EINVAL); 475 pci_cfgregwrite(0, 1, 0, AGP3_VIA_APSIZE, apsize, 1); 476 477 return (0); 478 } 479 480 static device_method_t agp_amd64_methods[] = { 481 /* Device interface */ 482 DEVMETHOD(device_probe, agp_amd64_probe), 483 DEVMETHOD(device_attach, agp_amd64_attach), 484 DEVMETHOD(device_detach, agp_amd64_detach), 485 DEVMETHOD(device_shutdown, bus_generic_shutdown), 486 DEVMETHOD(device_suspend, bus_generic_suspend), 487 DEVMETHOD(device_resume, bus_generic_resume), 488 489 /* AGP interface */ 490 DEVMETHOD(agp_get_aperture, agp_amd64_get_aperture), 491 DEVMETHOD(agp_set_aperture, agp_amd64_set_aperture), 492 DEVMETHOD(agp_bind_page, agp_amd64_bind_page), 493 DEVMETHOD(agp_unbind_page, agp_amd64_unbind_page), 494 DEVMETHOD(agp_flush_tlb, agp_amd64_flush_tlb), 495 DEVMETHOD(agp_enable, agp_generic_enable), 496 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory), 497 DEVMETHOD(agp_free_memory, agp_generic_free_memory), 498 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory), 499 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory), 500 501 { 0, 0 } 502 }; 503 504 static driver_t agp_amd64_driver = { 505 "agp", 506 agp_amd64_methods, 507 sizeof(struct agp_amd64_softc), 508 }; 509 510 static devclass_t agp_devclass; 511 512 DRIVER_MODULE(agp_amd64, hostb, agp_amd64_driver, agp_devclass, 0, 0); 513 MODULE_DEPEND(agp_amd64, agp, 1, 1, 1); 514 MODULE_DEPEND(agp_amd64, pci, 1, 1, 1);
Cache object: 254c9411ac39e09b61ca8d3258a49e04
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