FreeBSD/Linux Kernel Cross Reference
sys/dev/agp/agp_i810.c
1 /*-
2 * Copyright (c) 2000 Doug Rabson
3 * Copyright (c) 2000 Ruslan Ermilov
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28 /*
29 * Fixes for 830/845G support: David Dawes <dawes@xfree86.org>
30 * 852GM/855GM/865G support added by David Dawes <dawes@xfree86.org>
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD: releng/8.1/sys/dev/agp/agp_i810.c 206164 2010-04-04 15:37:47Z rnoland $");
35
36 #include "opt_bus.h"
37
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/malloc.h>
41 #include <sys/kernel.h>
42 #include <sys/module.h>
43 #include <sys/bus.h>
44 #include <sys/lock.h>
45 #include <sys/mutex.h>
46 #include <sys/proc.h>
47
48 #include <dev/agp/agppriv.h>
49 #include <dev/agp/agpreg.h>
50 #include <dev/pci/pcivar.h>
51 #include <dev/pci/pcireg.h>
52
53 #include <vm/vm.h>
54 #include <vm/vm_object.h>
55 #include <vm/vm_page.h>
56 #include <vm/vm_pageout.h>
57 #include <vm/pmap.h>
58
59 #include <machine/bus.h>
60 #include <machine/resource.h>
61 #include <machine/md_var.h>
62 #include <sys/rman.h>
63
64 MALLOC_DECLARE(M_AGP);
65
66 enum {
67 CHIP_I810, /* i810/i815 */
68 CHIP_I830, /* 830M/845G */
69 CHIP_I855, /* 852GM/855GM/865G */
70 CHIP_I915, /* 915G/915GM */
71 CHIP_I965, /* G965 */
72 CHIP_G33, /* G33/Q33/Q35 */
73 CHIP_IGD, /* Pineview */
74 CHIP_G4X, /* G45/Q45 */
75 };
76
77 /* The i810 through i855 have the registers at BAR 1, and the GATT gets
78 * allocated by us. The i915 has registers in BAR 0 and the GATT is at the
79 * start of the stolen memory, and should only be accessed by the OS through
80 * BAR 3. The G965 has registers and GATT in the same BAR (0) -- first 512KB
81 * is registers, second 512KB is GATT.
82 */
83 static struct resource_spec agp_i810_res_spec[] = {
84 { SYS_RES_MEMORY, AGP_I810_MMADR, RF_ACTIVE | RF_SHAREABLE },
85 { -1, 0 }
86 };
87
88 static struct resource_spec agp_i915_res_spec[] = {
89 { SYS_RES_MEMORY, AGP_I915_MMADR, RF_ACTIVE | RF_SHAREABLE },
90 { SYS_RES_MEMORY, AGP_I915_GTTADR, RF_ACTIVE | RF_SHAREABLE },
91 { -1, 0 }
92 };
93
94 static struct resource_spec agp_i965_res_spec[] = {
95 { SYS_RES_MEMORY, AGP_I965_GTTMMADR, RF_ACTIVE | RF_SHAREABLE },
96 { -1, 0 }
97 };
98
99 struct agp_i810_softc {
100 struct agp_softc agp;
101 u_int32_t initial_aperture; /* aperture size at startup */
102 struct agp_gatt *gatt;
103 int chiptype; /* i810-like or i830 */
104 u_int32_t dcache_size; /* i810 only */
105 u_int32_t stolen; /* number of i830/845 gtt entries for stolen memory */
106 device_t bdev; /* bridge device */
107
108 void *argb_cursor; /* contigmalloc area for ARGB cursor */
109
110 struct resource_spec * sc_res_spec;
111 struct resource *sc_res[2];
112 };
113
114 /* For adding new devices, devid is the id of the graphics controller
115 * (pci:0:2:0, for example). The placeholder (usually at pci:0:2:1) for the
116 * second head should never be added. The bridge_offset is the offset to
117 * subtract from devid to get the id of the hostb that the device is on.
118 */
119 static const struct agp_i810_match {
120 int devid;
121 int chiptype;
122 int bridge_offset;
123 char *name;
124 } agp_i810_matches[] = {
125 {0x71218086, CHIP_I810, 0x00010000,
126 "Intel 82810 (i810 GMCH) SVGA controller"},
127 {0x71238086, CHIP_I810, 0x00010000,
128 "Intel 82810-DC100 (i810-DC100 GMCH) SVGA controller"},
129 {0x71258086, CHIP_I810, 0x00010000,
130 "Intel 82810E (i810E GMCH) SVGA controller"},
131 {0x11328086, CHIP_I810, 0x00020000,
132 "Intel 82815 (i815 GMCH) SVGA controller"},
133 {0x35778086, CHIP_I830, 0x00020000,
134 "Intel 82830M (830M GMCH) SVGA controller"},
135 {0x25628086, CHIP_I830, 0x00020000,
136 "Intel 82845M (845M GMCH) SVGA controller"},
137 {0x35828086, CHIP_I855, 0x00020000,
138 "Intel 82852/855GM SVGA controller"},
139 {0x25728086, CHIP_I855, 0x00020000,
140 "Intel 82865G (865G GMCH) SVGA controller"},
141 {0x25828086, CHIP_I915, 0x00020000,
142 "Intel 82915G (915G GMCH) SVGA controller"},
143 {0x258A8086, CHIP_I915, 0x00020000,
144 "Intel E7221 SVGA controller"},
145 {0x25928086, CHIP_I915, 0x00020000,
146 "Intel 82915GM (915GM GMCH) SVGA controller"},
147 {0x27728086, CHIP_I915, 0x00020000,
148 "Intel 82945G (945G GMCH) SVGA controller"},
149 {0x27A28086, CHIP_I915, 0x00020000,
150 "Intel 82945GM (945GM GMCH) SVGA controller"},
151 {0x27AE8086, CHIP_I915, 0x00020000,
152 "Intel 945GME SVGA controller"},
153 {0x29728086, CHIP_I965, 0x00020000,
154 "Intel 946GZ SVGA controller"},
155 {0x29828086, CHIP_I965, 0x00020000,
156 "Intel G965 SVGA controller"},
157 {0x29928086, CHIP_I965, 0x00020000,
158 "Intel Q965 SVGA controller"},
159 {0x29A28086, CHIP_I965, 0x00020000,
160 "Intel G965 SVGA controller"},
161 {0x29B28086, CHIP_G33, 0x00020000,
162 "Intel Q35 SVGA controller"},
163 {0x29C28086, CHIP_G33, 0x00020000,
164 "Intel G33 SVGA controller"},
165 {0x29D28086, CHIP_G33, 0x00020000,
166 "Intel Q33 SVGA controller"},
167 {0xA0018086, CHIP_IGD, 0x00010000,
168 "Intel Pineview SVGA controller"},
169 {0xA0118086, CHIP_IGD, 0x00010000,
170 "Intel Pineview (M) SVGA controller"},
171 {0x2A028086, CHIP_I965, 0x00020000,
172 "Intel GM965 SVGA controller"},
173 {0x2A128086, CHIP_I965, 0x00020000,
174 "Intel GME965 SVGA controller"},
175 {0x2A428086, CHIP_G4X, 0x00020000,
176 "Intel GM45 SVGA controller"},
177 {0x2E028086, CHIP_G4X, 0x00020000,
178 "Intel Eaglelake SVGA controller"},
179 {0x2E128086, CHIP_G4X, 0x00020000,
180 "Intel Q45 SVGA controller"},
181 {0x2E228086, CHIP_G4X, 0x00020000,
182 "Intel G45 SVGA controller"},
183 {0x2E328086, CHIP_G4X, 0x00020000,
184 "Intel G41 SVGA controller"},
185 {0x00428086, CHIP_G4X, 0x00020000,
186 "Intel Ironlake (D) SVGA controller"},
187 {0x00468086, CHIP_G4X, 0x00020000,
188 "Intel Ironlake (M) SVGA controller"},
189 {0, 0, 0, NULL}
190 };
191
192 static const struct agp_i810_match*
193 agp_i810_match(device_t dev)
194 {
195 int i, devid;
196
197 if (pci_get_class(dev) != PCIC_DISPLAY
198 || pci_get_subclass(dev) != PCIS_DISPLAY_VGA)
199 return NULL;
200
201 devid = pci_get_devid(dev);
202 for (i = 0; agp_i810_matches[i].devid != 0; i++) {
203 if (agp_i810_matches[i].devid == devid)
204 break;
205 }
206 if (agp_i810_matches[i].devid == 0)
207 return NULL;
208 else
209 return &agp_i810_matches[i];
210 }
211
212 /*
213 * Find bridge device.
214 */
215 static device_t
216 agp_i810_find_bridge(device_t dev)
217 {
218 device_t *children, child;
219 int nchildren, i;
220 u_int32_t devid;
221 const struct agp_i810_match *match;
222
223 match = agp_i810_match(dev);
224 devid = match->devid - match->bridge_offset;
225
226 if (device_get_children(device_get_parent(device_get_parent(dev)),
227 &children, &nchildren))
228 return 0;
229
230 for (i = 0; i < nchildren; i++) {
231 child = children[i];
232
233 if (pci_get_devid(child) == devid) {
234 free(children, M_TEMP);
235 return child;
236 }
237 }
238 free(children, M_TEMP);
239 return 0;
240 }
241
242 static void
243 agp_i810_identify(driver_t *driver, device_t parent)
244 {
245
246 if (device_find_child(parent, "agp", -1) == NULL &&
247 agp_i810_match(parent))
248 device_add_child(parent, "agp", -1);
249 }
250
251 static int
252 agp_i810_probe(device_t dev)
253 {
254 device_t bdev;
255 const struct agp_i810_match *match;
256 u_int8_t smram;
257 int gcc1, deven;
258
259 if (resource_disabled("agp", device_get_unit(dev)))
260 return (ENXIO);
261 match = agp_i810_match(dev);
262 if (match == NULL)
263 return ENXIO;
264
265 bdev = agp_i810_find_bridge(dev);
266 if (!bdev) {
267 if (bootverbose)
268 printf("I810: can't find bridge device\n");
269 return ENXIO;
270 }
271
272 /*
273 * checking whether internal graphics device has been activated.
274 */
275 switch (match->chiptype) {
276 case CHIP_I810:
277 smram = pci_read_config(bdev, AGP_I810_SMRAM, 1);
278 if ((smram & AGP_I810_SMRAM_GMS) ==
279 AGP_I810_SMRAM_GMS_DISABLED) {
280 if (bootverbose)
281 printf("I810: disabled, not probing\n");
282 return ENXIO;
283 }
284 break;
285 case CHIP_I830:
286 case CHIP_I855:
287 gcc1 = pci_read_config(bdev, AGP_I830_GCC1, 1);
288 if ((gcc1 & AGP_I830_GCC1_DEV2) ==
289 AGP_I830_GCC1_DEV2_DISABLED) {
290 if (bootverbose)
291 printf("I830: disabled, not probing\n");
292 return ENXIO;
293 }
294 break;
295 case CHIP_I915:
296 case CHIP_I965:
297 case CHIP_G33:
298 case CHIP_IGD:
299 case CHIP_G4X:
300 deven = pci_read_config(bdev, AGP_I915_DEVEN, 4);
301 if ((deven & AGP_I915_DEVEN_D2F0) ==
302 AGP_I915_DEVEN_D2F0_DISABLED) {
303 if (bootverbose)
304 printf("I915: disabled, not probing\n");
305 return ENXIO;
306 }
307 break;
308 }
309
310 if (match->devid == 0x35828086) {
311 switch (pci_read_config(dev, AGP_I85X_CAPID, 1)) {
312 case AGP_I855_GME:
313 device_set_desc(dev,
314 "Intel 82855GME (855GME GMCH) SVGA controller");
315 break;
316 case AGP_I855_GM:
317 device_set_desc(dev,
318 "Intel 82855GM (855GM GMCH) SVGA controller");
319 break;
320 case AGP_I852_GME:
321 device_set_desc(dev,
322 "Intel 82852GME (852GME GMCH) SVGA controller");
323 break;
324 case AGP_I852_GM:
325 device_set_desc(dev,
326 "Intel 82852GM (852GM GMCH) SVGA controller");
327 break;
328 default:
329 device_set_desc(dev,
330 "Intel 8285xM (85xGM GMCH) SVGA controller");
331 break;
332 }
333 } else {
334 device_set_desc(dev, match->name);
335 }
336
337 return BUS_PROBE_DEFAULT;
338 }
339
340 static void
341 agp_i810_dump_regs(device_t dev)
342 {
343 struct agp_i810_softc *sc = device_get_softc(dev);
344
345 device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n",
346 bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL));
347
348 switch (sc->chiptype) {
349 case CHIP_I810:
350 device_printf(dev, "AGP_I810_MISCC: 0x%04x\n",
351 pci_read_config(sc->bdev, AGP_I810_MISCC, 2));
352 break;
353 case CHIP_I830:
354 device_printf(dev, "AGP_I830_GCC1: 0x%02x\n",
355 pci_read_config(sc->bdev, AGP_I830_GCC1, 1));
356 break;
357 case CHIP_I855:
358 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
359 pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
360 break;
361 case CHIP_I915:
362 case CHIP_I965:
363 case CHIP_G33:
364 case CHIP_IGD:
365 case CHIP_G4X:
366 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
367 pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
368 device_printf(dev, "AGP_I915_MSAC: 0x%02x\n",
369 pci_read_config(sc->bdev, AGP_I915_MSAC, 1));
370 break;
371 }
372 device_printf(dev, "Aperture resource size: %d bytes\n",
373 AGP_GET_APERTURE(dev));
374 }
375
376 static int
377 agp_i810_attach(device_t dev)
378 {
379 struct agp_i810_softc *sc = device_get_softc(dev);
380 struct agp_gatt *gatt;
381 const struct agp_i810_match *match;
382 int error;
383
384 sc->bdev = agp_i810_find_bridge(dev);
385 if (!sc->bdev)
386 return ENOENT;
387
388 match = agp_i810_match(dev);
389 sc->chiptype = match->chiptype;
390
391 switch (sc->chiptype) {
392 case CHIP_I810:
393 case CHIP_I830:
394 case CHIP_I855:
395 sc->sc_res_spec = agp_i810_res_spec;
396 agp_set_aperture_resource(dev, AGP_APBASE);
397 break;
398 case CHIP_I915:
399 case CHIP_G33:
400 case CHIP_IGD:
401 sc->sc_res_spec = agp_i915_res_spec;
402 agp_set_aperture_resource(dev, AGP_I915_GMADR);
403 break;
404 case CHIP_I965:
405 case CHIP_G4X:
406 sc->sc_res_spec = agp_i965_res_spec;
407 agp_set_aperture_resource(dev, AGP_I915_GMADR);
408 break;
409 }
410
411 error = agp_generic_attach(dev);
412 if (error)
413 return error;
414
415 if (sc->chiptype != CHIP_I965 && sc->chiptype != CHIP_G33 &&
416 sc->chiptype != CHIP_IGD && sc->chiptype != CHIP_G4X &&
417 ptoa((vm_paddr_t)Maxmem) > 0xfffffffful)
418 {
419 device_printf(dev, "agp_i810.c does not support physical "
420 "memory above 4GB.\n");
421 return ENOENT;
422 }
423
424 if (bus_alloc_resources(dev, sc->sc_res_spec, sc->sc_res)) {
425 agp_generic_detach(dev);
426 return ENODEV;
427 }
428
429 sc->initial_aperture = AGP_GET_APERTURE(dev);
430
431 gatt = malloc( sizeof(struct agp_gatt), M_AGP, M_NOWAIT);
432 if (!gatt) {
433 bus_release_resources(dev, sc->sc_res_spec, sc->sc_res);
434 agp_generic_detach(dev);
435 return ENOMEM;
436 }
437 sc->gatt = gatt;
438
439 gatt->ag_entries = AGP_GET_APERTURE(dev) >> AGP_PAGE_SHIFT;
440
441 if ( sc->chiptype == CHIP_I810 ) {
442 /* Some i810s have on-chip memory called dcache */
443 if (bus_read_1(sc->sc_res[0], AGP_I810_DRT) &
444 AGP_I810_DRT_POPULATED)
445 sc->dcache_size = 4 * 1024 * 1024;
446 else
447 sc->dcache_size = 0;
448
449 /* According to the specs the gatt on the i810 must be 64k */
450 gatt->ag_virtual = contigmalloc( 64 * 1024, M_AGP, 0,
451 0, ~0, PAGE_SIZE, 0);
452 if (!gatt->ag_virtual) {
453 if (bootverbose)
454 device_printf(dev, "contiguous allocation failed\n");
455 bus_release_resources(dev, sc->sc_res_spec,
456 sc->sc_res);
457 free(gatt, M_AGP);
458 agp_generic_detach(dev);
459 return ENOMEM;
460 }
461 bzero(gatt->ag_virtual, gatt->ag_entries * sizeof(u_int32_t));
462
463 gatt->ag_physical = vtophys((vm_offset_t) gatt->ag_virtual);
464 agp_flush_cache();
465 /* Install the GATT. */
466 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
467 gatt->ag_physical | 1);
468 } else if ( sc->chiptype == CHIP_I830 ) {
469 /* The i830 automatically initializes the 128k gatt on boot. */
470 unsigned int gcc1, pgtblctl;
471
472 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 1);
473 switch (gcc1 & AGP_I830_GCC1_GMS) {
474 case AGP_I830_GCC1_GMS_STOLEN_512:
475 sc->stolen = (512 - 132) * 1024 / 4096;
476 break;
477 case AGP_I830_GCC1_GMS_STOLEN_1024:
478 sc->stolen = (1024 - 132) * 1024 / 4096;
479 break;
480 case AGP_I830_GCC1_GMS_STOLEN_8192:
481 sc->stolen = (8192 - 132) * 1024 / 4096;
482 break;
483 default:
484 sc->stolen = 0;
485 device_printf(dev, "unknown memory configuration, disabling\n");
486 bus_release_resources(dev, sc->sc_res_spec,
487 sc->sc_res);
488 free(gatt, M_AGP);
489 agp_generic_detach(dev);
490 return EINVAL;
491 }
492 if (sc->stolen > 0) {
493 device_printf(dev, "detected %dk stolen memory\n",
494 sc->stolen * 4);
495 }
496 device_printf(dev, "aperture size is %dM\n",
497 sc->initial_aperture / 1024 / 1024);
498
499 /* GATT address is already in there, make sure it's enabled */
500 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
501 pgtblctl |= 1;
502 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
503
504 gatt->ag_physical = pgtblctl & ~1;
505 } else if (sc->chiptype == CHIP_I855 || sc->chiptype == CHIP_I915 ||
506 sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33 ||
507 sc->chiptype == CHIP_IGD || sc->chiptype == CHIP_G4X) {
508 unsigned int gcc1, pgtblctl, stolen, gtt_size;
509
510 /* Stolen memory is set up at the beginning of the aperture by
511 * the BIOS, consisting of the GATT followed by 4kb for the
512 * BIOS display.
513 */
514 switch (sc->chiptype) {
515 case CHIP_I855:
516 gtt_size = 128;
517 break;
518 case CHIP_I915:
519 gtt_size = 256;
520 break;
521 case CHIP_I965:
522 switch (bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL) &
523 AGP_I810_PGTBL_SIZE_MASK) {
524 case AGP_I810_PGTBL_SIZE_128KB:
525 gtt_size = 128;
526 break;
527 case AGP_I810_PGTBL_SIZE_256KB:
528 gtt_size = 256;
529 break;
530 case AGP_I810_PGTBL_SIZE_512KB:
531 gtt_size = 512;
532 break;
533 case AGP_I965_PGTBL_SIZE_1MB:
534 gtt_size = 1024;
535 break;
536 case AGP_I965_PGTBL_SIZE_2MB:
537 gtt_size = 2048;
538 break;
539 case AGP_I965_PGTBL_SIZE_1_5MB:
540 gtt_size = 1024 + 512;
541 break;
542 default:
543 device_printf(dev, "Bad PGTBL size\n");
544 bus_release_resources(dev, sc->sc_res_spec,
545 sc->sc_res);
546 free(gatt, M_AGP);
547 agp_generic_detach(dev);
548 return EINVAL;
549 }
550 break;
551 case CHIP_G33:
552 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 2);
553 switch (gcc1 & AGP_G33_MGGC_GGMS_MASK) {
554 case AGP_G33_MGGC_GGMS_SIZE_1M:
555 gtt_size = 1024;
556 break;
557 case AGP_G33_MGGC_GGMS_SIZE_2M:
558 gtt_size = 2048;
559 break;
560 default:
561 device_printf(dev, "Bad PGTBL size\n");
562 bus_release_resources(dev, sc->sc_res_spec,
563 sc->sc_res);
564 free(gatt, M_AGP);
565 agp_generic_detach(dev);
566 return EINVAL;
567 }
568 break;
569 case CHIP_IGD:
570 case CHIP_G4X:
571 gtt_size = 0;
572 break;
573 default:
574 device_printf(dev, "Bad chiptype\n");
575 bus_release_resources(dev, sc->sc_res_spec,
576 sc->sc_res);
577 free(gatt, M_AGP);
578 agp_generic_detach(dev);
579 return EINVAL;
580 }
581
582 /* GCC1 is called MGGC on i915+ */
583 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 1);
584 switch (gcc1 & AGP_I855_GCC1_GMS) {
585 case AGP_I855_GCC1_GMS_STOLEN_1M:
586 stolen = 1024;
587 break;
588 case AGP_I855_GCC1_GMS_STOLEN_4M:
589 stolen = 4 * 1024;
590 break;
591 case AGP_I855_GCC1_GMS_STOLEN_8M:
592 stolen = 8 * 1024;
593 break;
594 case AGP_I855_GCC1_GMS_STOLEN_16M:
595 stolen = 16 * 1024;
596 break;
597 case AGP_I855_GCC1_GMS_STOLEN_32M:
598 stolen = 32 * 1024;
599 break;
600 case AGP_I915_GCC1_GMS_STOLEN_48M:
601 if (sc->chiptype == CHIP_I915 ||
602 sc->chiptype == CHIP_I965 ||
603 sc->chiptype == CHIP_G33 ||
604 sc->chiptype == CHIP_IGD ||
605 sc->chiptype == CHIP_G4X) {
606 stolen = 48 * 1024;
607 } else {
608 stolen = 0;
609 }
610 break;
611 case AGP_I915_GCC1_GMS_STOLEN_64M:
612 if (sc->chiptype == CHIP_I915 ||
613 sc->chiptype == CHIP_I965 ||
614 sc->chiptype == CHIP_G33 ||
615 sc->chiptype == CHIP_IGD ||
616 sc->chiptype == CHIP_G4X) {
617 stolen = 64 * 1024;
618 } else {
619 stolen = 0;
620 }
621 break;
622 case AGP_G33_GCC1_GMS_STOLEN_128M:
623 if (sc->chiptype == CHIP_I965 ||
624 sc->chiptype == CHIP_G33 ||
625 sc->chiptype == CHIP_IGD ||
626 sc->chiptype == CHIP_G4X) {
627 stolen = 128 * 1024;
628 } else {
629 stolen = 0;
630 }
631 break;
632 case AGP_G33_GCC1_GMS_STOLEN_256M:
633 if (sc->chiptype == CHIP_I965 ||
634 sc->chiptype == CHIP_G33 ||
635 sc->chiptype == CHIP_IGD ||
636 sc->chiptype == CHIP_G4X) {
637 stolen = 256 * 1024;
638 } else {
639 stolen = 0;
640 }
641 break;
642 case AGP_G4X_GCC1_GMS_STOLEN_96M:
643 if (sc->chiptype == CHIP_I965 ||
644 sc->chiptype == CHIP_G4X) {
645 stolen = 96 * 1024;
646 } else {
647 stolen = 0;
648 }
649 break;
650 case AGP_G4X_GCC1_GMS_STOLEN_160M:
651 if (sc->chiptype == CHIP_I965 ||
652 sc->chiptype == CHIP_G4X) {
653 stolen = 160 * 1024;
654 } else {
655 stolen = 0;
656 }
657 break;
658 case AGP_G4X_GCC1_GMS_STOLEN_224M:
659 if (sc->chiptype == CHIP_I965 ||
660 sc->chiptype == CHIP_G4X) {
661 stolen = 224 * 1024;
662 } else {
663 stolen = 0;
664 }
665 break;
666 case AGP_G4X_GCC1_GMS_STOLEN_352M:
667 if (sc->chiptype == CHIP_I965 ||
668 sc->chiptype == CHIP_G4X) {
669 stolen = 352 * 1024;
670 } else {
671 stolen = 0;
672 }
673 break;
674 default:
675 device_printf(dev, "unknown memory configuration, "
676 "disabling\n");
677 bus_release_resources(dev, sc->sc_res_spec,
678 sc->sc_res);
679 free(gatt, M_AGP);
680 agp_generic_detach(dev);
681 return EINVAL;
682 }
683
684 gtt_size += 4;
685
686 sc->stolen = (stolen - gtt_size) * 1024 / 4096;
687 if (sc->stolen > 0)
688 device_printf(dev, "detected %dk stolen memory\n", sc->stolen * 4);
689 device_printf(dev, "aperture size is %dM\n", sc->initial_aperture / 1024 / 1024);
690
691 /* GATT address is already in there, make sure it's enabled */
692 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
693 pgtblctl |= 1;
694 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
695
696 gatt->ag_physical = pgtblctl & ~1;
697 }
698
699 if (0)
700 agp_i810_dump_regs(dev);
701
702 return 0;
703 }
704
705 static int
706 agp_i810_detach(device_t dev)
707 {
708 struct agp_i810_softc *sc = device_get_softc(dev);
709
710 agp_free_cdev(dev);
711
712 /* Clear the GATT base. */
713 if ( sc->chiptype == CHIP_I810 ) {
714 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, 0);
715 } else {
716 unsigned int pgtblctl;
717 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
718 pgtblctl &= ~1;
719 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
720 }
721
722 /* Put the aperture back the way it started. */
723 AGP_SET_APERTURE(dev, sc->initial_aperture);
724
725 if ( sc->chiptype == CHIP_I810 ) {
726 contigfree(sc->gatt->ag_virtual, 64 * 1024, M_AGP);
727 }
728 free(sc->gatt, M_AGP);
729
730 bus_release_resources(dev, sc->sc_res_spec, sc->sc_res);
731 agp_free_res(dev);
732
733 return 0;
734 }
735
736 static int
737 agp_i810_resume(device_t dev)
738 {
739 struct agp_i810_softc *sc;
740 sc = device_get_softc(dev);
741
742 AGP_SET_APERTURE(dev, sc->initial_aperture);
743
744 /* Install the GATT. */
745 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
746 sc->gatt->ag_physical | 1);
747
748 return (bus_generic_resume(dev));
749 }
750
751 /**
752 * Sets the PCI resource size of the aperture on i830-class and below chipsets,
753 * while returning failure on later chipsets when an actual change is
754 * requested.
755 *
756 * This whole function is likely bogus, as the kernel would probably need to
757 * reconfigure the placement of the AGP aperture if a larger size is requested,
758 * which doesn't happen currently.
759 */
760 static int
761 agp_i810_set_aperture(device_t dev, u_int32_t aperture)
762 {
763 struct agp_i810_softc *sc = device_get_softc(dev);
764 u_int16_t miscc, gcc1;
765
766 switch (sc->chiptype) {
767 case CHIP_I810:
768 /*
769 * Double check for sanity.
770 */
771 if (aperture != 32 * 1024 * 1024 && aperture != 64 * 1024 * 1024) {
772 device_printf(dev, "bad aperture size %d\n", aperture);
773 return EINVAL;
774 }
775
776 miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2);
777 miscc &= ~AGP_I810_MISCC_WINSIZE;
778 if (aperture == 32 * 1024 * 1024)
779 miscc |= AGP_I810_MISCC_WINSIZE_32;
780 else
781 miscc |= AGP_I810_MISCC_WINSIZE_64;
782
783 pci_write_config(sc->bdev, AGP_I810_MISCC, miscc, 2);
784 break;
785 case CHIP_I830:
786 if (aperture != 64 * 1024 * 1024 &&
787 aperture != 128 * 1024 * 1024) {
788 device_printf(dev, "bad aperture size %d\n", aperture);
789 return EINVAL;
790 }
791 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2);
792 gcc1 &= ~AGP_I830_GCC1_GMASIZE;
793 if (aperture == 64 * 1024 * 1024)
794 gcc1 |= AGP_I830_GCC1_GMASIZE_64;
795 else
796 gcc1 |= AGP_I830_GCC1_GMASIZE_128;
797
798 pci_write_config(sc->bdev, AGP_I830_GCC1, gcc1, 2);
799 break;
800 case CHIP_I855:
801 case CHIP_I915:
802 case CHIP_I965:
803 case CHIP_G33:
804 case CHIP_IGD:
805 case CHIP_G4X:
806 return agp_generic_set_aperture(dev, aperture);
807 }
808
809 return 0;
810 }
811
812 /**
813 * Writes a GTT entry mapping the page at the given offset from the beginning
814 * of the aperture to the given physical address.
815 */
816 static void
817 agp_i810_write_gtt_entry(device_t dev, int offset, vm_offset_t physical,
818 int enabled)
819 {
820 struct agp_i810_softc *sc = device_get_softc(dev);
821 u_int32_t pte;
822
823 pte = (u_int32_t)physical | 1;
824 if (sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33 ||
825 sc->chiptype == CHIP_IGD || sc->chiptype == CHIP_G4X) {
826 pte |= (physical & 0x0000000f00000000ull) >> 28;
827 } else {
828 /* If we do actually have memory above 4GB on an older system,
829 * crash cleanly rather than scribble on system memory,
830 * so we know we need to fix it.
831 */
832 KASSERT((pte & 0x0000000f00000000ull) == 0,
833 (">4GB physical address in agp"));
834 }
835
836 switch (sc->chiptype) {
837 case CHIP_I810:
838 case CHIP_I830:
839 case CHIP_I855:
840 bus_write_4(sc->sc_res[0],
841 AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, pte);
842 break;
843 case CHIP_I915:
844 case CHIP_G33:
845 case CHIP_IGD:
846 bus_write_4(sc->sc_res[1],
847 (offset >> AGP_PAGE_SHIFT) * 4, pte);
848 break;
849 case CHIP_I965:
850 bus_write_4(sc->sc_res[0],
851 (offset >> AGP_PAGE_SHIFT) * 4 + (512 * 1024), pte);
852 break;
853 case CHIP_G4X:
854 bus_write_4(sc->sc_res[0],
855 (offset >> AGP_PAGE_SHIFT) * 4 + (2 * 1024 * 1024), pte);
856 break;
857 }
858 }
859
860 static int
861 agp_i810_bind_page(device_t dev, vm_offset_t offset, vm_offset_t physical)
862 {
863 struct agp_i810_softc *sc = device_get_softc(dev);
864
865 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) {
866 device_printf(dev, "failed: offset is 0x%08jx, shift is %d, entries is %d\n", (intmax_t)offset, AGP_PAGE_SHIFT, sc->gatt->ag_entries);
867 return EINVAL;
868 }
869
870 if ( sc->chiptype != CHIP_I810 ) {
871 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) {
872 device_printf(dev, "trying to bind into stolen memory");
873 return EINVAL;
874 }
875 }
876
877 agp_i810_write_gtt_entry(dev, offset, physical, 1);
878
879 return 0;
880 }
881
882 static int
883 agp_i810_unbind_page(device_t dev, vm_offset_t offset)
884 {
885 struct agp_i810_softc *sc = device_get_softc(dev);
886
887 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
888 return EINVAL;
889
890 if ( sc->chiptype != CHIP_I810 ) {
891 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) {
892 device_printf(dev, "trying to unbind from stolen memory");
893 return EINVAL;
894 }
895 }
896
897 agp_i810_write_gtt_entry(dev, offset, 0, 0);
898
899 return 0;
900 }
901
902 /*
903 * Writing via memory mapped registers already flushes all TLBs.
904 */
905 static void
906 agp_i810_flush_tlb(device_t dev)
907 {
908 }
909
910 static int
911 agp_i810_enable(device_t dev, u_int32_t mode)
912 {
913
914 return 0;
915 }
916
917 static struct agp_memory *
918 agp_i810_alloc_memory(device_t dev, int type, vm_size_t size)
919 {
920 struct agp_i810_softc *sc = device_get_softc(dev);
921 struct agp_memory *mem;
922
923 if ((size & (AGP_PAGE_SIZE - 1)) != 0)
924 return 0;
925
926 if (sc->agp.as_allocated + size > sc->agp.as_maxmem)
927 return 0;
928
929 if (type == 1) {
930 /*
931 * Mapping local DRAM into GATT.
932 */
933 if ( sc->chiptype != CHIP_I810 )
934 return 0;
935 if (size != sc->dcache_size)
936 return 0;
937 } else if (type == 2) {
938 /*
939 * Type 2 is the contiguous physical memory type, that hands
940 * back a physical address. This is used for cursors on i810.
941 * Hand back as many single pages with physical as the user
942 * wants, but only allow one larger allocation (ARGB cursor)
943 * for simplicity.
944 */
945 if (size != AGP_PAGE_SIZE) {
946 if (sc->argb_cursor != NULL)
947 return 0;
948
949 /* Allocate memory for ARGB cursor, if we can. */
950 sc->argb_cursor = contigmalloc(size, M_AGP,
951 0, 0, ~0, PAGE_SIZE, 0);
952 if (sc->argb_cursor == NULL)
953 return 0;
954 }
955 }
956
957 mem = malloc(sizeof *mem, M_AGP, M_WAITOK);
958 mem->am_id = sc->agp.as_nextid++;
959 mem->am_size = size;
960 mem->am_type = type;
961 if (type != 1 && (type != 2 || size == AGP_PAGE_SIZE))
962 mem->am_obj = vm_object_allocate(OBJT_DEFAULT,
963 atop(round_page(size)));
964 else
965 mem->am_obj = 0;
966
967 if (type == 2) {
968 if (size == AGP_PAGE_SIZE) {
969 /*
970 * Allocate and wire down the page now so that we can
971 * get its physical address.
972 */
973 vm_page_t m;
974
975 VM_OBJECT_LOCK(mem->am_obj);
976 m = vm_page_grab(mem->am_obj, 0, VM_ALLOC_NOBUSY |
977 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_RETRY);
978 VM_OBJECT_UNLOCK(mem->am_obj);
979 mem->am_physical = VM_PAGE_TO_PHYS(m);
980 } else {
981 /* Our allocation is already nicely wired down for us.
982 * Just grab the physical address.
983 */
984 mem->am_physical = vtophys(sc->argb_cursor);
985 }
986 } else {
987 mem->am_physical = 0;
988 }
989
990 mem->am_offset = 0;
991 mem->am_is_bound = 0;
992 TAILQ_INSERT_TAIL(&sc->agp.as_memory, mem, am_link);
993 sc->agp.as_allocated += size;
994
995 return mem;
996 }
997
998 static int
999 agp_i810_free_memory(device_t dev, struct agp_memory *mem)
1000 {
1001 struct agp_i810_softc *sc = device_get_softc(dev);
1002
1003 if (mem->am_is_bound)
1004 return EBUSY;
1005
1006 if (mem->am_type == 2) {
1007 if (mem->am_size == AGP_PAGE_SIZE) {
1008 /*
1009 * Unwire the page which we wired in alloc_memory.
1010 */
1011 vm_page_t m;
1012
1013 VM_OBJECT_LOCK(mem->am_obj);
1014 m = vm_page_lookup(mem->am_obj, 0);
1015 VM_OBJECT_UNLOCK(mem->am_obj);
1016 vm_page_lock_queues();
1017 vm_page_unwire(m, 0);
1018 vm_page_unlock_queues();
1019 } else {
1020 contigfree(sc->argb_cursor, mem->am_size, M_AGP);
1021 sc->argb_cursor = NULL;
1022 }
1023 }
1024
1025 sc->agp.as_allocated -= mem->am_size;
1026 TAILQ_REMOVE(&sc->agp.as_memory, mem, am_link);
1027 if (mem->am_obj)
1028 vm_object_deallocate(mem->am_obj);
1029 free(mem, M_AGP);
1030 return 0;
1031 }
1032
1033 static int
1034 agp_i810_bind_memory(device_t dev, struct agp_memory *mem,
1035 vm_offset_t offset)
1036 {
1037 struct agp_i810_softc *sc = device_get_softc(dev);
1038 vm_offset_t i;
1039
1040 /* Do some sanity checks first. */
1041 if ((offset & (AGP_PAGE_SIZE - 1)) != 0 ||
1042 offset + mem->am_size > AGP_GET_APERTURE(dev)) {
1043 device_printf(dev, "binding memory at bad offset %#x\n",
1044 (int)offset);
1045 return EINVAL;
1046 }
1047
1048 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
1049 mtx_lock(&sc->agp.as_lock);
1050 if (mem->am_is_bound) {
1051 mtx_unlock(&sc->agp.as_lock);
1052 return EINVAL;
1053 }
1054 /* The memory's already wired down, just stick it in the GTT. */
1055 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1056 agp_i810_write_gtt_entry(dev, offset + i,
1057 mem->am_physical + i, 1);
1058 }
1059 agp_flush_cache();
1060 mem->am_offset = offset;
1061 mem->am_is_bound = 1;
1062 mtx_unlock(&sc->agp.as_lock);
1063 return 0;
1064 }
1065
1066 if (mem->am_type != 1)
1067 return agp_generic_bind_memory(dev, mem, offset);
1068
1069 if ( sc->chiptype != CHIP_I810 )
1070 return EINVAL;
1071
1072 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1073 bus_write_4(sc->sc_res[0],
1074 AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, i | 3);
1075 }
1076
1077 return 0;
1078 }
1079
1080 static int
1081 agp_i810_unbind_memory(device_t dev, struct agp_memory *mem)
1082 {
1083 struct agp_i810_softc *sc = device_get_softc(dev);
1084 vm_offset_t i;
1085
1086 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
1087 mtx_lock(&sc->agp.as_lock);
1088 if (!mem->am_is_bound) {
1089 mtx_unlock(&sc->agp.as_lock);
1090 return EINVAL;
1091 }
1092
1093 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1094 agp_i810_write_gtt_entry(dev, mem->am_offset + i,
1095 0, 0);
1096 }
1097 agp_flush_cache();
1098 mem->am_is_bound = 0;
1099 mtx_unlock(&sc->agp.as_lock);
1100 return 0;
1101 }
1102
1103 if (mem->am_type != 1)
1104 return agp_generic_unbind_memory(dev, mem);
1105
1106 if ( sc->chiptype != CHIP_I810 )
1107 return EINVAL;
1108
1109 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1110 bus_write_4(sc->sc_res[0],
1111 AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, 0);
1112 }
1113
1114 return 0;
1115 }
1116
1117 static device_method_t agp_i810_methods[] = {
1118 /* Device interface */
1119 DEVMETHOD(device_identify, agp_i810_identify),
1120 DEVMETHOD(device_probe, agp_i810_probe),
1121 DEVMETHOD(device_attach, agp_i810_attach),
1122 DEVMETHOD(device_detach, agp_i810_detach),
1123 DEVMETHOD(device_suspend, bus_generic_suspend),
1124 DEVMETHOD(device_resume, agp_i810_resume),
1125
1126 /* AGP interface */
1127 DEVMETHOD(agp_get_aperture, agp_generic_get_aperture),
1128 DEVMETHOD(agp_set_aperture, agp_i810_set_aperture),
1129 DEVMETHOD(agp_bind_page, agp_i810_bind_page),
1130 DEVMETHOD(agp_unbind_page, agp_i810_unbind_page),
1131 DEVMETHOD(agp_flush_tlb, agp_i810_flush_tlb),
1132 DEVMETHOD(agp_enable, agp_i810_enable),
1133 DEVMETHOD(agp_alloc_memory, agp_i810_alloc_memory),
1134 DEVMETHOD(agp_free_memory, agp_i810_free_memory),
1135 DEVMETHOD(agp_bind_memory, agp_i810_bind_memory),
1136 DEVMETHOD(agp_unbind_memory, agp_i810_unbind_memory),
1137
1138 { 0, 0 }
1139 };
1140
1141 static driver_t agp_i810_driver = {
1142 "agp",
1143 agp_i810_methods,
1144 sizeof(struct agp_i810_softc),
1145 };
1146
1147 static devclass_t agp_devclass;
1148
1149 DRIVER_MODULE(agp_i810, vgapci, agp_i810_driver, agp_devclass, 0, 0);
1150 MODULE_DEPEND(agp_i810, agp, 1, 1, 1);
1151 MODULE_DEPEND(agp_i810, pci, 1, 1, 1);
Cache object: f8f92bbe64af242fd969d42b91209e8f
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