Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/agp/agp_intel.c
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1 /*- 2 * Copyright (c) 2000 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/malloc.h> 33 #include <sys/kernel.h> 34 #include <sys/module.h> 35 #include <sys/bus.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/proc.h> 39 40 #include <dev/agp/agppriv.h> 41 #include <dev/agp/agpreg.h> 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcireg.h> 44 45 #include <vm/vm.h> 46 #include <vm/vm_object.h> 47 #include <vm/pmap.h> 48 49 #define MAX_APSIZE 0x3f /* 256 MB */ 50 51 struct agp_intel_softc { 52 struct agp_softc agp; 53 u_int32_t initial_aperture; /* aperture size at startup */ 54 struct agp_gatt *gatt; 55 u_int aperture_mask; 56 u_int32_t current_aperture; /* current aperture size */ 57 }; 58 59 static const char* 60 agp_intel_match(device_t dev) 61 { 62 if (pci_get_class(dev) != PCIC_BRIDGE 63 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST) 64 return (NULL); 65 66 if (agp_find_caps(dev) == 0) 67 return (NULL); 68 69 switch (pci_get_devid(dev)) { 70 /* Intel -- vendor 0x8086 */ 71 case 0x71808086: 72 return ("Intel 82443LX (440 LX) host to PCI bridge"); 73 case 0x71908086: 74 return ("Intel 82443BX (440 BX) host to PCI bridge"); 75 case 0x71a08086: 76 return ("Intel 82443GX host to PCI bridge"); 77 case 0x71a18086: 78 return ("Intel 82443GX host to AGP bridge"); 79 case 0x11308086: 80 return ("Intel 82815 (i815 GMCH) host to PCI bridge"); 81 case 0x25008086: 82 case 0x25018086: 83 return ("Intel 82820 host to AGP bridge"); 84 case 0x35758086: 85 return ("Intel 82830 host to AGP bridge"); 86 case 0x1a218086: 87 return ("Intel 82840 host to AGP bridge"); 88 case 0x1a308086: 89 return ("Intel 82845 host to AGP bridge"); 90 case 0x25308086: 91 return ("Intel 82850 host to AGP bridge"); 92 case 0x33408086: 93 return ("Intel 82855 host to AGP bridge"); 94 case 0x25318086: 95 return ("Intel 82860 host to AGP bridge"); 96 case 0x25708086: 97 return ("Intel 82865 host to AGP bridge"); 98 case 0x255d8086: 99 return ("Intel E7205 host to AGP bridge"); 100 case 0x25508086: 101 return ("Intel E7505 host to AGP bridge"); 102 case 0x25788086: 103 return ("Intel 82875P host to AGP bridge"); 104 case 0x25608086: 105 return ("Intel 82845G host to AGP bridge"); 106 case 0x35808086: 107 return ("Intel 82855GM host to AGP bridge"); 108 } 109 110 return (NULL); 111 } 112 113 static int 114 agp_intel_probe(device_t dev) 115 { 116 const char *desc; 117 118 if (resource_disabled("agp", device_get_unit(dev))) 119 return (ENXIO); 120 desc = agp_intel_match(dev); 121 if (desc) { 122 device_set_desc(dev, desc); 123 return (BUS_PROBE_DEFAULT); 124 } 125 126 return (ENXIO); 127 } 128 129 static void 130 agp_intel_commit_gatt(device_t dev) 131 { 132 struct agp_intel_softc *sc; 133 u_int32_t type; 134 u_int32_t value; 135 136 sc = device_get_softc(dev); 137 type = pci_get_devid(dev); 138 139 /* Install the gatt. */ 140 pci_write_config(dev, AGP_INTEL_ATTBASE, sc->gatt->ag_physical, 4); 141 142 /* Enable the GLTB and setup the control register. */ 143 switch (type) { 144 case 0x71908086: /* 440LX/EX */ 145 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2080, 4); 146 break; 147 case 0x71808086: /* 440BX */ 148 /* 149 * XXX: Should be 0xa080? Bit 9 is undefined, and 150 * bit 13 being on and bit 15 being clear is illegal. 151 */ 152 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4); 153 break; 154 default: 155 value = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4); 156 pci_write_config(dev, AGP_INTEL_AGPCTRL, value | 0x80, 4); 157 } 158 159 /* Enable aperture accesses. */ 160 switch (type) { 161 case 0x25008086: /* i820 */ 162 case 0x25018086: /* i820 */ 163 pci_write_config(dev, AGP_INTEL_I820_RDCR, 164 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 165 | (1 << 1)), 1); 166 break; 167 case 0x1a308086: /* i845 */ 168 case 0x25608086: /* i845G */ 169 case 0x33408086: /* i855 */ 170 case 0x35808086: /* i855GM */ 171 case 0x25708086: /* i865 */ 172 case 0x25788086: /* i875P */ 173 pci_write_config(dev, AGP_INTEL_I845_AGPM, 174 (pci_read_config(dev, AGP_INTEL_I845_AGPM, 1) 175 | (1 << 1)), 1); 176 break; 177 case 0x1a218086: /* i840 */ 178 case 0x25308086: /* i850 */ 179 case 0x25318086: /* i860 */ 180 case 0x255d8086: /* E7205 */ 181 case 0x25508086: /* E7505 */ 182 pci_write_config(dev, AGP_INTEL_MCHCFG, 183 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 184 | (1 << 9)), 2); 185 break; 186 default: /* Intel Generic (maybe) */ 187 pci_write_config(dev, AGP_INTEL_NBXCFG, 188 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 189 & ~(1 << 10)) | (1 << 9), 4); 190 } 191 192 /* Clear errors. */ 193 switch (type) { 194 case 0x1a218086: /* i840 */ 195 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2); 196 break; 197 case 0x25008086: /* i820 */ 198 case 0x25018086: /* i820 */ 199 case 0x1a308086: /* i845 */ 200 case 0x25608086: /* i845G */ 201 case 0x25308086: /* i850 */ 202 case 0x33408086: /* i855 */ 203 case 0x25318086: /* i860 */ 204 case 0x25708086: /* i865 */ 205 case 0x25788086: /* i875P */ 206 case 0x255d8086: /* E7205 */ 207 case 0x25508086: /* E7505 */ 208 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x00ff, 2); 209 break; 210 default: /* Intel Generic (maybe) */ 211 pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1); 212 } 213 } 214 215 static int 216 agp_intel_attach(device_t dev) 217 { 218 struct agp_intel_softc *sc; 219 struct agp_gatt *gatt; 220 u_int32_t value; 221 int error; 222 223 sc = device_get_softc(dev); 224 225 error = agp_generic_attach(dev); 226 if (error) 227 return (error); 228 229 /* Determine maximum supported aperture size. */ 230 value = pci_read_config(dev, AGP_INTEL_APSIZE, 1); 231 pci_write_config(dev, AGP_INTEL_APSIZE, MAX_APSIZE, 1); 232 sc->aperture_mask = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & 233 MAX_APSIZE; 234 pci_write_config(dev, AGP_INTEL_APSIZE, value, 1); 235 sc->current_aperture = sc->initial_aperture = AGP_GET_APERTURE(dev); 236 237 for (;;) { 238 gatt = agp_alloc_gatt(dev); 239 if (gatt) 240 break; 241 242 /* 243 * Probably contigmalloc failure. Try reducing the 244 * aperture so that the gatt size reduces. 245 */ 246 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) { 247 agp_generic_detach(dev); 248 return (ENOMEM); 249 } 250 } 251 sc->gatt = gatt; 252 253 agp_intel_commit_gatt(dev); 254 255 return (0); 256 } 257 258 static int 259 agp_intel_detach(device_t dev) 260 { 261 struct agp_intel_softc *sc; 262 u_int32_t reg; 263 264 sc = device_get_softc(dev); 265 266 agp_free_cdev(dev); 267 268 /* Disable aperture accesses. */ 269 switch (pci_get_devid(dev)) { 270 case 0x25008086: /* i820 */ 271 case 0x25018086: /* i820 */ 272 reg = pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) & ~(1 << 1); 273 printf("%s: set RDCR to %02x\n", __func__, reg & 0xff); 274 pci_write_config(dev, AGP_INTEL_I820_RDCR, reg, 1); 275 break; 276 case 0x1a308086: /* i845 */ 277 case 0x25608086: /* i845G */ 278 case 0x33408086: /* i855 */ 279 case 0x35808086: /* i855GM */ 280 case 0x25708086: /* i865 */ 281 case 0x25788086: /* i875P */ 282 reg = pci_read_config(dev, AGP_INTEL_I845_AGPM, 1) & ~(1 << 1); 283 printf("%s: set AGPM to %02x\n", __func__, reg & 0xff); 284 pci_write_config(dev, AGP_INTEL_I845_AGPM, reg, 1); 285 break; 286 case 0x1a218086: /* i840 */ 287 case 0x25308086: /* i850 */ 288 case 0x25318086: /* i860 */ 289 case 0x255d8086: /* E7205 */ 290 case 0x25508086: /* E7505 */ 291 reg = pci_read_config(dev, AGP_INTEL_MCHCFG, 2) & ~(1 << 9); 292 printf("%s: set MCHCFG to %x04\n", __func__, reg & 0xffff); 293 pci_write_config(dev, AGP_INTEL_MCHCFG, reg, 2); 294 break; 295 default: /* Intel Generic (maybe) */ 296 reg = pci_read_config(dev, AGP_INTEL_NBXCFG, 4) & ~(1 << 9); 297 printf("%s: set NBXCFG to %08x\n", __func__, reg); 298 pci_write_config(dev, AGP_INTEL_NBXCFG, reg, 4); 299 } 300 pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4); 301 AGP_SET_APERTURE(dev, sc->initial_aperture); 302 agp_free_gatt(sc->gatt); 303 agp_free_res(dev); 304 305 return (0); 306 } 307 308 static int 309 agp_intel_resume(device_t dev) 310 { 311 struct agp_intel_softc *sc; 312 sc = device_get_softc(dev); 313 314 AGP_SET_APERTURE(dev, sc->current_aperture); 315 agp_intel_commit_gatt(dev); 316 return (bus_generic_resume(dev)); 317 } 318 319 static u_int32_t 320 agp_intel_get_aperture(device_t dev) 321 { 322 struct agp_intel_softc *sc; 323 u_int32_t apsize; 324 325 sc = device_get_softc(dev); 326 327 apsize = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & sc->aperture_mask; 328 329 /* 330 * The size is determined by the number of low bits of 331 * register APBASE which are forced to zero. The low 22 bits 332 * are always forced to zero and each zero bit in the apsize 333 * field just read forces the corresponding bit in the 27:22 334 * to be zero. We calculate the aperture size accordingly. 335 */ 336 return ((((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1); 337 } 338 339 static int 340 agp_intel_set_aperture(device_t dev, u_int32_t aperture) 341 { 342 struct agp_intel_softc *sc; 343 u_int32_t apsize; 344 345 sc = device_get_softc(dev); 346 347 /* 348 * Reverse the magic from get_aperture. 349 */ 350 apsize = ((aperture - 1) >> 22) ^ sc->aperture_mask; 351 352 /* 353 * Double check for sanity. 354 */ 355 if ((((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1 != aperture) 356 return (EINVAL); 357 358 sc->current_aperture = apsize; 359 360 pci_write_config(dev, AGP_INTEL_APSIZE, apsize, 1); 361 362 return (0); 363 } 364 365 static int 366 agp_intel_bind_page(device_t dev, vm_offset_t offset, vm_offset_t physical) 367 { 368 struct agp_intel_softc *sc; 369 370 sc = device_get_softc(dev); 371 372 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 373 return (EINVAL); 374 375 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17; 376 return (0); 377 } 378 379 static int 380 agp_intel_unbind_page(device_t dev, vm_offset_t offset) 381 { 382 struct agp_intel_softc *sc; 383 384 sc = device_get_softc(dev); 385 386 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 387 return (EINVAL); 388 389 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 390 return (0); 391 } 392 393 static void 394 agp_intel_flush_tlb(device_t dev) 395 { 396 u_int32_t val; 397 398 val = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4); 399 pci_write_config(dev, AGP_INTEL_AGPCTRL, val & ~(1 << 7), 4); 400 pci_write_config(dev, AGP_INTEL_AGPCTRL, val, 4); 401 } 402 403 static device_method_t agp_intel_methods[] = { 404 /* Device interface */ 405 DEVMETHOD(device_probe, agp_intel_probe), 406 DEVMETHOD(device_attach, agp_intel_attach), 407 DEVMETHOD(device_detach, agp_intel_detach), 408 DEVMETHOD(device_shutdown, bus_generic_shutdown), 409 DEVMETHOD(device_suspend, bus_generic_suspend), 410 DEVMETHOD(device_resume, agp_intel_resume), 411 412 /* AGP interface */ 413 DEVMETHOD(agp_get_aperture, agp_intel_get_aperture), 414 DEVMETHOD(agp_set_aperture, agp_intel_set_aperture), 415 DEVMETHOD(agp_bind_page, agp_intel_bind_page), 416 DEVMETHOD(agp_unbind_page, agp_intel_unbind_page), 417 DEVMETHOD(agp_flush_tlb, agp_intel_flush_tlb), 418 DEVMETHOD(agp_enable, agp_generic_enable), 419 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory), 420 DEVMETHOD(agp_free_memory, agp_generic_free_memory), 421 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory), 422 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory), 423 424 { 0, 0 } 425 }; 426 427 static driver_t agp_intel_driver = { 428 "agp", 429 agp_intel_methods, 430 sizeof(struct agp_intel_softc), 431 }; 432 433 static devclass_t agp_devclass; 434 435 DRIVER_MODULE(agp_intel, hostb, agp_intel_driver, agp_devclass, 0, 0); 436 MODULE_DEPEND(agp_intel, agp, 1, 1, 1); 437 MODULE_DEPEND(agp_intel, pci, 1, 1, 1);
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