The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/agp/agp_nvidia.c

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    1 /*-
    2  * Copyright (c) 2003 Matthew N. Dodd <winter@jurai.net>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  *
   26  * $FreeBSD: src/sys/dev/agp/agp_nvidia.c,v 1.13 2007/11/12 21:51:37 jhb Exp $
   27  */
   28 
   29 /*
   30  * Written using information gleaned from the
   31  * NVIDIA nForce/nForce2 AGPGART Linux Kernel Patch.
   32  */
   33 
   34 #include <sys/param.h>
   35 #include <sys/systm.h>
   36 #include <sys/malloc.h>
   37 #include <sys/kernel.h>
   38 #include <sys/bus.h>
   39 #include <sys/lock.h>
   40 #include <sys/rman.h>
   41 
   42 #include <bus/pci/pcivar.h>
   43 #include <bus/pci/pcireg.h>
   44 #include "agppriv.h"
   45 #include "agpreg.h"
   46 
   47 #include <vm/vm.h>
   48 #include <vm/vm_object.h>
   49 #include <vm/pmap.h>
   50 
   51 #define NVIDIA_VENDORID         0x10de
   52 #define NVIDIA_DEVICEID_NFORCE  0x01a4
   53 #define NVIDIA_DEVICEID_NFORCE2 0x01e0
   54 
   55 struct agp_nvidia_softc {
   56         struct agp_softc        agp;
   57         u_int32_t               initial_aperture; /* aperture size at startup */
   58         struct agp_gatt *       gatt;
   59 
   60         device_t                dev;            /* AGP Controller */
   61         device_t                mc1_dev;        /* Memory Controller */
   62         device_t                mc2_dev;        /* Memory Controller */
   63         device_t                bdev;           /* Bridge */
   64 
   65         u_int32_t               wbc_mask;
   66         int                     num_dirs;
   67         int                     num_active_entries;
   68         off_t                   pg_offset;
   69 };
   70 
   71 static const char *agp_nvidia_match(device_t dev);
   72 static int agp_nvidia_probe(device_t);
   73 static int agp_nvidia_attach(device_t);
   74 static int agp_nvidia_detach(device_t);
   75 static u_int32_t agp_nvidia_get_aperture(device_t);
   76 static int agp_nvidia_set_aperture(device_t, u_int32_t);
   77 static int agp_nvidia_bind_page(device_t, vm_offset_t, vm_offset_t);
   78 static int agp_nvidia_unbind_page(device_t, vm_offset_t);
   79 
   80 static int nvidia_init_iorr(u_int32_t, u_int32_t);
   81 
   82 static const char *
   83 agp_nvidia_match (device_t dev)
   84 {
   85         if (pci_get_class(dev) != PCIC_BRIDGE ||
   86             pci_get_subclass(dev) != PCIS_BRIDGE_HOST ||
   87             pci_get_vendor(dev) != NVIDIA_VENDORID)
   88                 return (NULL);
   89 
   90         switch (pci_get_device(dev)) {
   91         case NVIDIA_DEVICEID_NFORCE:
   92                 return ("NVIDIA nForce AGP Controller");
   93         case NVIDIA_DEVICEID_NFORCE2:
   94                 return ("NVIDIA nForce2 AGP Controller");
   95         }
   96         return (NULL);
   97 }
   98 
   99 static int
  100 agp_nvidia_probe (device_t dev)
  101 {
  102         const char *desc;
  103 
  104         if (resource_disabled("agp", device_get_unit(dev)))
  105                 return (ENXIO);
  106         desc = agp_nvidia_match(dev);
  107         if (desc) {
  108                 device_verbose(dev);
  109                 device_set_desc(dev, desc);
  110                 return (BUS_PROBE_DEFAULT);
  111         }
  112         return (ENXIO);
  113 }
  114 
  115 static int
  116 agp_nvidia_attach (device_t dev)
  117 {
  118         struct agp_nvidia_softc *sc = device_get_softc(dev);
  119         struct agp_gatt *gatt;
  120         u_int32_t apbase;
  121         u_int32_t aplimit;
  122         u_int32_t temp;
  123         int size;
  124         int i;
  125         int error;
  126 
  127         switch (pci_get_device(dev)) {
  128         case NVIDIA_DEVICEID_NFORCE:
  129                 sc->wbc_mask = 0x00010000;
  130                 break;
  131         case NVIDIA_DEVICEID_NFORCE2:
  132                 sc->wbc_mask = 0x80000000;
  133                 break;
  134         default:
  135                 device_printf(dev, "Bad chip id\n");
  136                 return (ENODEV);
  137         }
  138 
  139         /* AGP Controller */
  140         sc->dev = dev;
  141 
  142         /* Memory Controller 1 */
  143         sc->mc1_dev = pci_find_bsf(pci_get_bus(dev), 0, 1);
  144         if (sc->mc1_dev == NULL) {
  145                 device_printf(dev,
  146                         "Unable to find NVIDIA Memory Controller 1.\n");
  147                 return (ENODEV);
  148         }
  149 
  150         /* Memory Controller 2 */
  151         sc->mc2_dev = pci_find_bsf(pci_get_bus(dev), 0, 2);
  152         if (sc->mc2_dev == NULL) {
  153                 device_printf(dev,
  154                         "Unable to find NVIDIA Memory Controller 2.\n");
  155                 return (ENODEV);
  156         }
  157 
  158         /* AGP Host to PCI Bridge */
  159         sc->bdev = pci_find_bsf(pci_get_bus(dev), 30, 0);
  160         if (sc->bdev == NULL) {
  161                 device_printf(dev,
  162                         "Unable to find NVIDIA AGP Host to PCI Bridge.\n");
  163                 return (ENODEV);
  164         }
  165 
  166         error = agp_generic_attach(dev);
  167         if (error)
  168                 return (error);
  169 
  170         sc->initial_aperture = AGP_GET_APERTURE(dev);
  171         if (sc->initial_aperture == 0) {
  172                 device_printf(dev, "bad initial aperture size, disabling\n");
  173                 return ENXIO;
  174         }
  175 
  176         for (;;) {
  177                 gatt = agp_alloc_gatt(dev);
  178                 if (gatt)
  179                         break;
  180                 /*
  181                  * Probably contigmalloc failure. Try reducing the
  182                  * aperture so that the gatt size reduces.
  183                  */
  184                 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2))
  185                         goto fail;
  186         }
  187         sc->gatt = gatt;
  188 
  189         apbase = rman_get_start(sc->agp.as_aperture);
  190         aplimit = apbase + AGP_GET_APERTURE(dev) - 1;
  191         pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APBASE, apbase, 4);
  192         pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APLIMIT, aplimit, 4);
  193         pci_write_config(sc->bdev, AGP_NVIDIA_3_APBASE, apbase, 4);
  194         pci_write_config(sc->bdev, AGP_NVIDIA_3_APLIMIT, aplimit, 4);
  195 
  196         error = nvidia_init_iorr(apbase, AGP_GET_APERTURE(dev));
  197         if (error) {
  198                 device_printf(dev, "Failed to setup IORRs\n");
  199                 goto fail;
  200         }
  201 
  202         /* directory size is 64k */
  203         size = AGP_GET_APERTURE(dev) / 1024 / 1024;
  204         sc->num_dirs = size / 64;
  205         sc->num_active_entries = (size == 32) ? 16384 : ((size * 1024) / 4);
  206         sc->pg_offset = 0;
  207         if (sc->num_dirs == 0) {
  208                 sc->num_dirs = 1;
  209                 sc->num_active_entries /= (64 / size);
  210                 sc->pg_offset = (apbase & (64 * 1024 * 1024 - 1) &
  211                                  ~(AGP_GET_APERTURE(dev) - 1)) / PAGE_SIZE;
  212         }
  213 
  214         /* (G)ATT Base Address */
  215         for (i = 0; i < 8; i++) {
  216                 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_ATTBASE(i),
  217                                  (sc->gatt->ag_physical +
  218                                    (i % sc->num_dirs) * 64 * 1024) | 1, 4);
  219         }
  220 
  221         /* GTLB Control */
  222         temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
  223         pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp | 0x11, 4);
  224 
  225         /* GART Control */
  226         temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
  227         pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp | 0x100, 4);
  228 
  229         return (0);
  230 fail:
  231         agp_generic_detach(dev);
  232         return (ENOMEM);
  233 }
  234 
  235 static int
  236 agp_nvidia_detach (device_t dev)
  237 {
  238         struct agp_nvidia_softc *sc = device_get_softc(dev);
  239         u_int32_t temp;
  240 
  241         agp_free_cdev(dev);
  242 
  243         /* GART Control */
  244         temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
  245         pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp & ~(0x100), 4);
  246 
  247         /* GTLB Control */
  248         temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
  249         pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp & ~(0x11), 4);
  250 
  251         /* Put the aperture back the way it started. */
  252         AGP_SET_APERTURE(dev, sc->initial_aperture);
  253 
  254         /* restore iorr for previous aperture size */
  255         nvidia_init_iorr(rman_get_start(sc->agp.as_aperture),
  256                          sc->initial_aperture);
  257 
  258         agp_free_gatt(sc->gatt);
  259         agp_free_res(dev);
  260 
  261         return (0);
  262 }
  263 
  264 static u_int32_t
  265 agp_nvidia_get_aperture(device_t dev)
  266 {
  267         switch (pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1) & 0x0f) {
  268         case 0: return (512 * 1024 * 1024); break;
  269         case 8: return (256 * 1024 * 1024); break;
  270         case 12: return (128 * 1024 * 1024); break;
  271         case 14: return (64 * 1024 * 1024); break;
  272         case 15: return (32 * 1024 * 1024); break;
  273         default:
  274                 device_printf(dev, "Invalid aperture setting 0x%x\n",
  275                     pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1));
  276                 return 0;
  277         }
  278 }
  279 
  280 static int
  281 agp_nvidia_set_aperture(device_t dev, u_int32_t aperture)
  282 {
  283         u_int8_t val;
  284         u_int8_t key;
  285 
  286         switch (aperture) {
  287         case (512 * 1024 * 1024): key = 0; break;
  288         case (256 * 1024 * 1024): key = 8; break;
  289         case (128 * 1024 * 1024): key = 12; break;
  290         case (64 * 1024 * 1024): key = 14; break;
  291         case (32 * 1024 * 1024): key = 15; break;
  292         default:
  293                 device_printf(dev, "Invalid aperture size (%dMb)\n",
  294                                 aperture / 1024 / 1024);
  295                 return (EINVAL);
  296         }
  297         val = pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1);
  298         pci_write_config(dev, AGP_NVIDIA_0_APSIZE, ((val & ~0x0f) | key), 1);
  299 
  300         return (0);
  301 }
  302 
  303 static int
  304 agp_nvidia_bind_page(device_t dev, vm_offset_t offset, vm_offset_t physical)
  305 {
  306         struct agp_nvidia_softc *sc = device_get_softc(dev);
  307         u_int32_t index;
  308 
  309         if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
  310                 return (EINVAL);
  311 
  312         index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT;
  313         sc->gatt->ag_virtual[index] = physical | 1;
  314 
  315         return (0);
  316 }
  317 
  318 static int
  319 agp_nvidia_unbind_page(device_t dev, vm_offset_t offset)
  320 {
  321         struct agp_nvidia_softc *sc = device_get_softc(dev);
  322         u_int32_t index;
  323 
  324         if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
  325                 return (EINVAL);
  326 
  327         index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT;
  328         sc->gatt->ag_virtual[index] = 0;
  329 
  330         return (0);
  331 }
  332 
  333 static void
  334 agp_nvidia_flush_tlb (device_t dev)
  335 {
  336         struct agp_nvidia_softc *sc;
  337         u_int32_t wbc_reg, temp;
  338         volatile u_int32_t *ag_virtual;
  339         int i, pages;
  340 
  341         sc = (struct agp_nvidia_softc *)device_get_softc(dev);
  342 
  343         if (sc->wbc_mask) {
  344                 wbc_reg = pci_read_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, 4);
  345                 wbc_reg |= sc->wbc_mask;
  346                 pci_write_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, wbc_reg, 4);
  347 
  348                 /* Wait no more than 3 seconds. */
  349                 for (i = 0; i < 3000; i++) {
  350                         wbc_reg = pci_read_config(sc->mc1_dev,
  351                                                   AGP_NVIDIA_1_WBC, 4);
  352                         if ((sc->wbc_mask & wbc_reg) == 0)
  353                                 break;
  354                         else
  355                                 DELAY(1000);
  356                 }
  357                 if (i == 3000)
  358                         device_printf(dev,
  359                                 "TLB flush took more than 3 seconds.\n");
  360         }
  361 
  362         ag_virtual = (volatile u_int32_t *)sc->gatt->ag_virtual;
  363 
  364         /* Flush TLB entries. */
  365         pages = sc->gatt->ag_entries * sizeof(u_int32_t) / PAGE_SIZE;
  366         for(i = 0; i < pages; i++)
  367                 temp = ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
  368         for(i = 0; i < pages; i++)
  369                 temp = ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
  370 }
  371 
  372 #define SYSCFG          0xC0010010
  373 #define IORR_BASE0      0xC0010016
  374 #define IORR_MASK0      0xC0010017
  375 #define AMD_K7_NUM_IORR 2
  376 
  377 static int
  378 nvidia_init_iorr(u_int32_t addr, u_int32_t size)
  379 {
  380         quad_t base, mask, sys;
  381         u_int32_t iorr_addr, free_iorr_addr;
  382 
  383         /* Find the iorr that is already used for the addr */
  384         /* If not found, determine the uppermost available iorr */
  385         free_iorr_addr = AMD_K7_NUM_IORR;
  386         for(iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
  387                 base = rdmsr(IORR_BASE0 + 2 * iorr_addr);
  388                 mask = rdmsr(IORR_MASK0 + 2 * iorr_addr);
  389 
  390                 if ((base & 0xfffff000ULL) == (addr & 0xfffff000))
  391                         break;
  392 
  393                 if ((mask & 0x00000800ULL) == 0)
  394                         free_iorr_addr = iorr_addr;
  395         }
  396 
  397         if (iorr_addr >= AMD_K7_NUM_IORR) {
  398                 iorr_addr = free_iorr_addr;
  399                 if (iorr_addr >= AMD_K7_NUM_IORR)
  400                         return (EINVAL);
  401         }
  402 
  403         base = (addr & ~0xfff) | 0x18;
  404         mask = (0xfULL << 32) | ((~(size - 1)) & 0xfffff000) | 0x800;
  405         wrmsr(IORR_BASE0 + 2 * iorr_addr, base);
  406         wrmsr(IORR_MASK0 + 2 * iorr_addr, mask);
  407 
  408         sys = rdmsr(SYSCFG);
  409         sys |= 0x00100000ULL;
  410         wrmsr(SYSCFG, sys);
  411 
  412         return (0);
  413 }
  414 
  415 static device_method_t agp_nvidia_methods[] = {
  416         /* Device interface */
  417         DEVMETHOD(device_probe,         agp_nvidia_probe),
  418         DEVMETHOD(device_attach,        agp_nvidia_attach),
  419         DEVMETHOD(device_detach,        agp_nvidia_detach),
  420         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  421         DEVMETHOD(device_suspend,       bus_generic_suspend),
  422         DEVMETHOD(device_resume,        bus_generic_resume),
  423 
  424         /* AGP interface */
  425         DEVMETHOD(agp_get_aperture,     agp_nvidia_get_aperture),
  426         DEVMETHOD(agp_set_aperture,     agp_nvidia_set_aperture),
  427         DEVMETHOD(agp_bind_page,        agp_nvidia_bind_page),
  428         DEVMETHOD(agp_unbind_page,      agp_nvidia_unbind_page),
  429         DEVMETHOD(agp_flush_tlb,        agp_nvidia_flush_tlb),
  430 
  431         DEVMETHOD(agp_enable,           agp_generic_enable),
  432         DEVMETHOD(agp_alloc_memory,     agp_generic_alloc_memory),
  433         DEVMETHOD(agp_free_memory,      agp_generic_free_memory),
  434         DEVMETHOD(agp_bind_memory,      agp_generic_bind_memory),
  435         DEVMETHOD(agp_unbind_memory,    agp_generic_unbind_memory),
  436 
  437         DEVMETHOD_END
  438 };
  439 
  440 static driver_t agp_nvidia_driver = {
  441         "agp",
  442         agp_nvidia_methods,
  443         sizeof(struct agp_nvidia_softc),
  444 };
  445 
  446 static devclass_t agp_devclass;
  447 
  448 DRIVER_MODULE(agp_nvidia, pci, agp_nvidia_driver, agp_devclass, NULL, NULL);
  449 MODULE_DEPEND(agp_nvidia, agp, 1, 1, 1);
  450 MODULE_DEPEND(agp_nvidia, pci, 1, 1, 1);

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