1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2003 Matthew N. Dodd <winter@jurai.net>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31
32 /*
33 * Written using information gleaned from the
34 * NVIDIA nForce/nForce2 AGPGART Linux Kernel Patch.
35 */
36
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/malloc.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <sys/bus.h>
43 #include <sys/lock.h>
44 #include <sys/mutex.h>
45 #include <sys/proc.h>
46
47 #include <dev/agp/agppriv.h>
48 #include <dev/agp/agpreg.h>
49 #include <dev/pci/pcivar.h>
50 #include <dev/pci/pcireg.h>
51
52 #include <vm/vm.h>
53 #include <vm/vm_object.h>
54 #include <vm/pmap.h>
55
56 #include <machine/bus.h>
57 #include <machine/resource.h>
58 #include <sys/rman.h>
59
60 #define NVIDIA_VENDORID 0x10de
61 #define NVIDIA_DEVICEID_NFORCE 0x01a4
62 #define NVIDIA_DEVICEID_NFORCE2 0x01e0
63
64 struct agp_nvidia_softc {
65 struct agp_softc agp;
66 u_int32_t initial_aperture; /* aperture size at startup */
67 struct agp_gatt * gatt;
68
69 device_t dev; /* AGP Controller */
70 device_t mc1_dev; /* Memory Controller */
71 device_t mc2_dev; /* Memory Controller */
72 device_t bdev; /* Bridge */
73
74 u_int32_t wbc_mask;
75 int num_dirs;
76 int num_active_entries;
77 off_t pg_offset;
78 };
79
80 static const char *agp_nvidia_match(device_t dev);
81 static int agp_nvidia_probe(device_t);
82 static int agp_nvidia_attach(device_t);
83 static int agp_nvidia_detach(device_t);
84 static u_int32_t agp_nvidia_get_aperture(device_t);
85 static int agp_nvidia_set_aperture(device_t, u_int32_t);
86 static int agp_nvidia_bind_page(device_t, vm_offset_t, vm_offset_t);
87 static int agp_nvidia_unbind_page(device_t, vm_offset_t);
88
89 static int nvidia_init_iorr(u_int32_t, u_int32_t);
90
91 static const char *
92 agp_nvidia_match (device_t dev)
93 {
94 if (pci_get_class(dev) != PCIC_BRIDGE ||
95 pci_get_subclass(dev) != PCIS_BRIDGE_HOST ||
96 pci_get_vendor(dev) != NVIDIA_VENDORID)
97 return (NULL);
98
99 switch (pci_get_device(dev)) {
100 case NVIDIA_DEVICEID_NFORCE:
101 return ("NVIDIA nForce AGP Controller");
102 case NVIDIA_DEVICEID_NFORCE2:
103 return ("NVIDIA nForce2 AGP Controller");
104 }
105 return (NULL);
106 }
107
108 static int
109 agp_nvidia_probe (device_t dev)
110 {
111 const char *desc;
112
113 if (resource_disabled("agp", device_get_unit(dev)))
114 return (ENXIO);
115 desc = agp_nvidia_match(dev);
116 if (desc) {
117 device_set_desc(dev, desc);
118 return (BUS_PROBE_DEFAULT);
119 }
120 return (ENXIO);
121 }
122
123 static int
124 agp_nvidia_attach (device_t dev)
125 {
126 struct agp_nvidia_softc *sc = device_get_softc(dev);
127 struct agp_gatt *gatt;
128 u_int32_t apbase;
129 u_int32_t aplimit;
130 u_int32_t temp;
131 int size;
132 int i;
133 int error;
134
135 switch (pci_get_device(dev)) {
136 case NVIDIA_DEVICEID_NFORCE:
137 sc->wbc_mask = 0x00010000;
138 break;
139 case NVIDIA_DEVICEID_NFORCE2:
140 sc->wbc_mask = 0x80000000;
141 break;
142 default:
143 device_printf(dev, "Bad chip id\n");
144 return (ENODEV);
145 }
146
147 /* AGP Controller */
148 sc->dev = dev;
149
150 /* Memory Controller 1 */
151 sc->mc1_dev = pci_find_bsf(pci_get_bus(dev), 0, 1);
152 if (sc->mc1_dev == NULL) {
153 device_printf(dev,
154 "Unable to find NVIDIA Memory Controller 1.\n");
155 return (ENODEV);
156 }
157
158 /* Memory Controller 2 */
159 sc->mc2_dev = pci_find_bsf(pci_get_bus(dev), 0, 2);
160 if (sc->mc2_dev == NULL) {
161 device_printf(dev,
162 "Unable to find NVIDIA Memory Controller 2.\n");
163 return (ENODEV);
164 }
165
166 /* AGP Host to PCI Bridge */
167 sc->bdev = pci_find_bsf(pci_get_bus(dev), 30, 0);
168 if (sc->bdev == NULL) {
169 device_printf(dev,
170 "Unable to find NVIDIA AGP Host to PCI Bridge.\n");
171 return (ENODEV);
172 }
173
174 error = agp_generic_attach(dev);
175 if (error)
176 return (error);
177
178 sc->initial_aperture = AGP_GET_APERTURE(dev);
179
180 for (;;) {
181 gatt = agp_alloc_gatt(dev);
182 if (gatt)
183 break;
184 /*
185 * Probably contigmalloc failure. Try reducing the
186 * aperture so that the gatt size reduces.
187 */
188 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2))
189 goto fail;
190 }
191 sc->gatt = gatt;
192
193 apbase = rman_get_start(sc->agp.as_aperture);
194 aplimit = apbase + AGP_GET_APERTURE(dev) - 1;
195 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APBASE, apbase, 4);
196 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APLIMIT, aplimit, 4);
197 pci_write_config(sc->bdev, AGP_NVIDIA_3_APBASE, apbase, 4);
198 pci_write_config(sc->bdev, AGP_NVIDIA_3_APLIMIT, aplimit, 4);
199
200 error = nvidia_init_iorr(apbase, AGP_GET_APERTURE(dev));
201 if (error) {
202 device_printf(dev, "Failed to setup IORRs\n");
203 goto fail;
204 }
205
206 /* directory size is 64k */
207 size = AGP_GET_APERTURE(dev) / 1024 / 1024;
208 sc->num_dirs = size / 64;
209 sc->num_active_entries = (size == 32) ? 16384 : ((size * 1024) / 4);
210 sc->pg_offset = 0;
211 if (sc->num_dirs == 0) {
212 sc->num_dirs = 1;
213 sc->num_active_entries /= (64 / size);
214 sc->pg_offset = rounddown2(apbase & (64 * 1024 * 1024 - 1),
215 AGP_GET_APERTURE(dev)) / PAGE_SIZE;
216 }
217
218 /* (G)ATT Base Address */
219 for (i = 0; i < 8; i++) {
220 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_ATTBASE(i),
221 (sc->gatt->ag_physical +
222 (i % sc->num_dirs) * 64 * 1024) | 1, 4);
223 }
224
225 /* GTLB Control */
226 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
227 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp | 0x11, 4);
228
229 /* GART Control */
230 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
231 pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp | 0x100, 4);
232
233 return (0);
234 fail:
235 agp_generic_detach(dev);
236 return (ENOMEM);
237 }
238
239 static int
240 agp_nvidia_detach (device_t dev)
241 {
242 struct agp_nvidia_softc *sc = device_get_softc(dev);
243 u_int32_t temp;
244
245 agp_free_cdev(dev);
246
247 /* GART Control */
248 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
249 pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp & ~(0x100), 4);
250
251 /* GTLB Control */
252 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
253 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp & ~(0x11), 4);
254
255 /* Put the aperture back the way it started. */
256 AGP_SET_APERTURE(dev, sc->initial_aperture);
257
258 /* restore iorr for previous aperture size */
259 nvidia_init_iorr(rman_get_start(sc->agp.as_aperture),
260 sc->initial_aperture);
261
262 agp_free_gatt(sc->gatt);
263 agp_free_res(dev);
264
265 return (0);
266 }
267
268 static u_int32_t
269 agp_nvidia_get_aperture(device_t dev)
270 {
271 switch (pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1) & 0x0f) {
272 case 0: return (512 * 1024 * 1024);
273 case 8: return (256 * 1024 * 1024);
274 case 12: return (128 * 1024 * 1024);
275 case 14: return (64 * 1024 * 1024);
276 case 15: return (32 * 1024 * 1024);
277 default:
278 device_printf(dev, "Invalid aperture setting 0x%x\n",
279 pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1));
280 return 0;
281 }
282 }
283
284 static int
285 agp_nvidia_set_aperture(device_t dev, u_int32_t aperture)
286 {
287 u_int8_t val;
288 u_int8_t key;
289
290 switch (aperture) {
291 case (512 * 1024 * 1024): key = 0; break;
292 case (256 * 1024 * 1024): key = 8; break;
293 case (128 * 1024 * 1024): key = 12; break;
294 case (64 * 1024 * 1024): key = 14; break;
295 case (32 * 1024 * 1024): key = 15; break;
296 default:
297 device_printf(dev, "Invalid aperture size (%dMb)\n",
298 aperture / 1024 / 1024);
299 return (EINVAL);
300 }
301 val = pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1);
302 pci_write_config(dev, AGP_NVIDIA_0_APSIZE, ((val & ~0x0f) | key), 1);
303
304 return (0);
305 }
306
307 static int
308 agp_nvidia_bind_page(device_t dev, vm_offset_t offset, vm_offset_t physical)
309 {
310 struct agp_nvidia_softc *sc = device_get_softc(dev);
311 u_int32_t index;
312
313 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
314 return (EINVAL);
315
316 index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT;
317 sc->gatt->ag_virtual[index] = physical | 1;
318
319 return (0);
320 }
321
322 static int
323 agp_nvidia_unbind_page(device_t dev, vm_offset_t offset)
324 {
325 struct agp_nvidia_softc *sc = device_get_softc(dev);
326 u_int32_t index;
327
328 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
329 return (EINVAL);
330
331 index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT;
332 sc->gatt->ag_virtual[index] = 0;
333
334 return (0);
335 }
336
337 static void
338 agp_nvidia_flush_tlb (device_t dev)
339 {
340 struct agp_nvidia_softc *sc;
341 u_int32_t wbc_reg, temp;
342 volatile u_int32_t *ag_virtual;
343 int i, pages;
344
345 sc = (struct agp_nvidia_softc *)device_get_softc(dev);
346
347 if (sc->wbc_mask) {
348 wbc_reg = pci_read_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, 4);
349 wbc_reg |= sc->wbc_mask;
350 pci_write_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, wbc_reg, 4);
351
352 /* Wait no more than 3 seconds. */
353 for (i = 0; i < 3000; i++) {
354 wbc_reg = pci_read_config(sc->mc1_dev,
355 AGP_NVIDIA_1_WBC, 4);
356 if ((sc->wbc_mask & wbc_reg) == 0)
357 break;
358 else
359 DELAY(1000);
360 }
361 if (i == 3000)
362 device_printf(dev,
363 "TLB flush took more than 3 seconds.\n");
364 }
365
366 ag_virtual = (volatile u_int32_t *)sc->gatt->ag_virtual;
367
368 /* Flush TLB entries. */
369 pages = sc->gatt->ag_entries * sizeof(u_int32_t) / PAGE_SIZE;
370 for(i = 0; i < pages; i++)
371 temp = ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
372 for(i = 0; i < pages; i++)
373 temp = ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
374 }
375
376 #define SYSCFG 0xC0010010
377 #define IORR_BASE0 0xC0010016
378 #define IORR_MASK0 0xC0010017
379 #define AMD_K7_NUM_IORR 2
380
381 static int
382 nvidia_init_iorr(u_int32_t addr, u_int32_t size)
383 {
384 quad_t base, mask, sys;
385 u_int32_t iorr_addr, free_iorr_addr;
386
387 /* Find the iorr that is already used for the addr */
388 /* If not found, determine the uppermost available iorr */
389 free_iorr_addr = AMD_K7_NUM_IORR;
390 for(iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
391 base = rdmsr(IORR_BASE0 + 2 * iorr_addr);
392 mask = rdmsr(IORR_MASK0 + 2 * iorr_addr);
393
394 if ((base & 0xfffff000ULL) == (addr & 0xfffff000))
395 break;
396
397 if ((mask & 0x00000800ULL) == 0)
398 free_iorr_addr = iorr_addr;
399 }
400
401 if (iorr_addr >= AMD_K7_NUM_IORR) {
402 iorr_addr = free_iorr_addr;
403 if (iorr_addr >= AMD_K7_NUM_IORR)
404 return (EINVAL);
405 }
406
407 base = (addr & ~0xfff) | 0x18;
408 mask = (0xfULL << 32) | rounddown2(0xfffff000, size) | 0x800;
409 wrmsr(IORR_BASE0 + 2 * iorr_addr, base);
410 wrmsr(IORR_MASK0 + 2 * iorr_addr, mask);
411
412 sys = rdmsr(SYSCFG);
413 sys |= 0x00100000ULL;
414 wrmsr(SYSCFG, sys);
415
416 return (0);
417 }
418
419 static device_method_t agp_nvidia_methods[] = {
420 /* Device interface */
421 DEVMETHOD(device_probe, agp_nvidia_probe),
422 DEVMETHOD(device_attach, agp_nvidia_attach),
423 DEVMETHOD(device_detach, agp_nvidia_detach),
424 DEVMETHOD(device_shutdown, bus_generic_shutdown),
425 DEVMETHOD(device_suspend, bus_generic_suspend),
426 DEVMETHOD(device_resume, bus_generic_resume),
427
428 /* AGP interface */
429 DEVMETHOD(agp_get_aperture, agp_nvidia_get_aperture),
430 DEVMETHOD(agp_set_aperture, agp_nvidia_set_aperture),
431 DEVMETHOD(agp_bind_page, agp_nvidia_bind_page),
432 DEVMETHOD(agp_unbind_page, agp_nvidia_unbind_page),
433 DEVMETHOD(agp_flush_tlb, agp_nvidia_flush_tlb),
434
435 DEVMETHOD(agp_enable, agp_generic_enable),
436 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
437 DEVMETHOD(agp_free_memory, agp_generic_free_memory),
438 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
439 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
440 { 0, 0 }
441 };
442
443 static driver_t agp_nvidia_driver = {
444 "agp",
445 agp_nvidia_methods,
446 sizeof(struct agp_nvidia_softc),
447 };
448
449 static devclass_t agp_devclass;
450
451 DRIVER_MODULE(agp_nvidia, hostb, agp_nvidia_driver, agp_devclass, 0, 0);
452 MODULE_DEPEND(agp_nvidia, agp, 1, 1, 1);
453 MODULE_DEPEND(agp_nvidia, pci, 1, 1, 1);
Cache object: 91d532c20871472444cf30d5eafed83d
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