FreeBSD/Linux Kernel Cross Reference
sys/dev/agp/agpreg.h
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2000 Doug Rabson
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD: releng/12.0/sys/dev/agp/agpreg.h 326255 2017-11-27 14:52:40Z pfg $
29 */
30
31 #ifndef _PCI_AGPREG_H_
32 #define _PCI_AGPREG_H_
33
34 /*
35 * Offsets for various AGP configuration registers.
36 */
37 #define AGP_APBASE PCIR_BAR(0)
38
39 /*
40 * Offsets from the AGP Capability pointer.
41 */
42 #define AGP_CAPID 0x0
43 #define AGP_STATUS 0x4
44 #define AGP_COMMAND 0x8
45 #define AGP_STATUS_AGP3 0x0008
46 #define AGP_STATUS_RQ_MASK 0xff000000
47 #define AGP_COMMAND_RQ_MASK 0xff000000
48 #define AGP_STATUS_ARQSZ_MASK 0xe000
49 #define AGP_COMMAND_ARQSZ_MASK 0xe000
50 #define AGP_STATUS_CAL_MASK 0x1c00
51 #define AGP_COMMAND_CAL_MASK 0x1c00
52 #define AGP_STATUS_ISOCH 0x10000
53 #define AGP_STATUS_SBA 0x0200
54 #define AGP_STATUS_ITA_COH 0x0100
55 #define AGP_STATUS_GART64 0x0080
56 #define AGP_STATUS_HTRANS 0x0040
57 #define AGP_STATUS_64BIT 0x0020
58 #define AGP_STATUS_FW 0x0010
59 #define AGP_COMMAND_RQ_MASK 0xff000000
60 #define AGP_COMMAND_ARQSZ_MASK 0xe000
61 #define AGP_COMMAND_CAL_MASK 0x1c00
62 #define AGP_COMMAND_SBA 0x0200
63 #define AGP_COMMAND_AGP 0x0100
64 #define AGP_COMMAND_GART64 0x0080
65 #define AGP_COMMAND_64BIT 0x0020
66 #define AGP_COMMAND_FW 0x0010
67
68 /*
69 * Config offsets for Intel AGP chipsets.
70 */
71 #define AGP_INTEL_NBXCFG 0x50
72 #define AGP_INTEL_ERRSTS 0x91
73 #define AGP_INTEL_AGPCTRL 0xb0
74 #define AGP_INTEL_APSIZE 0xb4
75 #define AGP_INTEL_ATTBASE 0xb8
76
77 /*
78 * Config offsets for Intel i8xx/E7xxx AGP chipsets.
79 */
80 #define AGP_INTEL_MCHCFG 0x50
81 #define AGP_INTEL_I820_RDCR 0x51
82 #define AGP_INTEL_I845_AGPM 0x51
83 #define AGP_INTEL_I8XX_ERRSTS 0xc8
84
85 /*
86 * Config offsets for VIA AGP 2.x chipsets.
87 */
88 #define AGP_VIA_GARTCTRL 0x80
89 #define AGP_VIA_APSIZE 0x84
90 #define AGP_VIA_ATTBASE 0x88
91
92 /*
93 * Config offsets for VIA AGP 3.0 chipsets.
94 */
95 #define AGP3_VIA_GARTCTRL 0x90
96 #define AGP3_VIA_APSIZE 0x94
97 #define AGP3_VIA_ATTBASE 0x98
98 #define AGP_VIA_AGPSEL 0xfd
99
100 /*
101 * Config offsets for SiS AGP chipsets.
102 */
103 #define AGP_SIS_ATTBASE 0x90
104 #define AGP_SIS_WINCTRL 0x94
105 #define AGP_SIS_TLBCTRL 0x97
106 #define AGP_SIS_TLBFLUSH 0x98
107
108 /*
109 * Config offsets for Ali AGP chipsets.
110 */
111 #define AGP_ALI_AGPCTRL 0xb8
112 #define AGP_ALI_ATTBASE 0xbc
113 #define AGP_ALI_TLBCTRL 0xc0
114
115 /*
116 * Config offsets for the AMD 751 chipset.
117 */
118 #define AGP_AMD751_APBASE 0x10
119 #define AGP_AMD751_REGISTERS 0x14
120 #define AGP_AMD751_APCTRL 0xac
121 #define AGP_AMD751_MODECTRL 0xb0
122 #define AGP_AMD751_MODECTRL_SYNEN 0x80
123 #define AGP_AMD751_MODECTRL2 0xb2
124 #define AGP_AMD751_MODECTRL2_G1LM 0x01
125 #define AGP_AMD751_MODECTRL2_GPDCE 0x02
126 #define AGP_AMD751_MODECTRL2_NGSE 0x08
127
128 /*
129 * Memory mapped register offsets for AMD 751 chipset.
130 */
131 #define AGP_AMD751_CAPS 0x00
132 #define AGP_AMD751_CAPS_EHI 0x0800
133 #define AGP_AMD751_CAPS_P2P 0x0400
134 #define AGP_AMD751_CAPS_MPC 0x0200
135 #define AGP_AMD751_CAPS_VBE 0x0100
136 #define AGP_AMD751_CAPS_REV 0x00ff
137 #define AGP_AMD751_STATUS 0x02
138 #define AGP_AMD751_STATUS_P2PS 0x0800
139 #define AGP_AMD751_STATUS_GCS 0x0400
140 #define AGP_AMD751_STATUS_MPS 0x0200
141 #define AGP_AMD751_STATUS_VBES 0x0100
142 #define AGP_AMD751_STATUS_P2PE 0x0008
143 #define AGP_AMD751_STATUS_GCE 0x0004
144 #define AGP_AMD751_STATUS_VBEE 0x0001
145 #define AGP_AMD751_ATTBASE 0x04
146 #define AGP_AMD751_TLBCTRL 0x0c
147
148 /*
149 * Config registers for i810 device 0
150 */
151 #define AGP_I810_SMRAM 0x70
152 #define AGP_I810_SMRAM_GMS 0xc0
153 #define AGP_I810_SMRAM_GMS_DISABLED 0x00
154 #define AGP_I810_SMRAM_GMS_ENABLED_0 0x40
155 #define AGP_I810_SMRAM_GMS_ENABLED_512 0x80
156 #define AGP_I810_SMRAM_GMS_ENABLED_1024 0xc0
157 #define AGP_I810_MISCC 0x72
158 #define AGP_I810_MISCC_WINSIZE 0x0001
159 #define AGP_I810_MISCC_WINSIZE_64 0x0000
160 #define AGP_I810_MISCC_WINSIZE_32 0x0001
161 #define AGP_I810_MISCC_PLCK 0x0008
162 #define AGP_I810_MISCC_PLCK_UNLOCKED 0x0000
163 #define AGP_I810_MISCC_PLCK_LOCKED 0x0008
164 #define AGP_I810_MISCC_WPTC 0x0030
165 #define AGP_I810_MISCC_WPTC_NOLIMIT 0x0000
166 #define AGP_I810_MISCC_WPTC_62 0x0010
167 #define AGP_I810_MISCC_WPTC_50 0x0020
168 #define AGP_I810_MISCC_WPTC_37 0x0030
169 #define AGP_I810_MISCC_RPTC 0x00c0
170 #define AGP_I810_MISCC_RPTC_NOLIMIT 0x0000
171 #define AGP_I810_MISCC_RPTC_62 0x0040
172 #define AGP_I810_MISCC_RPTC_50 0x0080
173 #define AGP_I810_MISCC_RPTC_37 0x00c0
174
175 /*
176 * Config registers for i810 device 1
177 */
178 #define AGP_I810_GMADR 0x10
179 #define AGP_I810_MMADR 0x14
180
181 #define I810_PTE_VALID 0x00000001
182
183 /*
184 * Cache control
185 *
186 * Pre-Sandybridge bits
187 */
188 #define I810_PTE_MAIN_UNCACHED 0x00000000
189 #define I810_PTE_LOCAL 0x00000002 /* Non-snooped main phys memory */
190 #define I830_PTE_SYSTEM_CACHED 0x00000006 /* Snooped main phys memory */
191
192 /*
193 * Sandybridge
194 * LLC - Last Level Cache
195 * MMC - Mid Level Cache
196 */
197 #define GEN6_PTE_RESERVED 0x00000000
198 #define GEN6_PTE_UNCACHED 0x00000002 /* Do not cache */
199 #define GEN6_PTE_LLC 0x00000004 /* Cache in LLC */
200 #define GEN6_PTE_LLC_MLC 0x00000006 /* Cache in LLC and MLC */
201 #define GEN6_PTE_GFDT 0x00000008 /* Graphics Data Type */
202
203 /*
204 * Memory mapped register offsets for i810 chipset.
205 */
206 #define AGP_I810_PGTBL_CTL 0x2020
207 #define AGP_I810_PGTBL_ENABLED 0x00000001
208 /**
209 * This field determines the actual size of the global GTT on the 965
210 * and G33
211 */
212 #define AGP_I810_PGTBL_SIZE_MASK 0x0000000e
213 #define AGP_I810_PGTBL_SIZE_512KB (0 << 1)
214 #define AGP_I810_PGTBL_SIZE_256KB (1 << 1)
215 #define AGP_I810_PGTBL_SIZE_128KB (2 << 1)
216 #define AGP_I810_PGTBL_SIZE_1MB (3 << 1)
217 #define AGP_I810_PGTBL_SIZE_2MB (4 << 1)
218 #define AGP_I810_PGTBL_SIZE_1_5MB (5 << 1)
219 #define AGP_G33_GCC1_SIZE_MASK (3 << 8)
220 #define AGP_G33_GCC1_SIZE_1M (1 << 8)
221 #define AGP_G33_GCC1_SIZE_2M (2 << 8)
222 #define AGP_G4x_GCC1_SIZE_MASK (0xf << 8)
223 #define AGP_G4x_GCC1_SIZE_1M (0x1 << 8)
224 #define AGP_G4x_GCC1_SIZE_2M (0x3 << 8)
225 #define AGP_G4x_GCC1_SIZE_VT_EN (0x8 << 8)
226 #define AGP_G4x_GCC1_SIZE_VT_1M \
227 (AGP_G4x_GCC1_SIZE_1M | AGP_G4x_GCC1_SIZE_VT_EN)
228 #define AGP_G4x_GCC1_SIZE_VT_1_5M ((0x2 << 8) | AGP_G4x_GCC1_SIZE_VT_EN)
229 #define AGP_G4x_GCC1_SIZE_VT_2M \
230 (AGP_G4x_GCC1_SIZE_2M | AGP_G4x_GCC1_SIZE_VT_EN)
231
232 #define AGP_I810_DRT 0x3000
233 #define AGP_I810_DRT_UNPOPULATED 0x00
234 #define AGP_I810_DRT_POPULATED 0x01
235 #define AGP_I810_GTT 0x10000
236
237 /*
238 * Config registers for i830MG device 0
239 */
240 #define AGP_I830_GCC1 0x52
241 #define AGP_I830_GCC1_DEV2 0x08
242 #define AGP_I830_GCC1_DEV2_ENABLED 0x00
243 #define AGP_I830_GCC1_DEV2_DISABLED 0x08
244 #define AGP_I830_GCC1_GMS 0xf0 /* Top bit reserved pre-G33 */
245 #define AGP_I830_GCC1_GMS_STOLEN_512 0x20
246 #define AGP_I830_GCC1_GMS_STOLEN_1024 0x30
247 #define AGP_I830_GCC1_GMS_STOLEN_8192 0x40
248 #define AGP_I830_GCC1_GMASIZE 0x01
249 #define AGP_I830_GCC1_GMASIZE_64 0x01
250 #define AGP_I830_GCC1_GMASIZE_128 0x00
251 #define AGP_I830_HIC 0x70
252
253 /*
254 * Config registers for 852GM/855GM/865G device 0
255 */
256 #define AGP_I855_GCC1 0x52
257 #define AGP_I855_GCC1_DEV2 0x08
258 #define AGP_I855_GCC1_DEV2_ENABLED 0x00
259 #define AGP_I855_GCC1_DEV2_DISABLED 0x08
260 #define AGP_I855_GCC1_GMS 0xf0 /* Top bit reserved pre-G33 */
261 #define AGP_I855_GCC1_GMS_STOLEN_0M 0x00
262 #define AGP_I855_GCC1_GMS_STOLEN_1M 0x10
263 #define AGP_I855_GCC1_GMS_STOLEN_4M 0x20
264 #define AGP_I855_GCC1_GMS_STOLEN_8M 0x30
265 #define AGP_I855_GCC1_GMS_STOLEN_16M 0x40
266 #define AGP_I855_GCC1_GMS_STOLEN_32M 0x50
267
268 /*
269 * 852GM/855GM variant identification
270 */
271 #define AGP_I85X_CAPID 0x44
272 #define AGP_I85X_VARIANT_MASK 0x7
273 #define AGP_I85X_VARIANT_SHIFT 5
274 #define AGP_I855_GME 0x0
275 #define AGP_I855_GM 0x4
276 #define AGP_I852_GME 0x2
277 #define AGP_I852_GM 0x5
278
279 /*
280 * 915G registers
281 */
282 #define AGP_I915_GMADR 0x18
283 #define AGP_I915_MMADR 0x10
284 #define AGP_I915_GTTADR 0x1C
285 #define AGP_I915_GCC1_GMS_STOLEN_48M 0x60
286 #define AGP_I915_GCC1_GMS_STOLEN_64M 0x70
287 #define AGP_I915_DEVEN 0x54
288 #define AGP_SB_DEVEN_D2EN 0x10 /* SB+ has IGD enabled bit */
289 #define AGP_SB_DEVEN_D2EN_ENABLED 0x10 /* in different place */
290 #define AGP_SB_DEVEN_D2EN_DISABLED 0x00
291 #define AGP_I915_DEVEN_D2F0 0x08
292 #define AGP_I915_DEVEN_D2F0_ENABLED 0x08
293 #define AGP_I915_DEVEN_D2F0_DISABLED 0x00
294 #define AGP_I915_MSAC 0x62
295 #define AGP_I915_MSAC_GMASIZE 0x02
296 #define AGP_I915_MSAC_GMASIZE_128 0x02
297 #define AGP_I915_MSAC_GMASIZE_256 0x00
298 #define AGP_I915_IFPADDR 0x60
299
300 /*
301 * G33 registers
302 */
303 #define AGP_G33_MGGC_GGMS_MASK (3 << 8)
304 #define AGP_G33_MGGC_GGMS_SIZE_1M (1 << 8)
305 #define AGP_G33_MGGC_GGMS_SIZE_2M (2 << 8)
306 #define AGP_G33_GCC1_GMS_STOLEN_128M 0x80
307 #define AGP_G33_GCC1_GMS_STOLEN_256M 0x90
308
309 /*
310 * G965 registers
311 */
312 #define AGP_I965_GTTMMADR 0x10
313 #define AGP_I965_APBASE 0x18
314 #define AGP_I965_MSAC 0x62
315 #define AGP_I965_MSAC_GMASIZE_128 0x00
316 #define AGP_I965_MSAC_GMASIZE_256 0x02
317 #define AGP_I965_MSAC_GMASIZE_512 0x06
318 #define AGP_I965_PGTBL_SIZE_1MB (3 << 1)
319 #define AGP_I965_PGTBL_SIZE_2MB (4 << 1)
320 #define AGP_I965_PGTBL_SIZE_1_5MB (5 << 1)
321 #define AGP_I965_PGTBL_CTL2 0x20c4
322 #define AGP_I965_IFPADDR 0x70
323
324 /*
325 * G4X registers
326 */
327 #define AGP_G4X_GCC1_GMS_STOLEN_96M 0xa0
328 #define AGP_G4X_GCC1_GMS_STOLEN_160M 0xb0
329 #define AGP_G4X_GCC1_GMS_STOLEN_224M 0xc0
330 #define AGP_G4X_GCC1_GMS_STOLEN_352M 0xd0
331
332 /*
333 * SandyBridge/IvyBridge registers
334 */
335 #define AGP_SNB_GCC1 0x50
336 #define AGP_SNB_GMCH_GMS_STOLEN_MASK 0xF8
337 #define AGP_SNB_GMCH_GMS_STOLEN_32M (1 << 3)
338 #define AGP_SNB_GMCH_GMS_STOLEN_64M (2 << 3)
339 #define AGP_SNB_GMCH_GMS_STOLEN_96M (3 << 3)
340 #define AGP_SNB_GMCH_GMS_STOLEN_128M (4 << 3)
341 #define AGP_SNB_GMCH_GMS_STOLEN_160M (5 << 3)
342 #define AGP_SNB_GMCH_GMS_STOLEN_192M (6 << 3)
343 #define AGP_SNB_GMCH_GMS_STOLEN_224M (7 << 3)
344 #define AGP_SNB_GMCH_GMS_STOLEN_256M (8 << 3)
345 #define AGP_SNB_GMCH_GMS_STOLEN_288M (9 << 3)
346 #define AGP_SNB_GMCH_GMS_STOLEN_320M (0xa << 3)
347 #define AGP_SNB_GMCH_GMS_STOLEN_352M (0xb << 3)
348 #define AGP_SNB_GMCH_GMS_STOLEN_384M (0xc << 3)
349 #define AGP_SNB_GMCH_GMS_STOLEN_416M (0xd << 3)
350 #define AGP_SNB_GMCH_GMS_STOLEN_448M (0xe << 3)
351 #define AGP_SNB_GMCH_GMS_STOLEN_480M (0xf << 3)
352 #define AGP_SNB_GMCH_GMS_STOLEN_512M (0x10 << 3)
353 #define AGP_SNB_GTT_SIZE_0M (0 << 8)
354 #define AGP_SNB_GTT_SIZE_1M (1 << 8)
355 #define AGP_SNB_GTT_SIZE_2M (2 << 8)
356 #define AGP_SNB_GTT_SIZE_MASK (3 << 8)
357
358 #define AGP_SNB_GFX_MODE 0x02520
359
360 /*
361 * NVIDIA nForce/nForce2 registers
362 */
363 #define AGP_NVIDIA_0_APBASE 0x10
364 #define AGP_NVIDIA_0_APSIZE 0x80
365 #define AGP_NVIDIA_1_WBC 0xf0
366 #define AGP_NVIDIA_2_GARTCTRL 0xd0
367 #define AGP_NVIDIA_2_APBASE 0xd8
368 #define AGP_NVIDIA_2_APLIMIT 0xdc
369 #define AGP_NVIDIA_2_ATTBASE(i) (0xe0 + (i) * 4)
370 #define AGP_NVIDIA_3_APBASE 0x50
371 #define AGP_NVIDIA_3_APLIMIT 0x54
372
373 /*
374 * AMD64 GART registers
375 */
376 #define AGP_AMD64_APCTRL 0x90
377 #define AGP_AMD64_APBASE 0x94
378 #define AGP_AMD64_ATTBASE 0x98
379 #define AGP_AMD64_CACHECTRL 0x9c
380 #define AGP_AMD64_APCTRL_GARTEN 0x00000001
381 #define AGP_AMD64_APCTRL_SIZE_MASK 0x0000000e
382 #define AGP_AMD64_APCTRL_DISGARTCPU 0x00000010
383 #define AGP_AMD64_APCTRL_DISGARTIO 0x00000020
384 #define AGP_AMD64_APCTRL_DISWLKPRB 0x00000040
385 #define AGP_AMD64_APBASE_MASK 0x00007fff
386 #define AGP_AMD64_ATTBASE_MASK 0xfffffff0
387 #define AGP_AMD64_CACHECTRL_INVGART 0x00000001
388 #define AGP_AMD64_CACHECTRL_PTEERR 0x00000002
389
390 /*
391 * NVIDIA nForce3 registers
392 */
393 #define AGP_AMD64_NVIDIA_0_APBASE 0x10
394 #define AGP_AMD64_NVIDIA_1_APBASE1 0x50
395 #define AGP_AMD64_NVIDIA_1_APLIMIT1 0x54
396 #define AGP_AMD64_NVIDIA_1_APSIZE 0xa8
397 #define AGP_AMD64_NVIDIA_1_APBASE2 0xd8
398 #define AGP_AMD64_NVIDIA_1_APLIMIT2 0xdc
399
400 /*
401 * ULi M1689 registers
402 */
403 #define AGP_AMD64_ULI_APBASE 0x10
404 #define AGP_AMD64_ULI_HTT_FEATURE 0x50
405 #define AGP_AMD64_ULI_ENU_SCR 0x54
406
407 /*
408 * ATI IGP registers
409 */
410 #define ATI_GART_MMADDR 0x14
411 #define ATI_RS100_APSIZE 0xac
412 #define ATI_RS100_IG_AGPMODE 0xb0
413 #define ATI_RS300_APSIZE 0xf8
414 #define ATI_RS300_IG_AGPMODE 0xfc
415 #define ATI_GART_FEATURE_ID 0x00
416 #define ATI_GART_BASE 0x04
417 #define ATI_GART_CACHE_CNTRL 0x0c
418
419 #endif /* !_PCI_AGPREG_H_ */
Cache object: 5bd0ff1f12d6e0a84504eb13f5e47b54
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