Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/aha/ahareg.h
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1 /* 2 * Generic register and struct definitions for the Adaptech 154x/164x 3 * SCSI host adapters. Product specific probe and attach routines can 4 * be found in: 5 * <fill in list here> 6 * 7 * Derived from bt.c written by: 8 * 9 * Copyright (c) 1998 Justin T. Gibbs. 10 * All rights reserved. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions, and the following disclaimer, 17 * without modification, immediately at the beginning of the file. 18 * 2. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 36 #ifndef _AHAREG_H_ 37 #define _AHAREG_H_ 38 39 #include "aha.h" 40 41 #include <sys/queue.h> 42 #include <cam/scsi/scsi_all.h> 43 44 #define AHA_MAXTRANSFER_SIZE 0xffffff /* limited by 24bit counter */ 45 #define AHA_NSEG 17 /* The number of dma segments 46 * supported. */ 47 #define ALL_TARGETS (~0) 48 49 /* 50 * Control Register pp. 1-8, 1-9 (Write Only) 51 */ 52 #define CONTROL_REG 0x00 53 #define HARD_RESET 0x80 /* Hard Reset - return to POST state */ 54 #define SOFT_RESET 0x40 /* Soft Reset - Clears Adapter state */ 55 #define RESET_INTR 0x20 /* Reset/Ack Interrupt */ 56 #define RESET_SBUS 0x10 /* Drive SCSI bus reset signal */ 57 58 /* 59 * Status Register pp. 1-9, 1-10 (Read Only) 60 */ 61 #define STATUS_REG 0x00 62 #define DIAG_ACTIVE 0x80 /* Performing Internal Diags */ 63 #define DIAG_FAIL 0x40 /* Internal Diags failed */ 64 #define INIT_REQUIRED 0x20 /* MBOXes need initialization */ 65 #define HA_READY 0x10 /* HA ready for new commands */ 66 #define CMD_REG_BUSY 0x08 /* HA busy with last cmd byte */ 67 #define DATAIN_REG_READY 0x04 /* Data-in Byte available */ 68 #define STATUS_REG_RSVD 0x02 69 #define CMD_INVALID 0x01 /* Invalid Command detected */ 70 71 /* 72 * Command/Parameter Register pp. 1-10, 1-11 (Write Only) 73 */ 74 #define COMMAND_REG 0x01 75 76 /* 77 * Data in Register p. 1-11 (Read Only) 78 */ 79 #define DATAIN_REG 0x01 80 81 /* 82 * Interrupt Status Register pp. 1-12 -> 1-14 (Read Only) 83 */ 84 #define INTSTAT_REG 0x02 85 #define INTR_PENDING 0x80 /* There is a pending INTR */ 86 #define INTSTAT_REG_RSVD 0x70 87 #define SCSI_BUS_RESET 0x08 /* Bus Reset detected */ 88 #define CMD_COMPLETE 0x04 89 #define OMB_READY 0x02 /* Outgoin Mailbox Ready */ 90 #define IMB_LOADED 0x01 /* Incoming Mailbox loaded */ 91 92 /* 93 * Definitions for the "undocumented" geometry register, we just need 94 * its location. 95 */ 96 #define GEOMETRY_REG 0x03 97 98 #define AHA_NREGS (4) 99 100 /* 101 * Opcodes for Adapter commands. 102 */ 103 typedef enum { 104 AOP_NOP = 0x00, 105 AOP_INITIALIZE_MBOX = 0x01, 106 AOP_START_MBOX = 0x02, 107 AOP_EXECUTE_BIOS_CMD = 0x03, 108 AOP_INQUIRE_BOARD_ID = 0x04, 109 AOP_ENABLE_OMBR_INT = 0x05, 110 AOP_SET_SEL_TIMOUT = 0x06, 111 AOP_SET_TIME_ON_BUS = 0x07, 112 AOP_SET_TIME_OFF_BUS = 0x08, 113 AOP_SET_BUS_TRANS_RATE = 0x09, 114 AOP_INQUIRE_INST_LDEVS = 0x0A, 115 AOP_INQUIRE_CONFIG = 0x0B, 116 AOP_ENABLE_TARGET_MODE = 0x0C, 117 AOP_INQUIRE_SETUP_INFO = 0x0D, 118 AOP_WRITE_LRAM = 0x1A, 119 AOP_READ_LRAM = 0x1B, 120 AOP_WRITE_CHIP_FIFO = 0x1C, 121 AOP_READ_CHIP_FIFO = 0x1D, 122 AOP_ECHO_DATA_BYTE = 0x1F, 123 AOP_ADAPTER_DIAGNOSTICS = 0x20, 124 AOP_SET_ADAPTER_OPTIONS = 0x21, 125 AOP_SET_EEPROM = 0x22, 126 AOP_RETURN_EEPROM = 0x23, 127 AOP_ENABLE_SHADOW_RAM = 0x24, 128 AOP_INIT_BIOS_MBOX = 0x25, 129 AOP_SET_BIOS_BANK_1 = 0x26, 130 AOP_SET_BIOS_BANK_2 = 0x27, 131 AOP_RETURN_EXT_BIOS_INFO= 0x28, 132 AOP_MBOX_IF_ENABLE = 0x29, 133 AOP_SCSI_TERM_STATUS = 0x2C, 134 AOP_INQUIRE_SCAM_DEV = 0x2D, 135 AOP_SCSI_DEV_TABLE = 0x2E, 136 AOP_SCAM_OP = 0x2F, 137 AOP_START_BIOS_CMD = 0x82, 138 AOP_INQUIRE_ESETUP_INFO = 0x8D 139 } aha_op_t; 140 141 /************** Definitions of Multi-byte commands and responses ************/ 142 143 struct aha_extbios 144 { 145 u_int8_t flags; /* Bit 3 == 1 extended bios enabled */ 146 u_int8_t mailboxlock; /* mail box lock code to unlock it */ 147 }; 148 149 typedef struct { 150 u_int8_t num_mboxes; 151 u_int8_t base_addr[3]; 152 } init_24b_mbox_params_t; 153 154 typedef struct { 155 u_int8_t board_type; 156 /* These values are mostly from the aha-1540CP technical reference, but */ 157 /* with other values from the old aha1542.c driver. The values from the */ 158 /* aha-1540CP technical manual are used where conflicts arise */ 159 #define BOARD_1540_16HEAD_BIOS 0x00 160 #define BOARD_1540_64HEAD_BIOS 0x30 161 #define BOARD_1542 0x41 /* aha-1540/1542 w/64-h bios */ 162 #define BOARD_1640 0x42 /* aha-1640 */ 163 #define BOARD_1740 0x43 /* aha-1740A/1742A/1744 */ 164 #define BOARD_1542C 0x44 /* aha-1542C */ 165 #define BOARD_1542CF 0x45 /* aha-1542CF */ 166 #define BOARD_1542CP 0x46 /* aha-1542CP, plug and play */ 167 u_int8_t cust_features; 168 #define FEATURES_STANDARD 0x30 169 u_int8_t firmware_rev_major; 170 u_int8_t firmware_rev_minor; 171 } board_id_data_t; 172 173 typedef struct { 174 u_int8_t dma_chan; 175 #define DMA_CHAN_5 0x20 176 #define DMA_CHAN_6 0x40 177 #define DMA_CHAN_7 0x80 178 u_int8_t irq; 179 #define IRQ_9 0x01 180 #define IRQ_10 0x02 181 #define IRQ_11 0x04 182 #define IRQ_12 0x08 183 #define IRQ_14 0x20 184 #define IRQ_15 0x40 185 u_int8_t scsi_id; 186 } config_data_t; 187 188 typedef struct { 189 u_int8_t enable; 190 } target_mode_params_t; 191 192 typedef struct { 193 u_int8_t offset : 4, 194 period : 3, 195 sync : 1; 196 } targ_syncinfo_t; 197 198 typedef struct { 199 u_int8_t initiate_sync : 1, 200 parity_enable : 1, 201 : 6; 202 203 u_int8_t bus_transfer_rate; 204 u_int8_t time_on_bus; 205 u_int8_t time_off_bus; 206 u_int8_t num_mboxes; 207 u_int8_t mbox_base_addr[3]; 208 targ_syncinfo_t syncinfo[8]; 209 u_int8_t discinfo; 210 u_int8_t customer_sig[20]; 211 u_int8_t auto_retry; 212 u_int8_t board_switches; 213 u_int8_t firmware_cksum[2]; 214 u_int8_t bios_mbox_addr[3]; 215 } setup_data_t; 216 217 struct aha_isa_port { 218 u_int16_t addr; 219 u_int8_t bio; /* board IO offset */ 220 }; 221 222 #define AHA_NUM_ISAPORTS 6 223 224 typedef enum { 225 BIO_330 = 0, 226 BIO_334 = 1, 227 BIO_230 = 2, 228 BIO_234 = 3, 229 BIO_130 = 4, 230 BIO_134 = 5, 231 BIO_DISABLED = 6, 232 BIO_DISABLED2 = 7 233 } isa_compat_io_t; 234 235 typedef struct { 236 u_int8_t sync_rate[16]; /* Sync in 10ns units */ 237 } target_sync_info_data_t; 238 239 typedef struct { 240 u_int8_t len[3]; 241 u_int8_t addr[3]; 242 } aha_sg_t; 243 244 /********************** Mail Box definitions *******************************/ 245 246 typedef enum { 247 AMBO_FREE = 0x0, /* MBO intry is free */ 248 AMBO_START = 0x1, /* MBO activate entry */ 249 AMBO_ABORT = 0x2 /* MBO abort entry */ 250 } aha_mbo_action_code_t; 251 252 typedef struct aha_mbox_out { 253 u_int8_t action_code; 254 u_int8_t ccb_addr[3]; 255 } aha_mbox_out_t; 256 257 typedef enum { 258 AMBI_FREE = 0x0, /* MBI entry is free */ 259 AMBI_OK = 0x1, /* completed without error */ 260 AMBI_ABORT = 0x2, /* aborted ccb */ 261 AMBI_NOT_FOUND = 0x3, /* Tried to abort invalid CCB */ 262 AMBI_ERROR = 0x4 /* Completed with error */ 263 } aha_mbi_comp_code_t; 264 265 typedef struct aha_mbox_in { 266 u_int8_t comp_code; 267 u_int8_t ccb_addr[3]; 268 } aha_mbox_in_t; 269 270 /****************** Hardware CCB definition *********************************/ 271 typedef enum { 272 INITIATOR_CCB = 0x00, 273 INITIATOR_SG_CCB = 0x02, 274 INITIATOR_CCB_WRESID = 0x03, 275 INITIATOR_SG_CCB_WRESID = 0x04, 276 INITIATOR_BUS_DEV_RESET = 0x81 277 } aha_ccb_opcode_t; 278 279 typedef enum { 280 AHASTAT_NOERROR = 0x00, 281 AHASTAT_SELTIMEOUT = 0x11, 282 AHASTAT_DATARUN_ERROR = 0x12, 283 AHASTAT_UNEXPECTED_BUSFREE = 0x13, 284 AHASTAT_INVALID_PHASE = 0x14, 285 AHASTAT_INVALID_ACTION_CODE = 0x15, 286 AHASTAT_INVALID_OPCODE = 0x16, 287 AHASTAT_LINKED_CCB_LUN_MISMATCH = 0x17, 288 AHASTAT_INVALID_CCB_OR_SG_PARAM = 0x1A, 289 AHASTAT_HA_SCSI_BUS_RESET = 0x22, /* stolen from bt */ 290 AHASTAT_HA_BDR = 0x25 /* Stolen from bt */ 291 } ahastat_t; 292 293 struct aha_hccb { 294 u_int8_t opcode; /* 0 */ 295 u_int8_t lun : 3, /* 1 */ 296 datain : 1, 297 dataout : 1, 298 target : 3; 299 u_int8_t cmd_len; /* 2 */ 300 u_int8_t sense_len; /* 3 */ 301 u_int8_t data_len[3]; /* 4 */ 302 u_int8_t data_addr[3]; /* 7 */ 303 u_int8_t link_ptr[3]; /* 10 */ 304 u_int8_t link_id; /* 13 */ 305 u_int8_t ahastat; /* 14 */ 306 u_int8_t sdstat; /* 15 */ 307 u_int8_t reserved1; /* 16 */ 308 u_int8_t reserved2; /* 17 */ 309 u_int8_t scsi_cdb[16]; /* 18 */ 310 u_int8_t sense_data[SSD_FULL_SIZE]; 311 }; 312 313 typedef enum { 314 ACCB_FREE = 0x0, 315 ACCB_ACTIVE = 0x1, 316 ACCB_DEVICE_RESET = 0x2, 317 ACCB_RELEASE_SIMQ = 0x4 318 } accb_flags_t; 319 320 struct aha_ccb { 321 struct aha_hccb hccb; /* hccb assumed to be at 0 */ 322 SLIST_ENTRY(aha_ccb) links; 323 u_int32_t flags; 324 union ccb *ccb; 325 bus_dmamap_t dmamap; 326 aha_sg_t *sg_list; 327 u_int32_t sg_list_phys; 328 }; 329 330 struct sg_map_node { 331 bus_dmamap_t sg_dmamap; 332 bus_addr_t sg_physaddr; 333 aha_sg_t* sg_vaddr; 334 SLIST_ENTRY(sg_map_node) links; 335 }; 336 337 struct aha_softc { 338 bus_space_tag_t tag; 339 bus_space_handle_t bsh; 340 struct cam_sim *sim; 341 struct cam_path *path; 342 aha_mbox_out_t *cur_outbox; 343 aha_mbox_in_t *cur_inbox; 344 aha_mbox_out_t *last_outbox; 345 aha_mbox_in_t *last_inbox; 346 struct aha_ccb *aha_ccb_array; 347 SLIST_HEAD(,aha_ccb) free_aha_ccbs; 348 LIST_HEAD(,ccb_hdr) pending_ccbs; 349 u_int active_ccbs; 350 u_int32_t aha_ccb_physbase; 351 aha_ccb_opcode_t ccb_sg_opcode; 352 aha_ccb_opcode_t ccb_ccb_opcode; 353 aha_mbox_in_t *in_boxes; 354 aha_mbox_out_t *out_boxes; 355 struct scsi_sense_data *sense_buffers; 356 u_int32_t sense_buffers_physbase; 357 struct aha_ccb *recovery_accb; 358 u_int num_boxes; 359 bus_dma_tag_t parent_dmat; /* 360 * All dmat's derive from 361 * the dmat defined by our 362 * bus. 363 */ 364 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 365 bus_dma_tag_t mailbox_dmat; /* dmat for our mailboxes */ 366 bus_dmamap_t mailbox_dmamap; 367 bus_dma_tag_t ccb_dmat; /* dmat for our ccb array */ 368 bus_dmamap_t ccb_dmamap; 369 bus_dma_tag_t sg_dmat; /* dmat for our sg maps */ 370 SLIST_HEAD(, sg_map_node) sg_maps; 371 bus_addr_t mailbox_physbase; 372 u_int num_ccbs; /* Number of CCBs malloc'd */ 373 u_int max_ccbs; /* Maximum allocatable CCBs */ 374 u_int max_sg; 375 u_int unit; 376 u_int scsi_id; 377 u_int32_t extended_trans :1, 378 diff_bus :1, 379 extended_lun :1, 380 strict_rr :1, 381 tag_capable :1, 382 resource_shortage:1, 383 :26; 384 u_int16_t disc_permitted; 385 u_int16_t sync_permitted; 386 u_int8_t init_level; 387 volatile u_int8_t command_cmp; 388 volatile u_int8_t latched_status; 389 u_int32_t bios_addr; 390 u_int8_t fw_major; 391 u_int8_t fw_minor; 392 char model[32]; 393 u_int8_t boardid; 394 struct resource *irq; 395 int irqrid; 396 struct resource *port; 397 int portrid; 398 struct resource *drq; 399 int drqrid; 400 void **ih; 401 }; 402 403 extern struct aha_softc *aha_softcs[]; /* XXX Config should handle this */ 404 extern u_long aha_unit; 405 406 #define AHA_TEMP_UNIT 0xFF /* Unit for probes */ 407 struct aha_softc* aha_alloc(int, bus_space_tag_t, bus_space_handle_t); 408 int aha_attach(struct aha_softc *); 409 int aha_cmd(struct aha_softc *, aha_op_t, u_int8_t *, 410 u_int, u_int8_t *, u_int, u_int); 411 int aha_detach(struct aha_softc *); 412 int aha_fetch_adapter_info(struct aha_softc *); 413 void aha_find_probe_range(int, int *, int *); 414 void aha_free(struct aha_softc *); 415 int aha_init(struct aha_softc *); 416 void aha_intr(void *); 417 int aha_iop_from_bio(isa_compat_io_t); 418 char * aha_name(struct aha_softc *); 419 int aha_probe(struct aha_softc *); 420 421 #define DEFAULT_CMD_TIMEOUT 10000 /* 1 sec */ 422 423 #define aha_inb(aha, port) \ 424 bus_space_read_1((aha)->tag, (aha)->bsh, port) 425 426 #define aha_outb(aha, port, value) \ 427 bus_space_write_1((aha)->tag, (aha)->bsh, port, value) 428 429 /* XXX BAD */ 430 #define EXTRA_AHA 4 431 #define NAHATOT (NAHA + EXTRA_AHA) 432 433 #define ADP0100_PNP 0x00019004 /* ADP0100 */ 434 #define AHA1540_PNP 0x40159004 /* ADP1540 */ 435 #define AHA1542_PNP 0x42159004 /* ADP1542 */ 436 #define AHA1542_PNPCOMPAT 0xA000D040 /* PNP00A0 */ 437 #define ICU0091_PNP 0X91005AA4 /* ICU0091 */ 438 439 #endif /* _AHA_H_ */
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