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sys/dev/ahci/ahci.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/module.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/conf.h> 38 #include <sys/endian.h> 39 #include <sys/malloc.h> 40 #include <sys/lock.h> 41 #include <sys/mutex.h> 42 #include <sys/sbuf.h> 43 #include <sys/sysctl.h> 44 #include <machine/stdarg.h> 45 #include <machine/resource.h> 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 #include "ahci.h" 49 50 #include <cam/cam.h> 51 #include <cam/cam_ccb.h> 52 #include <cam/cam_sim.h> 53 #include <cam/cam_xpt_sim.h> 54 #include <cam/cam_debug.h> 55 56 /* local prototypes */ 57 static void ahci_intr(void *data); 58 static void ahci_intr_one(void *data); 59 static void ahci_intr_one_edge(void *data); 60 static int ahci_ch_init(device_t dev); 61 static int ahci_ch_deinit(device_t dev); 62 static int ahci_ch_suspend(device_t dev); 63 static int ahci_ch_resume(device_t dev); 64 static void ahci_ch_pm(void *arg); 65 static void ahci_ch_intr(void *arg); 66 static void ahci_ch_intr_direct(void *arg); 67 static void ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus); 68 static void ahci_begin_transaction(struct ahci_channel *ch, union ccb *ccb); 69 static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 70 static void ahci_execute_transaction(struct ahci_slot *slot); 71 static void ahci_timeout(void *arg); 72 static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et); 73 static int ahci_setup_fis(struct ahci_channel *ch, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag); 74 static void ahci_dmainit(device_t dev); 75 static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 76 static void ahci_dmafini(device_t dev); 77 static void ahci_slotsalloc(device_t dev); 78 static void ahci_slotsfree(device_t dev); 79 static void ahci_reset(struct ahci_channel *ch); 80 static void ahci_start(struct ahci_channel *ch, int fbs); 81 static void ahci_stop(struct ahci_channel *ch); 82 static void ahci_clo(struct ahci_channel *ch); 83 static void ahci_start_fr(struct ahci_channel *ch); 84 static void ahci_stop_fr(struct ahci_channel *ch); 85 static int ahci_phy_check_events(struct ahci_channel *ch, u_int32_t serr); 86 static uint32_t ahci_ch_detval(struct ahci_channel *ch, uint32_t val); 87 88 static int ahci_sata_connect(struct ahci_channel *ch); 89 static int ahci_sata_phy_reset(struct ahci_channel *ch); 90 static int ahci_wait_ready(struct ahci_channel *ch, int t, int t0); 91 92 static void ahci_issue_recovery(struct ahci_channel *ch); 93 static void ahci_process_read_log(struct ahci_channel *ch, union ccb *ccb); 94 static void ahci_process_request_sense(struct ahci_channel *ch, union ccb *ccb); 95 96 static void ahciaction(struct cam_sim *sim, union ccb *ccb); 97 static void ahcipoll(struct cam_sim *sim); 98 99 static MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers"); 100 101 #define recovery_type spriv_field0 102 #define RECOVERY_NONE 0 103 #define RECOVERY_READ_LOG 1 104 #define RECOVERY_REQUEST_SENSE 2 105 #define recovery_slot spriv_field1 106 107 static uint32_t 108 ahci_ch_detval(struct ahci_channel *ch, uint32_t val) 109 { 110 111 return ch->disablephy ? ATA_SC_DET_DISABLE : val; 112 } 113 114 int 115 ahci_ctlr_setup(device_t dev) 116 { 117 struct ahci_controller *ctlr = device_get_softc(dev); 118 /* Clear interrupts */ 119 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); 120 /* Configure CCC */ 121 if (ctlr->ccc) { 122 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); 123 ATA_OUTL(ctlr->r_mem, AHCI_CCCC, 124 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) | 125 (4 << AHCI_CCCC_CC_SHIFT) | 126 AHCI_CCCC_EN); 127 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & 128 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT; 129 if (bootverbose) { 130 device_printf(dev, 131 "CCC with %dms/4cmd enabled on vector %d\n", 132 ctlr->ccc, ctlr->cccv); 133 } 134 } 135 /* Enable AHCI interrupts */ 136 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 137 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); 138 return (0); 139 } 140 141 int 142 ahci_ctlr_reset(device_t dev) 143 { 144 struct ahci_controller *ctlr = device_get_softc(dev); 145 uint32_t v; 146 int timeout; 147 148 /* BIOS/OS Handoff */ 149 if ((ATA_INL(ctlr->r_mem, AHCI_VS) >= 0x00010200) && 150 (ATA_INL(ctlr->r_mem, AHCI_CAP2) & AHCI_CAP2_BOH) && 151 ((v = ATA_INL(ctlr->r_mem, AHCI_BOHC)) & AHCI_BOHC_OOS) == 0) { 152 /* Request OS ownership. */ 153 ATA_OUTL(ctlr->r_mem, AHCI_BOHC, v | AHCI_BOHC_OOS); 154 155 /* Wait up to 2s for BIOS ownership release. */ 156 for (timeout = 0; timeout < 80; timeout++) { 157 DELAY(25000); 158 v = ATA_INL(ctlr->r_mem, AHCI_BOHC); 159 if ((v & AHCI_BOHC_BOS) == 0) 160 break; 161 if ((v & AHCI_BOHC_BB) == 0) 162 break; 163 } 164 } 165 166 /* Enable AHCI mode */ 167 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 168 /* Reset AHCI controller */ 169 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR); 170 for (timeout = 1000; timeout > 0; timeout--) { 171 DELAY(1000); 172 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) 173 break; 174 } 175 if (timeout == 0) { 176 device_printf(dev, "AHCI controller reset failure\n"); 177 return (ENXIO); 178 } 179 /* Reenable AHCI mode */ 180 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 181 182 if (ctlr->quirks & AHCI_Q_RESTORE_CAP) { 183 /* 184 * Restore capability field. 185 * This is write to a read-only register to restore its state. 186 * On fully standard-compliant hardware this is not needed and 187 * this operation shall not take place. See ahci_pci.c for 188 * platforms using this quirk. 189 */ 190 ATA_OUTL(ctlr->r_mem, AHCI_CAP, ctlr->caps); 191 } 192 193 return (0); 194 } 195 196 int 197 ahci_attach(device_t dev) 198 { 199 struct ahci_controller *ctlr = device_get_softc(dev); 200 int error, i, speed, unit; 201 uint32_t u, version; 202 device_t child; 203 204 ctlr->dev = dev; 205 ctlr->ccc = 0; 206 resource_int_value(device_get_name(dev), 207 device_get_unit(dev), "ccc", &ctlr->ccc); 208 mtx_init(&ctlr->ch_mtx, "AHCI channels lock", NULL, MTX_DEF); 209 210 /* Setup our own memory management for channels. */ 211 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 212 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 213 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 214 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 215 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 216 ahci_free_mem(dev); 217 return (error); 218 } 219 if ((error = rman_manage_region(&ctlr->sc_iomem, 220 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 221 ahci_free_mem(dev); 222 rman_fini(&ctlr->sc_iomem); 223 return (error); 224 } 225 /* Get the HW capabilities */ 226 version = ATA_INL(ctlr->r_mem, AHCI_VS); 227 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 228 if (version >= 0x00010200) 229 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2); 230 if (ctlr->caps & AHCI_CAP_EMS) 231 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL); 232 233 if (ctlr->quirks & AHCI_Q_FORCE_PI) { 234 /* 235 * Enable ports. 236 * The spec says that BIOS sets up bits corresponding to 237 * available ports. On platforms where this information 238 * is missing, the driver can define available ports on its own. 239 */ 240 int nports = (ctlr->caps & AHCI_CAP_NPMASK) + 1; 241 int nmask = (1 << nports) - 1; 242 243 ATA_OUTL(ctlr->r_mem, AHCI_PI, nmask); 244 device_printf(dev, "Forcing PI to %d ports (mask = %x)\n", 245 nports, nmask); 246 } 247 248 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); 249 250 /* Identify and set separate quirks for HBA and RAID f/w Marvells. */ 251 if ((ctlr->quirks & AHCI_Q_ALTSIG) && 252 (ctlr->caps & AHCI_CAP_SPM) == 0) 253 ctlr->quirks |= AHCI_Q_NOBSYRES; 254 255 if (ctlr->quirks & AHCI_Q_1CH) { 256 ctlr->caps &= ~AHCI_CAP_NPMASK; 257 ctlr->ichannels &= 0x01; 258 } 259 if (ctlr->quirks & AHCI_Q_2CH) { 260 ctlr->caps &= ~AHCI_CAP_NPMASK; 261 ctlr->caps |= 1; 262 ctlr->ichannels &= 0x03; 263 } 264 if (ctlr->quirks & AHCI_Q_4CH) { 265 ctlr->caps &= ~AHCI_CAP_NPMASK; 266 ctlr->caps |= 3; 267 ctlr->ichannels &= 0x0f; 268 } 269 ctlr->channels = MAX(flsl(ctlr->ichannels), 270 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 271 if (ctlr->quirks & AHCI_Q_NOPMP) 272 ctlr->caps &= ~AHCI_CAP_SPM; 273 if (ctlr->quirks & AHCI_Q_NONCQ) 274 ctlr->caps &= ~AHCI_CAP_SNCQ; 275 if ((ctlr->caps & AHCI_CAP_CCCS) == 0) 276 ctlr->ccc = 0; 277 ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC); 278 279 /* Create controller-wide DMA tag. */ 280 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 281 (ctlr->caps & AHCI_CAP_64BIT) ? BUS_SPACE_MAXADDR : 282 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 283 BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, 284 ctlr->dma_coherent ? BUS_DMA_COHERENT : 0, NULL, NULL, 285 &ctlr->dma_tag)) { 286 ahci_free_mem(dev); 287 rman_fini(&ctlr->sc_iomem); 288 return (ENXIO); 289 } 290 291 ahci_ctlr_setup(dev); 292 293 /* Setup interrupts. */ 294 if ((error = ahci_setup_interrupt(dev)) != 0) { 295 bus_dma_tag_destroy(ctlr->dma_tag); 296 ahci_free_mem(dev); 297 rman_fini(&ctlr->sc_iomem); 298 return (error); 299 } 300 301 i = 0; 302 for (u = ctlr->ichannels; u != 0; u >>= 1) 303 i += (u & 1); 304 ctlr->direct = (ctlr->msi && (ctlr->numirqs > 1 || i <= 3)); 305 resource_int_value(device_get_name(dev), device_get_unit(dev), 306 "direct", &ctlr->direct); 307 /* Announce HW capabilities. */ 308 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT; 309 device_printf(dev, 310 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n", 311 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 312 ((version >> 4) & 0xf0) + (version & 0x0f), 313 (ctlr->caps & AHCI_CAP_NPMASK) + 1, 314 ((speed == 1) ? "1.5":((speed == 2) ? "3": 315 ((speed == 3) ? "6":"?"))), 316 (ctlr->caps & AHCI_CAP_SPM) ? 317 "supported" : "not supported", 318 (ctlr->caps & AHCI_CAP_FBSS) ? 319 " with FBS" : ""); 320 if (ctlr->quirks != 0) { 321 device_printf(dev, "quirks=0x%b\n", ctlr->quirks, 322 AHCI_Q_BIT_STRING); 323 } 324 if (bootverbose) { 325 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 326 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"", 327 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"", 328 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"", 329 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"", 330 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"", 331 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"", 332 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"", 333 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"", 334 ((speed == 1) ? "1.5":((speed == 2) ? "3": 335 ((speed == 3) ? "6":"?")))); 336 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 337 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"", 338 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"", 339 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"", 340 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"", 341 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"", 342 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"", 343 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 344 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"", 345 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"", 346 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"", 347 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 348 } 349 if (bootverbose && version >= 0x00010200) { 350 device_printf(dev, "Caps2:%s%s%s%s%s%s\n", 351 (ctlr->caps2 & AHCI_CAP2_DESO) ? " DESO":"", 352 (ctlr->caps2 & AHCI_CAP2_SADM) ? " SADM":"", 353 (ctlr->caps2 & AHCI_CAP2_SDS) ? " SDS":"", 354 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"", 355 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"", 356 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":""); 357 } 358 /* Attach all channels on this controller */ 359 for (unit = 0; unit < ctlr->channels; unit++) { 360 child = device_add_child(dev, "ahcich", -1); 361 if (child == NULL) { 362 device_printf(dev, "failed to add channel device\n"); 363 continue; 364 } 365 device_set_ivars(child, (void *)(intptr_t)unit); 366 if ((ctlr->ichannels & (1 << unit)) == 0) 367 device_disable(child); 368 } 369 /* Attach any remapped NVME device */ 370 for (; unit < ctlr->channels + ctlr->remapped_devices; unit++) { 371 child = device_add_child(dev, "nvme", -1); 372 if (child == NULL) { 373 device_printf(dev, "failed to add remapped NVMe device"); 374 continue; 375 } 376 device_set_ivars(child, (void *)(intptr_t)(unit | AHCI_REMAPPED_UNIT)); 377 } 378 379 int em = (ctlr->caps & AHCI_CAP_EMS) != 0; 380 resource_int_value(device_get_name(dev), device_get_unit(dev), 381 "em", &em); 382 if (em) { 383 child = device_add_child(dev, "ahciem", -1); 384 if (child == NULL) 385 device_printf(dev, "failed to add enclosure device\n"); 386 else 387 device_set_ivars(child, (void *)(intptr_t)AHCI_EM_UNIT); 388 } 389 bus_generic_attach(dev); 390 return (0); 391 } 392 393 int 394 ahci_detach(device_t dev) 395 { 396 struct ahci_controller *ctlr = device_get_softc(dev); 397 int i; 398 399 /* Detach & delete all children */ 400 device_delete_children(dev); 401 402 /* Free interrupts. */ 403 for (i = 0; i < ctlr->numirqs; i++) { 404 if (ctlr->irqs[i].r_irq) { 405 bus_teardown_intr(dev, ctlr->irqs[i].r_irq, 406 ctlr->irqs[i].handle); 407 bus_release_resource(dev, SYS_RES_IRQ, 408 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq); 409 } 410 } 411 bus_dma_tag_destroy(ctlr->dma_tag); 412 /* Free memory. */ 413 rman_fini(&ctlr->sc_iomem); 414 ahci_free_mem(dev); 415 mtx_destroy(&ctlr->ch_mtx); 416 return (0); 417 } 418 419 void 420 ahci_free_mem(device_t dev) 421 { 422 struct ahci_controller *ctlr = device_get_softc(dev); 423 424 /* Release memory resources */ 425 if (ctlr->r_mem) 426 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 427 if (ctlr->r_msix_table) 428 bus_release_resource(dev, SYS_RES_MEMORY, 429 ctlr->r_msix_tab_rid, ctlr->r_msix_table); 430 if (ctlr->r_msix_pba) 431 bus_release_resource(dev, SYS_RES_MEMORY, 432 ctlr->r_msix_pba_rid, ctlr->r_msix_pba); 433 434 ctlr->r_msix_pba = ctlr->r_mem = ctlr->r_msix_table = NULL; 435 } 436 437 int 438 ahci_setup_interrupt(device_t dev) 439 { 440 struct ahci_controller *ctlr = device_get_softc(dev); 441 int i; 442 443 /* Check for single MSI vector fallback. */ 444 if (ctlr->numirqs > 1 && 445 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) { 446 device_printf(dev, "Falling back to one MSI\n"); 447 ctlr->numirqs = 1; 448 } 449 450 /* Ensure we don't overrun irqs. */ 451 if (ctlr->numirqs > AHCI_MAX_IRQS) { 452 device_printf(dev, "Too many irqs %d > %d (clamping)\n", 453 ctlr->numirqs, AHCI_MAX_IRQS); 454 ctlr->numirqs = AHCI_MAX_IRQS; 455 } 456 457 /* Allocate all IRQs. */ 458 for (i = 0; i < ctlr->numirqs; i++) { 459 ctlr->irqs[i].ctlr = ctlr; 460 ctlr->irqs[i].r_irq_rid = i + (ctlr->msi ? 1 : 0); 461 if (ctlr->channels == 1 && !ctlr->ccc && ctlr->msi) 462 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 463 else if (ctlr->numirqs == 1 || i >= ctlr->channels || 464 (ctlr->ccc && i == ctlr->cccv)) 465 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL; 466 else if (ctlr->channels > ctlr->numirqs && 467 i == ctlr->numirqs - 1) 468 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER; 469 else 470 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 471 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 472 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 473 device_printf(dev, "unable to map interrupt\n"); 474 return (ENXIO); 475 } 476 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL, 477 (ctlr->irqs[i].mode != AHCI_IRQ_MODE_ONE) ? ahci_intr : 478 ((ctlr->quirks & AHCI_Q_EDGEIS) ? ahci_intr_one_edge : 479 ahci_intr_one), 480 &ctlr->irqs[i], &ctlr->irqs[i].handle))) { 481 /* SOS XXX release r_irq */ 482 device_printf(dev, "unable to setup interrupt\n"); 483 return (ENXIO); 484 } 485 if (ctlr->numirqs > 1) { 486 bus_describe_intr(dev, ctlr->irqs[i].r_irq, 487 ctlr->irqs[i].handle, 488 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ? 489 "ch%d" : "%d", i); 490 } 491 } 492 return (0); 493 } 494 495 /* 496 * Common case interrupt handler. 497 */ 498 static void 499 ahci_intr(void *data) 500 { 501 struct ahci_controller_irq *irq = data; 502 struct ahci_controller *ctlr = irq->ctlr; 503 u_int32_t is, ise = 0; 504 void *arg; 505 int unit; 506 507 if (irq->mode == AHCI_IRQ_MODE_ALL) { 508 unit = 0; 509 if (ctlr->ccc) 510 is = ctlr->ichannels; 511 else 512 is = ATA_INL(ctlr->r_mem, AHCI_IS); 513 } else { /* AHCI_IRQ_MODE_AFTER */ 514 unit = irq->r_irq_rid - 1; 515 is = ATA_INL(ctlr->r_mem, AHCI_IS); 516 is &= (0xffffffff << unit); 517 } 518 /* CCC interrupt is edge triggered. */ 519 if (ctlr->ccc) 520 ise = 1 << ctlr->cccv; 521 /* Some controllers have edge triggered IS. */ 522 if (ctlr->quirks & AHCI_Q_EDGEIS) 523 ise |= is; 524 if (ise != 0) 525 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise); 526 for (; unit < ctlr->channels; unit++) { 527 if ((is & (1 << unit)) != 0 && 528 (arg = ctlr->interrupt[unit].argument)) { 529 ctlr->interrupt[unit].function(arg); 530 } 531 } 532 for (; unit < ctlr->channels + ctlr->remapped_devices; unit++) { 533 if ((arg = ctlr->interrupt[unit].argument)) { 534 ctlr->interrupt[unit].function(arg); 535 } 536 } 537 538 /* AHCI declares level triggered IS. */ 539 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 540 ATA_OUTL(ctlr->r_mem, AHCI_IS, is); 541 ATA_RBL(ctlr->r_mem, AHCI_IS); 542 } 543 544 /* 545 * Simplified interrupt handler for multivector MSI mode. 546 */ 547 static void 548 ahci_intr_one(void *data) 549 { 550 struct ahci_controller_irq *irq = data; 551 struct ahci_controller *ctlr = irq->ctlr; 552 void *arg; 553 int unit; 554 555 unit = irq->r_irq_rid - 1; 556 if ((arg = ctlr->interrupt[unit].argument)) 557 ctlr->interrupt[unit].function(arg); 558 /* AHCI declares level triggered IS. */ 559 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 560 ATA_RBL(ctlr->r_mem, AHCI_IS); 561 } 562 563 static void 564 ahci_intr_one_edge(void *data) 565 { 566 struct ahci_controller_irq *irq = data; 567 struct ahci_controller *ctlr = irq->ctlr; 568 void *arg; 569 int unit; 570 571 unit = irq->r_irq_rid - 1; 572 /* Some controllers have edge triggered IS. */ 573 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 574 if ((arg = ctlr->interrupt[unit].argument)) 575 ctlr->interrupt[unit].function(arg); 576 ATA_RBL(ctlr->r_mem, AHCI_IS); 577 } 578 579 struct resource * 580 ahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 581 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 582 { 583 struct ahci_controller *ctlr = device_get_softc(dev); 584 struct resource *res; 585 rman_res_t st; 586 int offset, size, unit; 587 bool is_em, is_remapped; 588 589 unit = (intptr_t)device_get_ivars(child); 590 is_em = is_remapped = false; 591 if (unit & AHCI_REMAPPED_UNIT) { 592 unit &= AHCI_UNIT; 593 unit -= ctlr->channels; 594 is_remapped = true; 595 } else if (unit & AHCI_EM_UNIT) { 596 unit &= AHCI_UNIT; 597 is_em = true; 598 } 599 res = NULL; 600 switch (type) { 601 case SYS_RES_MEMORY: 602 if (is_remapped) { 603 offset = ctlr->remap_offset + unit * ctlr->remap_size; 604 size = ctlr->remap_size; 605 } else if (!is_em) { 606 offset = AHCI_OFFSET + (unit << 7); 607 size = 128; 608 } else if ((ctlr->caps & AHCI_CAP_EMS) == 0) { 609 break; 610 } else if (*rid == 0) { 611 offset = AHCI_EM_CTL; 612 size = 4; 613 } else { 614 offset = (ctlr->emloc & 0xffff0000) >> 14; 615 size = (ctlr->emloc & 0x0000ffff) << 2; 616 if (*rid != 1) { 617 if (*rid == 2 && (ctlr->capsem & 618 (AHCI_EM_XMT | AHCI_EM_SMB)) == 0) 619 offset += size; 620 else 621 break; 622 } 623 } 624 st = rman_get_start(ctlr->r_mem); 625 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 626 st + offset + size - 1, size, RF_ACTIVE, child); 627 if (res) { 628 bus_space_handle_t bsh; 629 bus_space_tag_t bst; 630 bsh = rman_get_bushandle(ctlr->r_mem); 631 bst = rman_get_bustag(ctlr->r_mem); 632 bus_space_subregion(bst, bsh, offset, 128, &bsh); 633 rman_set_bushandle(res, bsh); 634 rman_set_bustag(res, bst); 635 } 636 break; 637 case SYS_RES_IRQ: 638 if (*rid == ATA_IRQ_RID) 639 res = ctlr->irqs[0].r_irq; 640 break; 641 } 642 return (res); 643 } 644 645 int 646 ahci_release_resource(device_t dev, device_t child, int type, int rid, 647 struct resource *r) 648 { 649 650 switch (type) { 651 case SYS_RES_MEMORY: 652 rman_release_resource(r); 653 return (0); 654 case SYS_RES_IRQ: 655 if (rid != ATA_IRQ_RID) 656 return (ENOENT); 657 return (0); 658 } 659 return (EINVAL); 660 } 661 662 int 663 ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 664 int flags, driver_filter_t *filter, driver_intr_t *function, 665 void *argument, void **cookiep) 666 { 667 struct ahci_controller *ctlr = device_get_softc(dev); 668 int unit = (intptr_t)device_get_ivars(child) & AHCI_UNIT; 669 670 if (filter != NULL) { 671 printf("ahci.c: we cannot use a filter here\n"); 672 return (EINVAL); 673 } 674 ctlr->interrupt[unit].function = function; 675 ctlr->interrupt[unit].argument = argument; 676 return (0); 677 } 678 679 int 680 ahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 681 void *cookie) 682 { 683 struct ahci_controller *ctlr = device_get_softc(dev); 684 int unit = (intptr_t)device_get_ivars(child) & AHCI_UNIT; 685 686 ctlr->interrupt[unit].function = NULL; 687 ctlr->interrupt[unit].argument = NULL; 688 return (0); 689 } 690 691 int 692 ahci_print_child(device_t dev, device_t child) 693 { 694 intptr_t ivars; 695 int retval; 696 697 retval = bus_print_child_header(dev, child); 698 ivars = (intptr_t)device_get_ivars(child); 699 if ((ivars & AHCI_EM_UNIT) == 0) 700 retval += printf(" at channel %d", (int)ivars & AHCI_UNIT); 701 retval += bus_print_child_footer(dev, child); 702 return (retval); 703 } 704 705 int 706 ahci_child_location(device_t dev, device_t child, struct sbuf *sb) 707 { 708 intptr_t ivars; 709 710 ivars = (intptr_t)device_get_ivars(child); 711 if ((ivars & AHCI_EM_UNIT) == 0) 712 sbuf_printf(sb, "channel=%d", (int)ivars & AHCI_UNIT); 713 return (0); 714 } 715 716 bus_dma_tag_t 717 ahci_get_dma_tag(device_t dev, device_t child) 718 { 719 struct ahci_controller *ctlr = device_get_softc(dev); 720 721 return (ctlr->dma_tag); 722 } 723 724 void 725 ahci_attached(device_t dev, struct ahci_channel *ch) 726 { 727 struct ahci_controller *ctlr = device_get_softc(dev); 728 729 mtx_lock(&ctlr->ch_mtx); 730 ctlr->ch[ch->unit] = ch; 731 mtx_unlock(&ctlr->ch_mtx); 732 } 733 734 void 735 ahci_detached(device_t dev, struct ahci_channel *ch) 736 { 737 struct ahci_controller *ctlr = device_get_softc(dev); 738 739 mtx_lock(&ctlr->ch_mtx); 740 mtx_lock(&ch->mtx); 741 ctlr->ch[ch->unit] = NULL; 742 mtx_unlock(&ch->mtx); 743 mtx_unlock(&ctlr->ch_mtx); 744 } 745 746 struct ahci_channel * 747 ahci_getch(device_t dev, int n) 748 { 749 struct ahci_controller *ctlr = device_get_softc(dev); 750 struct ahci_channel *ch; 751 752 KASSERT(n >= 0 && n < AHCI_MAX_PORTS, ("Bad channel number %d", n)); 753 mtx_lock(&ctlr->ch_mtx); 754 ch = ctlr->ch[n]; 755 if (ch != NULL) 756 mtx_lock(&ch->mtx); 757 mtx_unlock(&ctlr->ch_mtx); 758 return (ch); 759 } 760 761 void 762 ahci_putch(struct ahci_channel *ch) 763 { 764 765 mtx_unlock(&ch->mtx); 766 } 767 768 static int 769 ahci_ch_probe(device_t dev) 770 { 771 772 device_set_desc_copy(dev, "AHCI channel"); 773 return (BUS_PROBE_DEFAULT); 774 } 775 776 static int 777 ahci_ch_disablephy_proc(SYSCTL_HANDLER_ARGS) 778 { 779 struct ahci_channel *ch; 780 int error, value; 781 782 ch = arg1; 783 value = ch->disablephy; 784 error = sysctl_handle_int(oidp, &value, 0, req); 785 if (error != 0 || req->newptr == NULL || (value != 0 && value != 1)) 786 return (error); 787 788 mtx_lock(&ch->mtx); 789 ch->disablephy = value; 790 if (value) { 791 ahci_ch_deinit(ch->dev); 792 } else { 793 ahci_ch_init(ch->dev); 794 ahci_phy_check_events(ch, ATA_SE_PHY_CHANGED | ATA_SE_EXCHANGED); 795 } 796 mtx_unlock(&ch->mtx); 797 798 return (0); 799 } 800 801 static int 802 ahci_ch_attach(device_t dev) 803 { 804 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 805 struct ahci_channel *ch = device_get_softc(dev); 806 struct cam_devq *devq; 807 struct sysctl_ctx_list *ctx; 808 struct sysctl_oid *tree; 809 int rid, error, i, sata_rev = 0; 810 u_int32_t version; 811 812 ch->dev = dev; 813 ch->unit = (intptr_t)device_get_ivars(dev); 814 ch->caps = ctlr->caps; 815 ch->caps2 = ctlr->caps2; 816 ch->start = ctlr->ch_start; 817 ch->quirks = ctlr->quirks; 818 ch->vendorid = ctlr->vendorid; 819 ch->deviceid = ctlr->deviceid; 820 ch->subvendorid = ctlr->subvendorid; 821 ch->subdeviceid = ctlr->subdeviceid; 822 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1; 823 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF); 824 ch->pm_level = 0; 825 resource_int_value(device_get_name(dev), 826 device_get_unit(dev), "pm_level", &ch->pm_level); 827 STAILQ_INIT(&ch->doneq); 828 if (ch->pm_level > 3) 829 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 830 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0); 831 /* JMicron external ports (0) sometimes limited */ 832 if ((ctlr->quirks & AHCI_Q_SATA1_UNIT0) && ch->unit == 0) 833 sata_rev = 1; 834 if (ch->quirks & AHCI_Q_SATA2) 835 sata_rev = 2; 836 resource_int_value(device_get_name(dev), 837 device_get_unit(dev), "sata_rev", &sata_rev); 838 for (i = 0; i < 16; i++) { 839 ch->user[i].revision = sata_rev; 840 ch->user[i].mode = 0; 841 ch->user[i].bytecount = 8192; 842 ch->user[i].tags = ch->numslots; 843 ch->user[i].caps = 0; 844 ch->curr[i] = ch->user[i]; 845 if (ch->pm_level) { 846 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ | 847 CTS_SATA_CAPS_H_APST | 848 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST; 849 } 850 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA | 851 CTS_SATA_CAPS_H_AN; 852 } 853 rid = 0; 854 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 855 &rid, RF_ACTIVE))) 856 return (ENXIO); 857 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD); 858 version = ATA_INL(ctlr->r_mem, AHCI_VS); 859 if (version < 0x00010200 && (ctlr->caps & AHCI_CAP_FBSS)) 860 ch->chcaps |= AHCI_P_CMD_FBSCP; 861 if (ch->caps2 & AHCI_CAP2_SDS) 862 ch->chscaps = ATA_INL(ch->r_mem, AHCI_P_DEVSLP); 863 if (bootverbose) { 864 device_printf(dev, "Caps:%s%s%s%s%s%s\n", 865 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"", 866 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"", 867 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"", 868 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"", 869 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":"", 870 (ch->chscaps & AHCI_P_DEVSLP_DSP) ? " DSP":""); 871 } 872 ahci_dmainit(dev); 873 ahci_slotsalloc(dev); 874 mtx_lock(&ch->mtx); 875 ahci_ch_init(dev); 876 rid = ATA_IRQ_RID; 877 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 878 &rid, RF_SHAREABLE | RF_ACTIVE))) { 879 device_printf(dev, "Unable to map interrupt\n"); 880 error = ENXIO; 881 goto err0; 882 } 883 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 884 ctlr->direct ? ahci_ch_intr_direct : ahci_ch_intr, 885 ch, &ch->ih))) { 886 device_printf(dev, "Unable to setup interrupt\n"); 887 error = ENXIO; 888 goto err1; 889 } 890 /* Create the device queue for our SIM. */ 891 devq = cam_simq_alloc(ch->numslots); 892 if (devq == NULL) { 893 device_printf(dev, "Unable to allocate simq\n"); 894 error = ENOMEM; 895 goto err1; 896 } 897 /* Construct SIM entry */ 898 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch, 899 device_get_unit(dev), (struct mtx *)&ch->mtx, 900 (ch->quirks & AHCI_Q_NOCCS) ? 1 : min(2, ch->numslots), 901 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0, 902 devq); 903 if (ch->sim == NULL) { 904 cam_simq_free(devq); 905 device_printf(dev, "unable to allocate sim\n"); 906 error = ENOMEM; 907 goto err1; 908 } 909 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 910 device_printf(dev, "unable to register xpt bus\n"); 911 error = ENXIO; 912 goto err2; 913 } 914 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 915 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 916 device_printf(dev, "unable to create path\n"); 917 error = ENXIO; 918 goto err3; 919 } 920 if (ch->pm_level > 3) { 921 callout_reset(&ch->pm_timer, 922 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 923 ahci_ch_pm, ch); 924 } 925 mtx_unlock(&ch->mtx); 926 ahci_attached(device_get_parent(dev), ch); 927 ctx = device_get_sysctl_ctx(dev); 928 tree = device_get_sysctl_tree(dev); 929 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "disable_phy", 930 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_MPSAFE, ch, 931 0, ahci_ch_disablephy_proc, "IU", "Disable PHY"); 932 return (0); 933 934 err3: 935 xpt_bus_deregister(cam_sim_path(ch->sim)); 936 err2: 937 cam_sim_free(ch->sim, /*free_devq*/TRUE); 938 err1: 939 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 940 err0: 941 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 942 mtx_unlock(&ch->mtx); 943 mtx_destroy(&ch->mtx); 944 return (error); 945 } 946 947 static int 948 ahci_ch_detach(device_t dev) 949 { 950 struct ahci_channel *ch = device_get_softc(dev); 951 952 ahci_detached(device_get_parent(dev), ch); 953 mtx_lock(&ch->mtx); 954 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 955 /* Forget about reset. */ 956 if (ch->resetting) { 957 ch->resetting = 0; 958 xpt_release_simq(ch->sim, TRUE); 959 } 960 xpt_free_path(ch->path); 961 xpt_bus_deregister(cam_sim_path(ch->sim)); 962 cam_sim_free(ch->sim, /*free_devq*/TRUE); 963 mtx_unlock(&ch->mtx); 964 965 if (ch->pm_level > 3) 966 callout_drain(&ch->pm_timer); 967 callout_drain(&ch->reset_timer); 968 bus_teardown_intr(dev, ch->r_irq, ch->ih); 969 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 970 971 ahci_ch_deinit(dev); 972 ahci_slotsfree(dev); 973 ahci_dmafini(dev); 974 975 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 976 mtx_destroy(&ch->mtx); 977 return (0); 978 } 979 980 static int 981 ahci_ch_init(device_t dev) 982 { 983 struct ahci_channel *ch = device_get_softc(dev); 984 uint64_t work; 985 986 /* Disable port interrupts */ 987 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 988 /* Setup work areas */ 989 work = ch->dma.work_bus + AHCI_CL_OFFSET; 990 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff); 991 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32); 992 work = ch->dma.rfis_bus; 993 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff); 994 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32); 995 /* Activate the channel and power/spin up device */ 996 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 997 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 998 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) | 999 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 ))); 1000 ahci_start_fr(ch); 1001 ahci_start(ch, 1); 1002 return (0); 1003 } 1004 1005 static int 1006 ahci_ch_deinit(device_t dev) 1007 { 1008 struct ahci_channel *ch = device_get_softc(dev); 1009 1010 /* Disable port interrupts. */ 1011 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 1012 /* Reset command register. */ 1013 ahci_stop(ch); 1014 ahci_stop_fr(ch); 1015 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0); 1016 /* Allow everything, including partial and slumber modes. */ 1017 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0); 1018 /* Request slumber mode transition and give some time to get there. */ 1019 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER); 1020 DELAY(100); 1021 /* Disable PHY. */ 1022 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 1023 return (0); 1024 } 1025 1026 static int 1027 ahci_ch_suspend(device_t dev) 1028 { 1029 struct ahci_channel *ch = device_get_softc(dev); 1030 1031 mtx_lock(&ch->mtx); 1032 xpt_freeze_simq(ch->sim, 1); 1033 /* Forget about reset. */ 1034 if (ch->resetting) { 1035 ch->resetting = 0; 1036 callout_stop(&ch->reset_timer); 1037 xpt_release_simq(ch->sim, TRUE); 1038 } 1039 while (ch->oslots) 1040 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100); 1041 ahci_ch_deinit(dev); 1042 mtx_unlock(&ch->mtx); 1043 return (0); 1044 } 1045 1046 static int 1047 ahci_ch_resume(device_t dev) 1048 { 1049 struct ahci_channel *ch = device_get_softc(dev); 1050 1051 mtx_lock(&ch->mtx); 1052 ahci_ch_init(dev); 1053 ahci_reset(ch); 1054 xpt_release_simq(ch->sim, TRUE); 1055 mtx_unlock(&ch->mtx); 1056 return (0); 1057 } 1058 1059 static device_method_t ahcich_methods[] = { 1060 DEVMETHOD(device_probe, ahci_ch_probe), 1061 DEVMETHOD(device_attach, ahci_ch_attach), 1062 DEVMETHOD(device_detach, ahci_ch_detach), 1063 DEVMETHOD(device_suspend, ahci_ch_suspend), 1064 DEVMETHOD(device_resume, ahci_ch_resume), 1065 DEVMETHOD_END 1066 }; 1067 static driver_t ahcich_driver = { 1068 "ahcich", 1069 ahcich_methods, 1070 sizeof(struct ahci_channel) 1071 }; 1072 DRIVER_MODULE(ahcich, ahci, ahcich_driver, NULL, NULL); 1073 1074 struct ahci_dc_cb_args { 1075 bus_addr_t maddr; 1076 int error; 1077 }; 1078 1079 static void 1080 ahci_dmainit(device_t dev) 1081 { 1082 struct ahci_channel *ch = device_get_softc(dev); 1083 struct ahci_dc_cb_args dcba; 1084 size_t rfsize; 1085 int error; 1086 1087 /* Command area. */ 1088 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 1089 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1090 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE, 1091 0, NULL, NULL, &ch->dma.work_tag); 1092 if (error != 0) 1093 goto error; 1094 error = bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 1095 BUS_DMA_ZERO, &ch->dma.work_map); 1096 if (error != 0) 1097 goto error; 1098 error = bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 1099 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, BUS_DMA_NOWAIT); 1100 if (error != 0 || (error = dcba.error) != 0) { 1101 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1102 goto error; 1103 } 1104 ch->dma.work_bus = dcba.maddr; 1105 /* FIS receive area. */ 1106 if (ch->chcaps & AHCI_P_CMD_FBSCP) 1107 rfsize = 4096; 1108 else 1109 rfsize = 256; 1110 error = bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0, 1111 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1112 NULL, NULL, rfsize, 1, rfsize, 1113 0, NULL, NULL, &ch->dma.rfis_tag); 1114 if (error != 0) 1115 goto error; 1116 error = bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0, 1117 &ch->dma.rfis_map); 1118 if (error != 0) 1119 goto error; 1120 error = bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis, 1121 rfsize, ahci_dmasetupc_cb, &dcba, BUS_DMA_NOWAIT); 1122 if (error != 0 || (error = dcba.error) != 0) { 1123 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1124 goto error; 1125 } 1126 ch->dma.rfis_bus = dcba.maddr; 1127 /* Data area. */ 1128 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 1129 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 1130 NULL, NULL, 1131 AHCI_SG_ENTRIES * PAGE_SIZE, AHCI_SG_ENTRIES, AHCI_PRD_MAX, 1132 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag); 1133 if (error != 0) 1134 goto error; 1135 return; 1136 1137 error: 1138 device_printf(dev, "WARNING - DMA initialization failed, error %d\n", 1139 error); 1140 ahci_dmafini(dev); 1141 } 1142 1143 static void 1144 ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 1145 { 1146 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc; 1147 1148 if (!(dcba->error = error)) 1149 dcba->maddr = segs[0].ds_addr; 1150 } 1151 1152 static void 1153 ahci_dmafini(device_t dev) 1154 { 1155 struct ahci_channel *ch = device_get_softc(dev); 1156 1157 if (ch->dma.data_tag) { 1158 bus_dma_tag_destroy(ch->dma.data_tag); 1159 ch->dma.data_tag = NULL; 1160 } 1161 if (ch->dma.rfis_bus) { 1162 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map); 1163 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 1164 ch->dma.rfis_bus = 0; 1165 ch->dma.rfis = NULL; 1166 } 1167 if (ch->dma.work_bus) { 1168 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 1169 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 1170 ch->dma.work_bus = 0; 1171 ch->dma.work = NULL; 1172 } 1173 if (ch->dma.work_tag) { 1174 bus_dma_tag_destroy(ch->dma.work_tag); 1175 ch->dma.work_tag = NULL; 1176 } 1177 } 1178 1179 static void 1180 ahci_slotsalloc(device_t dev) 1181 { 1182 struct ahci_channel *ch = device_get_softc(dev); 1183 int i; 1184 1185 /* Alloc and setup command/dma slots */ 1186 bzero(ch->slot, sizeof(ch->slot)); 1187 for (i = 0; i < ch->numslots; i++) { 1188 struct ahci_slot *slot = &ch->slot[i]; 1189 1190 slot->ch = ch; 1191 slot->slot = i; 1192 slot->state = AHCI_SLOT_EMPTY; 1193 slot->ct_offset = AHCI_CT_OFFSET + AHCI_CT_SIZE * i; 1194 slot->ccb = NULL; 1195 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 1196 1197 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 1198 device_printf(ch->dev, "FAILURE - create data_map\n"); 1199 } 1200 } 1201 1202 static void 1203 ahci_slotsfree(device_t dev) 1204 { 1205 struct ahci_channel *ch = device_get_softc(dev); 1206 int i; 1207 1208 /* Free all dma slots */ 1209 for (i = 0; i < ch->numslots; i++) { 1210 struct ahci_slot *slot = &ch->slot[i]; 1211 1212 callout_drain(&slot->timeout); 1213 if (slot->dma.data_map) { 1214 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 1215 slot->dma.data_map = NULL; 1216 } 1217 } 1218 } 1219 1220 static int 1221 ahci_phy_check_events(struct ahci_channel *ch, u_int32_t serr) 1222 { 1223 1224 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) || 1225 ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) { 1226 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1227 union ccb *ccb; 1228 1229 if (bootverbose) { 1230 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 1231 device_printf(ch->dev, "CONNECT requested\n"); 1232 else 1233 device_printf(ch->dev, "DISCONNECT requested\n"); 1234 } 1235 ahci_reset(ch); 1236 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1237 return (0); 1238 if (xpt_create_path(&ccb->ccb_h.path, NULL, 1239 cam_sim_path(ch->sim), 1240 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1241 xpt_free_ccb(ccb); 1242 return (0); 1243 } 1244 xpt_rescan(ccb); 1245 return (1); 1246 } 1247 return (0); 1248 } 1249 1250 static void 1251 ahci_cpd_check_events(struct ahci_channel *ch) 1252 { 1253 u_int32_t status; 1254 union ccb *ccb; 1255 device_t dev; 1256 1257 if (ch->pm_level == 0) 1258 return; 1259 1260 status = ATA_INL(ch->r_mem, AHCI_P_CMD); 1261 if ((status & AHCI_P_CMD_CPD) == 0) 1262 return; 1263 1264 if (bootverbose) { 1265 dev = ch->dev; 1266 if (status & AHCI_P_CMD_CPS) { 1267 device_printf(dev, "COLD CONNECT requested\n"); 1268 } else 1269 device_printf(dev, "COLD DISCONNECT requested\n"); 1270 } 1271 ahci_reset(ch); 1272 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1273 return; 1274 if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim), 1275 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1276 xpt_free_ccb(ccb); 1277 return; 1278 } 1279 xpt_rescan(ccb); 1280 } 1281 1282 static void 1283 ahci_notify_events(struct ahci_channel *ch, u_int32_t status) 1284 { 1285 struct cam_path *dpath; 1286 int i; 1287 1288 if (ch->caps & AHCI_CAP_SSNTF) 1289 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status); 1290 if (bootverbose) 1291 device_printf(ch->dev, "SNTF 0x%04x\n", status); 1292 for (i = 0; i < 16; i++) { 1293 if ((status & (1 << i)) == 0) 1294 continue; 1295 if (xpt_create_path(&dpath, NULL, 1296 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 1297 xpt_async(AC_SCSI_AEN, dpath, NULL); 1298 xpt_free_path(dpath); 1299 } 1300 } 1301 } 1302 1303 static void 1304 ahci_done(struct ahci_channel *ch, union ccb *ccb) 1305 { 1306 1307 mtx_assert(&ch->mtx, MA_OWNED); 1308 if ((ccb->ccb_h.func_code & XPT_FC_QUEUED) == 0 || 1309 ch->batch == 0) { 1310 xpt_done(ccb); 1311 return; 1312 } 1313 1314 STAILQ_INSERT_TAIL(&ch->doneq, &ccb->ccb_h, sim_links.stqe); 1315 } 1316 1317 static void 1318 ahci_ch_intr(void *arg) 1319 { 1320 struct ahci_channel *ch = (struct ahci_channel *)arg; 1321 uint32_t istatus; 1322 1323 /* Read interrupt statuses. */ 1324 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1325 1326 mtx_lock(&ch->mtx); 1327 ahci_ch_intr_main(ch, istatus); 1328 mtx_unlock(&ch->mtx); 1329 } 1330 1331 static void 1332 ahci_ch_intr_direct(void *arg) 1333 { 1334 struct ahci_channel *ch = (struct ahci_channel *)arg; 1335 struct ccb_hdr *ccb_h; 1336 uint32_t istatus; 1337 STAILQ_HEAD(, ccb_hdr) tmp_doneq = STAILQ_HEAD_INITIALIZER(tmp_doneq); 1338 1339 /* Read interrupt statuses. */ 1340 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1341 1342 mtx_lock(&ch->mtx); 1343 ch->batch = 1; 1344 ahci_ch_intr_main(ch, istatus); 1345 ch->batch = 0; 1346 /* 1347 * Prevent the possibility of issues caused by processing the queue 1348 * while unlocked below by moving the contents to a local queue. 1349 */ 1350 STAILQ_CONCAT(&tmp_doneq, &ch->doneq); 1351 mtx_unlock(&ch->mtx); 1352 while ((ccb_h = STAILQ_FIRST(&tmp_doneq)) != NULL) { 1353 STAILQ_REMOVE_HEAD(&tmp_doneq, sim_links.stqe); 1354 xpt_done_direct((union ccb *)ccb_h); 1355 } 1356 } 1357 1358 static void 1359 ahci_ch_pm(void *arg) 1360 { 1361 struct ahci_channel *ch = (struct ahci_channel *)arg; 1362 uint32_t work; 1363 1364 if (ch->numrslots != 0) 1365 return; 1366 work = ATA_INL(ch->r_mem, AHCI_P_CMD); 1367 if (ch->pm_level == 4) 1368 work |= AHCI_P_CMD_PARTIAL; 1369 else 1370 work |= AHCI_P_CMD_SLUMBER; 1371 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work); 1372 } 1373 1374 static void 1375 ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus) 1376 { 1377 uint32_t cstatus, serr = 0, sntf = 0, ok, err; 1378 enum ahci_err_type et; 1379 int i, ccs, port, reset = 0; 1380 1381 /* Clear interrupt statuses. */ 1382 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus); 1383 /* Read command statuses. */ 1384 if (ch->numtslots != 0) 1385 cstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1386 else 1387 cstatus = 0; 1388 if (ch->numrslots != ch->numtslots) 1389 cstatus |= ATA_INL(ch->r_mem, AHCI_P_CI); 1390 /* Read SNTF in one of possible ways. */ 1391 if ((istatus & AHCI_P_IX_SDB) && 1392 (ch->pm_present || ch->curr[0].atapi != 0)) { 1393 if (ch->caps & AHCI_CAP_SSNTF) 1394 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF); 1395 else if (ch->fbs_enabled) { 1396 u_int8_t *fis = ch->dma.rfis + 0x58; 1397 1398 for (i = 0; i < 16; i++) { 1399 if (fis[1] & 0x80) { 1400 fis[1] &= 0x7f; 1401 sntf |= 1 << i; 1402 } 1403 fis += 256; 1404 } 1405 } else { 1406 u_int8_t *fis = ch->dma.rfis + 0x58; 1407 1408 if (fis[1] & 0x80) 1409 sntf = (1 << (fis[1] & 0x0f)); 1410 } 1411 } 1412 /* Process PHY events */ 1413 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF | 1414 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1415 serr = ATA_INL(ch->r_mem, AHCI_P_SERR); 1416 if (serr) { 1417 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr); 1418 reset = ahci_phy_check_events(ch, serr); 1419 } 1420 } 1421 /* Process cold presence detection events */ 1422 if ((istatus & AHCI_P_IX_CPD) && !reset) 1423 ahci_cpd_check_events(ch); 1424 /* Process command errors */ 1425 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF | 1426 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1427 if (ch->quirks & AHCI_Q_NOCCS) { 1428 /* 1429 * ASMedia chips sometimes report failed commands as 1430 * completed. Count all running commands as failed. 1431 */ 1432 cstatus |= ch->rslots; 1433 1434 /* They also report wrong CCS, so try to guess one. */ 1435 ccs = powerof2(cstatus) ? ffs(cstatus) - 1 : -1; 1436 } else { 1437 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & 1438 AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT; 1439 } 1440 //device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n", 1441 // __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD), 1442 // serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs); 1443 port = -1; 1444 if (ch->fbs_enabled) { 1445 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS); 1446 if (fbs & AHCI_P_FBS_SDE) { 1447 port = (fbs & AHCI_P_FBS_DWE) 1448 >> AHCI_P_FBS_DWE_SHIFT; 1449 } else { 1450 for (i = 0; i < 16; i++) { 1451 if (ch->numrslotspd[i] == 0) 1452 continue; 1453 if (port == -1) 1454 port = i; 1455 else if (port != i) { 1456 port = -2; 1457 break; 1458 } 1459 } 1460 } 1461 } 1462 err = ch->rslots & cstatus; 1463 } else { 1464 ccs = 0; 1465 err = 0; 1466 port = -1; 1467 } 1468 /* Complete all successful commands. */ 1469 ok = ch->rslots & ~cstatus; 1470 for (i = 0; i < ch->numslots; i++) { 1471 if ((ok >> i) & 1) 1472 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE); 1473 } 1474 /* On error, complete the rest of commands with error statuses. */ 1475 if (err) { 1476 if (ch->frozen) { 1477 union ccb *fccb = ch->frozen; 1478 ch->frozen = NULL; 1479 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1480 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1481 xpt_freeze_devq(fccb->ccb_h.path, 1); 1482 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1483 } 1484 ahci_done(ch, fccb); 1485 } 1486 for (i = 0; i < ch->numslots; i++) { 1487 /* XXX: requests in loading state. */ 1488 if (((err >> i) & 1) == 0) 1489 continue; 1490 if (port >= 0 && 1491 ch->slot[i].ccb->ccb_h.target_id != port) 1492 continue; 1493 if (istatus & AHCI_P_IX_TFE) { 1494 if (port != -2) { 1495 /* Task File Error */ 1496 if (ch->numtslotspd[ 1497 ch->slot[i].ccb->ccb_h.target_id] == 0) { 1498 /* Untagged operation. */ 1499 if (i == ccs) 1500 et = AHCI_ERR_TFE; 1501 else 1502 et = AHCI_ERR_INNOCENT; 1503 } else { 1504 /* Tagged operation. */ 1505 et = AHCI_ERR_NCQ; 1506 } 1507 } else { 1508 et = AHCI_ERR_TFE; 1509 ch->fatalerr = 1; 1510 } 1511 } else if (istatus & AHCI_P_IX_IF) { 1512 if (ch->numtslots == 0 && i != ccs && port != -2) 1513 et = AHCI_ERR_INNOCENT; 1514 else 1515 et = AHCI_ERR_SATA; 1516 } else 1517 et = AHCI_ERR_INVALID; 1518 ahci_end_transaction(&ch->slot[i], et); 1519 } 1520 /* 1521 * We can't reinit port if there are some other 1522 * commands active, use resume to complete them. 1523 */ 1524 if (ch->rslots != 0 && !ch->recoverycmd) 1525 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC); 1526 } 1527 /* Process NOTIFY events */ 1528 if (sntf) 1529 ahci_notify_events(ch, sntf); 1530 } 1531 1532 /* Must be called with channel locked. */ 1533 static int 1534 ahci_check_collision(struct ahci_channel *ch, union ccb *ccb) 1535 { 1536 int t = ccb->ccb_h.target_id; 1537 1538 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1539 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1540 /* Tagged command while we have no supported tag free. */ 1541 if (((~ch->oslots) & (0xffffffff >> (32 - 1542 ch->curr[t].tags))) == 0) 1543 return (1); 1544 /* If we have FBS */ 1545 if (ch->fbs_enabled) { 1546 /* Tagged command while untagged are active. */ 1547 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0) 1548 return (1); 1549 } else { 1550 /* Tagged command while untagged are active. */ 1551 if (ch->numrslots != 0 && ch->numtslots == 0) 1552 return (1); 1553 /* Tagged command while tagged to other target is active. */ 1554 if (ch->numtslots != 0 && 1555 ch->taggedtarget != ccb->ccb_h.target_id) 1556 return (1); 1557 } 1558 } else { 1559 /* If we have FBS */ 1560 if (ch->fbs_enabled) { 1561 /* Untagged command while tagged are active. */ 1562 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0) 1563 return (1); 1564 } else { 1565 /* Untagged command while tagged are active. */ 1566 if (ch->numrslots != 0 && ch->numtslots != 0) 1567 return (1); 1568 } 1569 } 1570 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1571 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 1572 /* Atomic command while anything active. */ 1573 if (ch->numrslots != 0) 1574 return (1); 1575 } 1576 /* We have some atomic command running. */ 1577 if (ch->aslots != 0) 1578 return (1); 1579 return (0); 1580 } 1581 1582 /* Must be called with channel locked. */ 1583 static void 1584 ahci_begin_transaction(struct ahci_channel *ch, union ccb *ccb) 1585 { 1586 struct ahci_slot *slot; 1587 int tag, tags; 1588 1589 /* Choose empty slot. */ 1590 tags = ch->numslots; 1591 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1592 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) 1593 tags = ch->curr[ccb->ccb_h.target_id].tags; 1594 if (ch->lastslot + 1 < tags) 1595 tag = ffs(~(ch->oslots >> (ch->lastslot + 1))); 1596 else 1597 tag = 0; 1598 if (tag == 0 || tag + ch->lastslot >= tags) 1599 tag = ffs(~ch->oslots) - 1; 1600 else 1601 tag += ch->lastslot; 1602 ch->lastslot = tag; 1603 /* Occupy chosen slot. */ 1604 slot = &ch->slot[tag]; 1605 slot->ccb = ccb; 1606 /* Stop PM timer. */ 1607 if (ch->numrslots == 0 && ch->pm_level > 3) 1608 callout_stop(&ch->pm_timer); 1609 /* Update channel stats. */ 1610 ch->oslots |= (1 << tag); 1611 ch->numrslots++; 1612 ch->numrslotspd[ccb->ccb_h.target_id]++; 1613 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1614 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1615 ch->numtslots++; 1616 ch->numtslotspd[ccb->ccb_h.target_id]++; 1617 ch->taggedtarget = ccb->ccb_h.target_id; 1618 } 1619 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1620 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 1621 ch->aslots |= (1 << tag); 1622 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1623 slot->state = AHCI_SLOT_LOADING; 1624 bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map, ccb, 1625 ahci_dmasetprd, slot, 0); 1626 } else { 1627 slot->dma.nsegs = 0; 1628 ahci_execute_transaction(slot); 1629 } 1630 } 1631 1632 /* Locked by busdma engine. */ 1633 static void 1634 ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1635 { 1636 struct ahci_slot *slot = arg; 1637 struct ahci_channel *ch = slot->ch; 1638 struct ahci_cmd_tab *ctp; 1639 struct ahci_dma_prd *prd; 1640 int i; 1641 1642 if (error) { 1643 device_printf(ch->dev, "DMA load error\n"); 1644 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1645 return; 1646 } 1647 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n")); 1648 /* Get a piece of the workspace for this request */ 1649 ctp = (struct ahci_cmd_tab *)(ch->dma.work + slot->ct_offset); 1650 /* Fill S/G table */ 1651 prd = &ctp->prd_tab[0]; 1652 for (i = 0; i < nsegs; i++) { 1653 prd[i].dba = htole64(segs[i].ds_addr); 1654 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK); 1655 } 1656 slot->dma.nsegs = nsegs; 1657 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1658 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1659 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1660 ahci_execute_transaction(slot); 1661 } 1662 1663 /* Must be called with channel locked. */ 1664 static void 1665 ahci_execute_transaction(struct ahci_slot *slot) 1666 { 1667 struct ahci_channel *ch = slot->ch; 1668 struct ahci_cmd_tab *ctp; 1669 struct ahci_cmd_list *clp; 1670 union ccb *ccb = slot->ccb; 1671 int port = ccb->ccb_h.target_id & 0x0f; 1672 int fis_size, i, softreset; 1673 uint8_t *fis = ch->dma.rfis + 0x40; 1674 uint8_t val; 1675 uint16_t cmd_flags; 1676 1677 /* Get a piece of the workspace for this request */ 1678 ctp = (struct ahci_cmd_tab *)(ch->dma.work + slot->ct_offset); 1679 /* Setup the FIS for this request */ 1680 if (!(fis_size = ahci_setup_fis(ch, ctp, ccb, slot->slot))) { 1681 device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1682 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1683 return; 1684 } 1685 /* Setup the command list entry */ 1686 clp = (struct ahci_cmd_list *) 1687 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1688 cmd_flags = 1689 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) | 1690 (ccb->ccb_h.func_code == XPT_SCSI_IO ? 1691 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) | 1692 (fis_size / sizeof(u_int32_t)) | 1693 (port << 12); 1694 clp->prd_length = htole16(slot->dma.nsegs); 1695 /* Special handling for Soft Reset command. */ 1696 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1697 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1698 if (ccb->ataio.cmd.control & ATA_A_RESET) { 1699 softreset = 1; 1700 /* Kick controller into sane state */ 1701 ahci_stop(ch); 1702 ahci_clo(ch); 1703 ahci_start(ch, 0); 1704 cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY; 1705 } else { 1706 softreset = 2; 1707 /* Prepare FIS receive area for check. */ 1708 for (i = 0; i < 20; i++) 1709 fis[i] = 0xff; 1710 } 1711 } else 1712 softreset = 0; 1713 clp->bytecount = 0; 1714 clp->cmd_flags = htole16(cmd_flags); 1715 clp->cmd_table_phys = htole64(ch->dma.work_bus + slot->ct_offset); 1716 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1717 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1718 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1719 BUS_DMASYNC_PREREAD); 1720 /* Set ACTIVE bit for NCQ commands. */ 1721 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1722 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1723 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot); 1724 } 1725 /* If FBS is enabled, set PMP port. */ 1726 if (ch->fbs_enabled) { 1727 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | 1728 (port << AHCI_P_FBS_DEV_SHIFT)); 1729 } 1730 /* Issue command to the controller. */ 1731 slot->state = AHCI_SLOT_RUNNING; 1732 ch->rslots |= (1 << slot->slot); 1733 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot)); 1734 /* Device reset commands doesn't interrupt. Poll them. */ 1735 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1736 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) { 1737 int count, timeout = ccb->ccb_h.timeout * 100; 1738 enum ahci_err_type et = AHCI_ERR_NONE; 1739 1740 for (count = 0; count < timeout; count++) { 1741 DELAY(10); 1742 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot))) 1743 break; 1744 if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) && 1745 softreset != 1) { 1746 #if 0 1747 device_printf(ch->dev, 1748 "Poll error on slot %d, TFD: %04x\n", 1749 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD)); 1750 #endif 1751 et = AHCI_ERR_TFE; 1752 break; 1753 } 1754 /* Workaround for ATI SB600/SB700 chipsets. */ 1755 if (ccb->ccb_h.target_id == 15 && 1756 (ch->quirks & AHCI_Q_ATI_PMP_BUG) && 1757 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) { 1758 et = AHCI_ERR_TIMEOUT; 1759 break; 1760 } 1761 } 1762 1763 /* 1764 * Some Marvell controllers require additional time 1765 * after soft reset to work properly. Setup delay 1766 * to 50ms after soft reset. 1767 */ 1768 if (ch->quirks & AHCI_Q_MRVL_SR_DEL) 1769 DELAY(50000); 1770 1771 /* 1772 * Marvell HBAs with non-RAID firmware do not wait for 1773 * readiness after soft reset, so we have to wait here. 1774 * Marvell RAIDs do not have this problem, but instead 1775 * sometimes forget to update FIS receive area, breaking 1776 * this wait. 1777 */ 1778 if ((ch->quirks & AHCI_Q_NOBSYRES) == 0 && 1779 (ch->quirks & AHCI_Q_ATI_PMP_BUG) == 0 && 1780 softreset == 2 && et == AHCI_ERR_NONE) { 1781 for ( ; count < timeout; count++) { 1782 bus_dmamap_sync(ch->dma.rfis_tag, 1783 ch->dma.rfis_map, BUS_DMASYNC_POSTREAD); 1784 val = fis[2]; 1785 bus_dmamap_sync(ch->dma.rfis_tag, 1786 ch->dma.rfis_map, BUS_DMASYNC_PREREAD); 1787 if ((val & ATA_S_BUSY) == 0) 1788 break; 1789 DELAY(10); 1790 } 1791 } 1792 1793 if (timeout && (count >= timeout)) { 1794 device_printf(ch->dev, "Poll timeout on slot %d port %d\n", 1795 slot->slot, port); 1796 device_printf(ch->dev, "is %08x cs %08x ss %08x " 1797 "rs %08x tfd %02x serr %08x cmd %08x\n", 1798 ATA_INL(ch->r_mem, AHCI_P_IS), 1799 ATA_INL(ch->r_mem, AHCI_P_CI), 1800 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1801 ATA_INL(ch->r_mem, AHCI_P_TFD), 1802 ATA_INL(ch->r_mem, AHCI_P_SERR), 1803 ATA_INL(ch->r_mem, AHCI_P_CMD)); 1804 et = AHCI_ERR_TIMEOUT; 1805 } 1806 1807 /* Kick controller into sane state and enable FBS. */ 1808 if (softreset == 2) 1809 ch->eslots |= (1 << slot->slot); 1810 ahci_end_transaction(slot, et); 1811 return; 1812 } 1813 /* Start command execution timeout */ 1814 callout_reset_sbt(&slot->timeout, SBT_1MS * ccb->ccb_h.timeout / 2, 1815 0, ahci_timeout, slot, 0); 1816 return; 1817 } 1818 1819 /* Must be called with channel locked. */ 1820 static void 1821 ahci_process_timeout(struct ahci_channel *ch) 1822 { 1823 int i; 1824 1825 mtx_assert(&ch->mtx, MA_OWNED); 1826 /* Handle the rest of commands. */ 1827 for (i = 0; i < ch->numslots; i++) { 1828 /* Do we have a running request on slot? */ 1829 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1830 continue; 1831 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT); 1832 } 1833 } 1834 1835 /* Must be called with channel locked. */ 1836 static void 1837 ahci_rearm_timeout(struct ahci_channel *ch) 1838 { 1839 int i; 1840 1841 mtx_assert(&ch->mtx, MA_OWNED); 1842 for (i = 0; i < ch->numslots; i++) { 1843 struct ahci_slot *slot = &ch->slot[i]; 1844 1845 /* Do we have a running request on slot? */ 1846 if (slot->state < AHCI_SLOT_RUNNING) 1847 continue; 1848 if ((ch->toslots & (1 << i)) == 0) 1849 continue; 1850 callout_reset_sbt(&slot->timeout, 1851 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0, 1852 ahci_timeout, slot, 0); 1853 } 1854 } 1855 1856 /* Locked by callout mechanism. */ 1857 static void 1858 ahci_timeout(void *arg) 1859 { 1860 struct ahci_slot *slot = arg; 1861 struct ahci_channel *ch = slot->ch; 1862 device_t dev = ch->dev; 1863 uint32_t sstatus; 1864 int ccs; 1865 int i; 1866 1867 /* Check for stale timeout. */ 1868 if (slot->state < AHCI_SLOT_RUNNING) 1869 return; 1870 1871 /* Check if slot was not being executed last time we checked. */ 1872 if (slot->state < AHCI_SLOT_EXECUTING) { 1873 /* Check if slot started executing. */ 1874 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1875 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1876 >> AHCI_P_CMD_CCS_SHIFT; 1877 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot || 1878 ch->fbs_enabled || ch->wrongccs) 1879 slot->state = AHCI_SLOT_EXECUTING; 1880 else if ((ch->rslots & (1 << ccs)) == 0) { 1881 ch->wrongccs = 1; 1882 slot->state = AHCI_SLOT_EXECUTING; 1883 } 1884 1885 callout_reset_sbt(&slot->timeout, 1886 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0, 1887 ahci_timeout, slot, 0); 1888 return; 1889 } 1890 1891 device_printf(dev, "Timeout on slot %d port %d\n", 1892 slot->slot, slot->ccb->ccb_h.target_id & 0x0f); 1893 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x " 1894 "serr %08x cmd %08x\n", 1895 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI), 1896 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1897 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR), 1898 ATA_INL(ch->r_mem, AHCI_P_CMD)); 1899 1900 /* Handle frozen command. */ 1901 if (ch->frozen) { 1902 union ccb *fccb = ch->frozen; 1903 ch->frozen = NULL; 1904 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1905 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1906 xpt_freeze_devq(fccb->ccb_h.path, 1); 1907 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1908 } 1909 ahci_done(ch, fccb); 1910 } 1911 if (!ch->fbs_enabled && !ch->wrongccs) { 1912 /* Without FBS we know real timeout source. */ 1913 ch->fatalerr = 1; 1914 /* Handle command with timeout. */ 1915 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT); 1916 /* Handle the rest of commands. */ 1917 for (i = 0; i < ch->numslots; i++) { 1918 /* Do we have a running request on slot? */ 1919 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1920 continue; 1921 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 1922 } 1923 } else { 1924 /* With FBS we wait for other commands timeout and pray. */ 1925 if (ch->toslots == 0) 1926 xpt_freeze_simq(ch->sim, 1); 1927 ch->toslots |= (1 << slot->slot); 1928 if ((ch->rslots & ~ch->toslots) == 0) 1929 ahci_process_timeout(ch); 1930 else 1931 device_printf(dev, " ... waiting for slots %08x\n", 1932 ch->rslots & ~ch->toslots); 1933 } 1934 } 1935 1936 /* Must be called with channel locked. */ 1937 static void 1938 ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et) 1939 { 1940 struct ahci_channel *ch = slot->ch; 1941 union ccb *ccb = slot->ccb; 1942 struct ahci_cmd_list *clp; 1943 int lastto; 1944 uint32_t sig; 1945 1946 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1947 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1948 clp = (struct ahci_cmd_list *) 1949 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1950 /* Read result registers to the result struct 1951 * May be incorrect if several commands finished same time, 1952 * so read only when sure or have to. 1953 */ 1954 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1955 struct ata_res *res = &ccb->ataio.res; 1956 1957 if ((et == AHCI_ERR_TFE) || 1958 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 1959 u_int8_t *fis = ch->dma.rfis + 0x40; 1960 1961 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1962 BUS_DMASYNC_POSTREAD); 1963 if (ch->fbs_enabled) { 1964 fis += ccb->ccb_h.target_id * 256; 1965 res->status = fis[2]; 1966 res->error = fis[3]; 1967 } else { 1968 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD); 1969 1970 res->status = tfd; 1971 res->error = tfd >> 8; 1972 } 1973 res->lba_low = fis[4]; 1974 res->lba_mid = fis[5]; 1975 res->lba_high = fis[6]; 1976 res->device = fis[7]; 1977 res->lba_low_exp = fis[8]; 1978 res->lba_mid_exp = fis[9]; 1979 res->lba_high_exp = fis[10]; 1980 res->sector_count = fis[12]; 1981 res->sector_count_exp = fis[13]; 1982 1983 /* 1984 * Some weird controllers do not return signature in 1985 * FIS receive area. Read it from PxSIG register. 1986 */ 1987 if ((ch->quirks & AHCI_Q_ALTSIG) && 1988 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1989 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) { 1990 sig = ATA_INL(ch->r_mem, AHCI_P_SIG); 1991 res->lba_high = sig >> 24; 1992 res->lba_mid = sig >> 16; 1993 res->lba_low = sig >> 8; 1994 res->sector_count = sig; 1995 } 1996 } else 1997 bzero(res, sizeof(*res)); 1998 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 && 1999 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2000 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 2001 ccb->ataio.resid = 2002 ccb->ataio.dxfer_len - le32toh(clp->bytecount); 2003 } 2004 } else { 2005 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2006 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 2007 ccb->csio.resid = 2008 ccb->csio.dxfer_len - le32toh(clp->bytecount); 2009 } 2010 } 2011 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2012 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 2013 (ccb->ccb_h.flags & CAM_DIR_IN) ? 2014 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2015 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 2016 } 2017 if (et != AHCI_ERR_NONE) 2018 ch->eslots |= (1 << slot->slot); 2019 /* In case of error, freeze device for proper recovery. */ 2020 if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) && 2021 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 2022 xpt_freeze_devq(ccb->ccb_h.path, 1); 2023 ccb->ccb_h.status |= CAM_DEV_QFRZN; 2024 } 2025 /* Set proper result status. */ 2026 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2027 switch (et) { 2028 case AHCI_ERR_NONE: 2029 ccb->ccb_h.status |= CAM_REQ_CMP; 2030 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 2031 ccb->csio.scsi_status = SCSI_STATUS_OK; 2032 break; 2033 case AHCI_ERR_INVALID: 2034 ch->fatalerr = 1; 2035 ccb->ccb_h.status |= CAM_REQ_INVALID; 2036 break; 2037 case AHCI_ERR_INNOCENT: 2038 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 2039 break; 2040 case AHCI_ERR_TFE: 2041 case AHCI_ERR_NCQ: 2042 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2043 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 2044 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 2045 } else { 2046 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 2047 } 2048 break; 2049 case AHCI_ERR_SATA: 2050 ch->fatalerr = 1; 2051 if (!ch->recoverycmd) { 2052 xpt_freeze_simq(ch->sim, 1); 2053 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2054 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2055 } 2056 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 2057 break; 2058 case AHCI_ERR_TIMEOUT: 2059 if (!ch->recoverycmd) { 2060 xpt_freeze_simq(ch->sim, 1); 2061 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2062 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2063 } 2064 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 2065 break; 2066 default: 2067 ch->fatalerr = 1; 2068 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 2069 } 2070 /* Free slot. */ 2071 ch->oslots &= ~(1 << slot->slot); 2072 ch->rslots &= ~(1 << slot->slot); 2073 ch->aslots &= ~(1 << slot->slot); 2074 slot->state = AHCI_SLOT_EMPTY; 2075 slot->ccb = NULL; 2076 /* Update channel stats. */ 2077 ch->numrslots--; 2078 ch->numrslotspd[ccb->ccb_h.target_id]--; 2079 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2080 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 2081 ch->numtslots--; 2082 ch->numtslotspd[ccb->ccb_h.target_id]--; 2083 } 2084 /* Cancel timeout state if request completed normally. */ 2085 if (et != AHCI_ERR_TIMEOUT) { 2086 lastto = (ch->toslots == (1 << slot->slot)); 2087 ch->toslots &= ~(1 << slot->slot); 2088 if (lastto) 2089 xpt_release_simq(ch->sim, TRUE); 2090 } 2091 /* If it was first request of reset sequence and there is no error, 2092 * proceed to second request. */ 2093 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 2094 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 2095 (ccb->ataio.cmd.control & ATA_A_RESET) && 2096 et == AHCI_ERR_NONE) { 2097 ccb->ataio.cmd.control &= ~ATA_A_RESET; 2098 ahci_begin_transaction(ch, ccb); 2099 return; 2100 } 2101 /* If it was our READ LOG command - process it. */ 2102 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) { 2103 ahci_process_read_log(ch, ccb); 2104 /* If it was our REQUEST SENSE command - process it. */ 2105 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) { 2106 ahci_process_request_sense(ch, ccb); 2107 /* If it was NCQ or ATAPI command error, put result on hold. */ 2108 } else if (et == AHCI_ERR_NCQ || 2109 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR && 2110 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) { 2111 ch->hold[slot->slot] = ccb; 2112 ch->numhslots++; 2113 } else 2114 ahci_done(ch, ccb); 2115 /* If we have no other active commands, ... */ 2116 if (ch->rslots == 0) { 2117 /* if there was fatal error - reset port. */ 2118 if (ch->toslots != 0 || ch->fatalerr) { 2119 ahci_reset(ch); 2120 } else { 2121 /* if we have slots in error, we can reinit port. */ 2122 if (ch->eslots != 0) { 2123 ahci_stop(ch); 2124 ahci_clo(ch); 2125 ahci_start(ch, 1); 2126 } 2127 /* if there commands on hold, we can do READ LOG. */ 2128 if (!ch->recoverycmd && ch->numhslots) 2129 ahci_issue_recovery(ch); 2130 } 2131 /* If all the rest of commands are in timeout - give them chance. */ 2132 } else if ((ch->rslots & ~ch->toslots) == 0 && 2133 et != AHCI_ERR_TIMEOUT) 2134 ahci_rearm_timeout(ch); 2135 /* Unfreeze frozen command. */ 2136 if (ch->frozen && !ahci_check_collision(ch, ch->frozen)) { 2137 union ccb *fccb = ch->frozen; 2138 ch->frozen = NULL; 2139 ahci_begin_transaction(ch, fccb); 2140 xpt_release_simq(ch->sim, TRUE); 2141 } 2142 /* Start PM timer. */ 2143 if (ch->numrslots == 0 && ch->pm_level > 3 && 2144 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) { 2145 callout_schedule(&ch->pm_timer, 2146 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 2147 } 2148 } 2149 2150 static void 2151 ahci_issue_recovery(struct ahci_channel *ch) 2152 { 2153 union ccb *ccb; 2154 struct ccb_ataio *ataio; 2155 struct ccb_scsiio *csio; 2156 int i; 2157 2158 /* Find some held command. */ 2159 for (i = 0; i < ch->numslots; i++) { 2160 if (ch->hold[i]) 2161 break; 2162 } 2163 ccb = xpt_alloc_ccb_nowait(); 2164 if (ccb == NULL) { 2165 device_printf(ch->dev, "Unable to allocate recovery command\n"); 2166 completeall: 2167 /* We can't do anything -- complete held commands. */ 2168 for (i = 0; i < ch->numslots; i++) { 2169 if (ch->hold[i] == NULL) 2170 continue; 2171 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2172 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL; 2173 ahci_done(ch, ch->hold[i]); 2174 ch->hold[i] = NULL; 2175 ch->numhslots--; 2176 } 2177 ahci_reset(ch); 2178 return; 2179 } 2180 xpt_setup_ccb(&ccb->ccb_h, ch->hold[i]->ccb_h.path, 2181 ch->hold[i]->ccb_h.pinfo.priority); 2182 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 2183 /* READ LOG */ 2184 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG; 2185 ccb->ccb_h.func_code = XPT_ATA_IO; 2186 ccb->ccb_h.flags = CAM_DIR_IN; 2187 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2188 ataio = &ccb->ataio; 2189 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT); 2190 if (ataio->data_ptr == NULL) { 2191 xpt_free_ccb(ccb); 2192 device_printf(ch->dev, 2193 "Unable to allocate memory for READ LOG command\n"); 2194 goto completeall; 2195 } 2196 ataio->dxfer_len = 512; 2197 bzero(&ataio->cmd, sizeof(ataio->cmd)); 2198 ataio->cmd.flags = CAM_ATAIO_48BIT; 2199 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 2200 ataio->cmd.sector_count = 1; 2201 ataio->cmd.sector_count_exp = 0; 2202 ataio->cmd.lba_low = 0x10; 2203 ataio->cmd.lba_mid = 0; 2204 ataio->cmd.lba_mid_exp = 0; 2205 } else { 2206 /* REQUEST SENSE */ 2207 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE; 2208 ccb->ccb_h.recovery_slot = i; 2209 ccb->ccb_h.func_code = XPT_SCSI_IO; 2210 ccb->ccb_h.flags = CAM_DIR_IN; 2211 ccb->ccb_h.status = 0; 2212 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 2213 csio = &ccb->csio; 2214 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data; 2215 csio->dxfer_len = ch->hold[i]->csio.sense_len; 2216 csio->cdb_len = 6; 2217 bzero(&csio->cdb_io, sizeof(csio->cdb_io)); 2218 csio->cdb_io.cdb_bytes[0] = 0x03; 2219 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len; 2220 } 2221 /* Freeze SIM while doing recovery. */ 2222 ch->recoverycmd = 1; 2223 xpt_freeze_simq(ch->sim, 1); 2224 ahci_begin_transaction(ch, ccb); 2225 } 2226 2227 static void 2228 ahci_process_read_log(struct ahci_channel *ch, union ccb *ccb) 2229 { 2230 uint8_t *data; 2231 struct ata_res *res; 2232 int i; 2233 2234 ch->recoverycmd = 0; 2235 2236 data = ccb->ataio.data_ptr; 2237 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 2238 (data[0] & 0x80) == 0) { 2239 for (i = 0; i < ch->numslots; i++) { 2240 if (!ch->hold[i]) 2241 continue; 2242 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2243 continue; 2244 if ((data[0] & 0x1F) == i) { 2245 res = &ch->hold[i]->ataio.res; 2246 res->status = data[2]; 2247 res->error = data[3]; 2248 res->lba_low = data[4]; 2249 res->lba_mid = data[5]; 2250 res->lba_high = data[6]; 2251 res->device = data[7]; 2252 res->lba_low_exp = data[8]; 2253 res->lba_mid_exp = data[9]; 2254 res->lba_high_exp = data[10]; 2255 res->sector_count = data[12]; 2256 res->sector_count_exp = data[13]; 2257 } else { 2258 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2259 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 2260 } 2261 ahci_done(ch, ch->hold[i]); 2262 ch->hold[i] = NULL; 2263 ch->numhslots--; 2264 } 2265 } else { 2266 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 2267 device_printf(ch->dev, "Error while READ LOG EXT\n"); 2268 else if ((data[0] & 0x80) == 0) { 2269 device_printf(ch->dev, "Non-queued command error in READ LOG EXT\n"); 2270 } 2271 for (i = 0; i < ch->numslots; i++) { 2272 if (!ch->hold[i]) 2273 continue; 2274 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2275 continue; 2276 ahci_done(ch, ch->hold[i]); 2277 ch->hold[i] = NULL; 2278 ch->numhslots--; 2279 } 2280 } 2281 free(ccb->ataio.data_ptr, M_AHCI); 2282 xpt_free_ccb(ccb); 2283 xpt_release_simq(ch->sim, TRUE); 2284 } 2285 2286 static void 2287 ahci_process_request_sense(struct ahci_channel *ch, union ccb *ccb) 2288 { 2289 int i; 2290 2291 ch->recoverycmd = 0; 2292 2293 i = ccb->ccb_h.recovery_slot; 2294 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) { 2295 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID; 2296 } else { 2297 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2298 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL; 2299 } 2300 ahci_done(ch, ch->hold[i]); 2301 ch->hold[i] = NULL; 2302 ch->numhslots--; 2303 xpt_free_ccb(ccb); 2304 xpt_release_simq(ch->sim, TRUE); 2305 } 2306 2307 static void 2308 ahci_start(struct ahci_channel *ch, int fbs) 2309 { 2310 u_int32_t cmd; 2311 2312 /* Run the channel start callback, if any. */ 2313 if (ch->start) 2314 ch->start(ch); 2315 2316 /* Clear SATA error register */ 2317 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF); 2318 /* Clear any interrupts pending on this channel */ 2319 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF); 2320 /* Configure FIS-based switching if supported. */ 2321 if (ch->chcaps & AHCI_P_CMD_FBSCP) { 2322 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0; 2323 ATA_OUTL(ch->r_mem, AHCI_P_FBS, 2324 ch->fbs_enabled ? AHCI_P_FBS_EN : 0); 2325 } 2326 /* Start operations on this channel */ 2327 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2328 cmd &= ~AHCI_P_CMD_PMA; 2329 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST | 2330 (ch->pm_present ? AHCI_P_CMD_PMA : 0)); 2331 } 2332 2333 static void 2334 ahci_stop(struct ahci_channel *ch) 2335 { 2336 u_int32_t cmd; 2337 int timeout; 2338 2339 /* Kill all activity on this channel */ 2340 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2341 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST); 2342 /* Wait for activity stop. */ 2343 timeout = 0; 2344 do { 2345 DELAY(10); 2346 if (timeout++ > 50000) { 2347 device_printf(ch->dev, "stopping AHCI engine failed\n"); 2348 break; 2349 } 2350 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR); 2351 ch->eslots = 0; 2352 } 2353 2354 static void 2355 ahci_clo(struct ahci_channel *ch) 2356 { 2357 u_int32_t cmd; 2358 int timeout; 2359 2360 /* Issue Command List Override if supported */ 2361 if (ch->caps & AHCI_CAP_SCLO) { 2362 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2363 cmd |= AHCI_P_CMD_CLO; 2364 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd); 2365 timeout = 0; 2366 do { 2367 DELAY(10); 2368 if (timeout++ > 50000) { 2369 device_printf(ch->dev, "executing CLO failed\n"); 2370 break; 2371 } 2372 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO); 2373 } 2374 } 2375 2376 static void 2377 ahci_stop_fr(struct ahci_channel *ch) 2378 { 2379 u_int32_t cmd; 2380 int timeout; 2381 2382 /* Kill all FIS reception on this channel */ 2383 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2384 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE); 2385 /* Wait for FIS reception stop. */ 2386 timeout = 0; 2387 do { 2388 DELAY(10); 2389 if (timeout++ > 50000) { 2390 device_printf(ch->dev, "stopping AHCI FR engine failed\n"); 2391 break; 2392 } 2393 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR); 2394 } 2395 2396 static void 2397 ahci_start_fr(struct ahci_channel *ch) 2398 { 2399 u_int32_t cmd; 2400 2401 /* Start FIS reception on this channel */ 2402 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2403 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE); 2404 } 2405 2406 static int 2407 ahci_wait_ready(struct ahci_channel *ch, int t, int t0) 2408 { 2409 int timeout = 0; 2410 uint32_t val; 2411 2412 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) & 2413 (ATA_S_BUSY | ATA_S_DRQ)) { 2414 if (timeout > t) { 2415 if (t != 0) { 2416 device_printf(ch->dev, 2417 "AHCI reset: device not ready after %dms " 2418 "(tfd = %08x)\n", 2419 MAX(t, 0) + t0, val); 2420 } 2421 return (EBUSY); 2422 } 2423 DELAY(1000); 2424 timeout++; 2425 } 2426 if (bootverbose) 2427 device_printf(ch->dev, "AHCI reset: device ready after %dms\n", 2428 timeout + t0); 2429 return (0); 2430 } 2431 2432 static void 2433 ahci_reset_to(void *arg) 2434 { 2435 struct ahci_channel *ch = arg; 2436 2437 if (ch->resetting == 0) 2438 return; 2439 ch->resetting--; 2440 if (ahci_wait_ready(ch, ch->resetting == 0 ? -1 : 0, 2441 (310 - ch->resetting) * 100) == 0) { 2442 ch->resetting = 0; 2443 ahci_start(ch, 1); 2444 xpt_release_simq(ch->sim, TRUE); 2445 return; 2446 } 2447 if (ch->resetting == 0) { 2448 ahci_clo(ch); 2449 ahci_start(ch, 1); 2450 xpt_release_simq(ch->sim, TRUE); 2451 return; 2452 } 2453 callout_schedule(&ch->reset_timer, hz / 10); 2454 } 2455 2456 static void 2457 ahci_reset(struct ahci_channel *ch) 2458 { 2459 struct ahci_controller *ctlr = device_get_softc(device_get_parent(ch->dev)); 2460 int i; 2461 2462 xpt_freeze_simq(ch->sim, 1); 2463 if (bootverbose) 2464 device_printf(ch->dev, "AHCI reset...\n"); 2465 /* Forget about previous reset. */ 2466 if (ch->resetting) { 2467 ch->resetting = 0; 2468 callout_stop(&ch->reset_timer); 2469 xpt_release_simq(ch->sim, TRUE); 2470 } 2471 /* Requeue freezed command. */ 2472 if (ch->frozen) { 2473 union ccb *fccb = ch->frozen; 2474 ch->frozen = NULL; 2475 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2476 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2477 xpt_freeze_devq(fccb->ccb_h.path, 1); 2478 fccb->ccb_h.status |= CAM_DEV_QFRZN; 2479 } 2480 ahci_done(ch, fccb); 2481 } 2482 /* Kill the engine and requeue all running commands. */ 2483 ahci_stop(ch); 2484 for (i = 0; i < ch->numslots; i++) { 2485 /* Do we have a running request on slot? */ 2486 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2487 continue; 2488 /* XXX; Commands in loading state. */ 2489 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2490 } 2491 for (i = 0; i < ch->numslots; i++) { 2492 if (!ch->hold[i]) 2493 continue; 2494 ahci_done(ch, ch->hold[i]); 2495 ch->hold[i] = NULL; 2496 ch->numhslots--; 2497 } 2498 if (ch->toslots != 0) 2499 xpt_release_simq(ch->sim, TRUE); 2500 ch->eslots = 0; 2501 ch->toslots = 0; 2502 ch->wrongccs = 0; 2503 ch->fatalerr = 0; 2504 /* Tell the XPT about the event */ 2505 xpt_async(AC_BUS_RESET, ch->path, NULL); 2506 /* Disable port interrupts */ 2507 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 2508 /* Reset and reconnect PHY, */ 2509 if (!ahci_sata_phy_reset(ch)) { 2510 if (bootverbose) 2511 device_printf(ch->dev, 2512 "AHCI reset: device not found\n"); 2513 ch->devices = 0; 2514 /* Enable wanted port interrupts */ 2515 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2516 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2517 AHCI_P_IX_PRC | AHCI_P_IX_PC)); 2518 xpt_release_simq(ch->sim, TRUE); 2519 return; 2520 } 2521 if (bootverbose) 2522 device_printf(ch->dev, "AHCI reset: device found\n"); 2523 /* Wait for clearing busy status. */ 2524 if (ahci_wait_ready(ch, dumping ? 31000 : 0, 0)) { 2525 if (dumping) 2526 ahci_clo(ch); 2527 else 2528 ch->resetting = 310; 2529 } 2530 ch->devices = 1; 2531 /* Enable wanted port interrupts */ 2532 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2533 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2534 AHCI_P_IX_TFE | AHCI_P_IX_HBF | 2535 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF | 2536 ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC | 2537 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) | 2538 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR))); 2539 if (ch->resetting) 2540 callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, ch); 2541 else { 2542 ahci_start(ch, 1); 2543 xpt_release_simq(ch->sim, TRUE); 2544 } 2545 } 2546 2547 static int 2548 ahci_setup_fis(struct ahci_channel *ch, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag) 2549 { 2550 u_int8_t *fis = &ctp->cfis[0]; 2551 2552 bzero(fis, 20); 2553 fis[0] = 0x27; /* host to device */ 2554 fis[1] = (ccb->ccb_h.target_id & 0x0f); 2555 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2556 fis[1] |= 0x80; 2557 fis[2] = ATA_PACKET_CMD; 2558 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2559 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 2560 fis[3] = ATA_F_DMA; 2561 else { 2562 fis[5] = ccb->csio.dxfer_len; 2563 fis[6] = ccb->csio.dxfer_len >> 8; 2564 } 2565 fis[7] = ATA_D_LBA; 2566 fis[15] = ATA_A_4BIT; 2567 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 2568 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 2569 ctp->acmd, ccb->csio.cdb_len); 2570 bzero(ctp->acmd + ccb->csio.cdb_len, 32 - ccb->csio.cdb_len); 2571 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 2572 fis[1] |= 0x80; 2573 fis[2] = ccb->ataio.cmd.command; 2574 fis[3] = ccb->ataio.cmd.features; 2575 fis[4] = ccb->ataio.cmd.lba_low; 2576 fis[5] = ccb->ataio.cmd.lba_mid; 2577 fis[6] = ccb->ataio.cmd.lba_high; 2578 fis[7] = ccb->ataio.cmd.device; 2579 fis[8] = ccb->ataio.cmd.lba_low_exp; 2580 fis[9] = ccb->ataio.cmd.lba_mid_exp; 2581 fis[10] = ccb->ataio.cmd.lba_high_exp; 2582 fis[11] = ccb->ataio.cmd.features_exp; 2583 fis[12] = ccb->ataio.cmd.sector_count; 2584 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 2585 fis[12] &= 0x07; 2586 fis[12] |= tag << 3; 2587 } 2588 fis[13] = ccb->ataio.cmd.sector_count_exp; 2589 if (ccb->ataio.ata_flags & ATA_FLAG_ICC) 2590 fis[14] = ccb->ataio.icc; 2591 fis[15] = ATA_A_4BIT; 2592 if (ccb->ataio.ata_flags & ATA_FLAG_AUX) { 2593 fis[16] = ccb->ataio.aux & 0xff; 2594 fis[17] = (ccb->ataio.aux >> 8) & 0xff; 2595 fis[18] = (ccb->ataio.aux >> 16) & 0xff; 2596 fis[19] = (ccb->ataio.aux >> 24) & 0xff; 2597 } 2598 } else { 2599 fis[15] = ccb->ataio.cmd.control; 2600 } 2601 return (20); 2602 } 2603 2604 static int 2605 ahci_sata_connect(struct ahci_channel *ch) 2606 { 2607 u_int32_t status; 2608 int timeout, found = 0; 2609 2610 /* Wait up to 100ms for "connect well" */ 2611 for (timeout = 0; timeout < 1000 ; timeout++) { 2612 status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 2613 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 2614 found = 1; 2615 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 2616 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 2617 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 2618 break; 2619 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) { 2620 if (bootverbose) { 2621 device_printf(ch->dev, "SATA offline status=%08x\n", 2622 status); 2623 } 2624 return (0); 2625 } 2626 if (found == 0 && timeout >= 100) 2627 break; 2628 DELAY(100); 2629 } 2630 if (timeout >= 1000 || !found) { 2631 if (bootverbose) { 2632 device_printf(ch->dev, 2633 "SATA connect timeout time=%dus status=%08x\n", 2634 timeout * 100, status); 2635 } 2636 return (0); 2637 } 2638 if (bootverbose) { 2639 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n", 2640 timeout * 100, status); 2641 } 2642 /* Clear SATA error register */ 2643 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff); 2644 return (1); 2645 } 2646 2647 static int 2648 ahci_sata_phy_reset(struct ahci_channel *ch) 2649 { 2650 int sata_rev; 2651 uint32_t val, detval; 2652 2653 if (ch->listening) { 2654 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2655 val |= AHCI_P_CMD_SUD; 2656 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2657 ch->listening = 0; 2658 } 2659 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 2660 if (sata_rev == 1) 2661 val = ATA_SC_SPD_SPEED_GEN1; 2662 else if (sata_rev == 2) 2663 val = ATA_SC_SPD_SPEED_GEN2; 2664 else if (sata_rev == 3) 2665 val = ATA_SC_SPD_SPEED_GEN3; 2666 else 2667 val = 0; 2668 detval = ahci_ch_detval(ch, ATA_SC_DET_RESET); 2669 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2670 detval | val | 2671 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER); 2672 DELAY(1000); 2673 detval = ahci_ch_detval(ch, ATA_SC_DET_IDLE); 2674 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2675 detval | val | ((ch->pm_level > 0) ? 0 : 2676 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); 2677 if (!ahci_sata_connect(ch)) { 2678 if (ch->caps & AHCI_CAP_SSS) { 2679 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2680 val &= ~AHCI_P_CMD_SUD; 2681 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2682 ch->listening = 1; 2683 } else if (ch->pm_level > 0) 2684 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 2685 return (0); 2686 } 2687 return (1); 2688 } 2689 2690 static int 2691 ahci_check_ids(struct ahci_channel *ch, union ccb *ccb) 2692 { 2693 2694 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) { 2695 ccb->ccb_h.status = CAM_TID_INVALID; 2696 ahci_done(ch, ccb); 2697 return (-1); 2698 } 2699 if (ccb->ccb_h.target_lun != 0) { 2700 ccb->ccb_h.status = CAM_LUN_INVALID; 2701 ahci_done(ch, ccb); 2702 return (-1); 2703 } 2704 return (0); 2705 } 2706 2707 static void 2708 ahciaction(struct cam_sim *sim, union ccb *ccb) 2709 { 2710 struct ahci_channel *ch; 2711 2712 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n", 2713 ccb->ccb_h.func_code)); 2714 2715 ch = (struct ahci_channel *)cam_sim_softc(sim); 2716 switch (ccb->ccb_h.func_code) { 2717 /* Common cases first */ 2718 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2719 case XPT_SCSI_IO: 2720 if (ahci_check_ids(ch, ccb)) 2721 return; 2722 if (ch->devices == 0 || 2723 (ch->pm_present == 0 && 2724 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) { 2725 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2726 break; 2727 } 2728 ccb->ccb_h.recovery_type = RECOVERY_NONE; 2729 /* Check for command collision. */ 2730 if (ahci_check_collision(ch, ccb)) { 2731 /* Freeze command. */ 2732 ch->frozen = ccb; 2733 /* We have only one frozen slot, so freeze simq also. */ 2734 xpt_freeze_simq(ch->sim, 1); 2735 return; 2736 } 2737 ahci_begin_transaction(ch, ccb); 2738 return; 2739 case XPT_ABORT: /* Abort the specified CCB */ 2740 /* XXX Implement */ 2741 ccb->ccb_h.status = CAM_REQ_INVALID; 2742 break; 2743 case XPT_SET_TRAN_SETTINGS: 2744 { 2745 struct ccb_trans_settings *cts = &ccb->cts; 2746 struct ahci_device *d; 2747 2748 if (ahci_check_ids(ch, ccb)) 2749 return; 2750 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2751 d = &ch->curr[ccb->ccb_h.target_id]; 2752 else 2753 d = &ch->user[ccb->ccb_h.target_id]; 2754 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2755 d->revision = cts->xport_specific.sata.revision; 2756 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2757 d->mode = cts->xport_specific.sata.mode; 2758 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 2759 d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 2760 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2761 d->tags = min(ch->numslots, cts->xport_specific.sata.tags); 2762 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2763 ch->pm_present = cts->xport_specific.sata.pm_present; 2764 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 2765 d->atapi = cts->xport_specific.sata.atapi; 2766 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 2767 d->caps = cts->xport_specific.sata.caps; 2768 ccb->ccb_h.status = CAM_REQ_CMP; 2769 break; 2770 } 2771 case XPT_GET_TRAN_SETTINGS: 2772 /* Get default/user set transfer settings for the target */ 2773 { 2774 struct ccb_trans_settings *cts = &ccb->cts; 2775 struct ahci_device *d; 2776 uint32_t status; 2777 2778 if (ahci_check_ids(ch, ccb)) 2779 return; 2780 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2781 d = &ch->curr[ccb->ccb_h.target_id]; 2782 else 2783 d = &ch->user[ccb->ccb_h.target_id]; 2784 cts->protocol = PROTO_UNSPECIFIED; 2785 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2786 cts->transport = XPORT_SATA; 2787 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2788 cts->proto_specific.valid = 0; 2789 cts->xport_specific.sata.valid = 0; 2790 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 2791 (ccb->ccb_h.target_id == 15 || 2792 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 2793 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK; 2794 if (status & 0x0f0) { 2795 cts->xport_specific.sata.revision = 2796 (status & 0x0f0) >> 4; 2797 cts->xport_specific.sata.valid |= 2798 CTS_SATA_VALID_REVISION; 2799 } 2800 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D; 2801 if (ch->pm_level) { 2802 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC)) 2803 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ; 2804 if (ch->caps2 & AHCI_CAP2_APST) 2805 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST; 2806 } 2807 if ((ch->caps & AHCI_CAP_SNCQ) && 2808 (ch->quirks & AHCI_Q_NOAA) == 0) 2809 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA; 2810 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN; 2811 cts->xport_specific.sata.caps &= 2812 ch->user[ccb->ccb_h.target_id].caps; 2813 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2814 } else { 2815 cts->xport_specific.sata.revision = d->revision; 2816 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 2817 cts->xport_specific.sata.caps = d->caps; 2818 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2819 } 2820 cts->xport_specific.sata.mode = d->mode; 2821 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 2822 cts->xport_specific.sata.bytecount = d->bytecount; 2823 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 2824 cts->xport_specific.sata.pm_present = ch->pm_present; 2825 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 2826 cts->xport_specific.sata.tags = d->tags; 2827 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 2828 cts->xport_specific.sata.atapi = d->atapi; 2829 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 2830 ccb->ccb_h.status = CAM_REQ_CMP; 2831 break; 2832 } 2833 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 2834 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2835 ahci_reset(ch); 2836 ccb->ccb_h.status = CAM_REQ_CMP; 2837 break; 2838 case XPT_TERM_IO: /* Terminate the I/O process */ 2839 /* XXX Implement */ 2840 ccb->ccb_h.status = CAM_REQ_INVALID; 2841 break; 2842 case XPT_PATH_INQ: /* Path routing inquiry */ 2843 { 2844 struct ccb_pathinq *cpi = &ccb->cpi; 2845 2846 cpi->version_num = 1; /* XXX??? */ 2847 cpi->hba_inquiry = PI_SDTR_ABLE; 2848 if (ch->caps & AHCI_CAP_SNCQ) 2849 cpi->hba_inquiry |= PI_TAG_ABLE; 2850 if (ch->caps & AHCI_CAP_SPM) 2851 cpi->hba_inquiry |= PI_SATAPM; 2852 cpi->target_sprt = 0; 2853 cpi->hba_misc = PIM_SEQSCAN | PIM_UNMAPPED; 2854 if ((ch->quirks & AHCI_Q_NOAUX) == 0) 2855 cpi->hba_misc |= PIM_ATA_EXT; 2856 cpi->hba_eng_cnt = 0; 2857 if (ch->caps & AHCI_CAP_SPM) 2858 cpi->max_target = 15; 2859 else 2860 cpi->max_target = 0; 2861 cpi->max_lun = 0; 2862 cpi->initiator_id = 0; 2863 cpi->bus_id = cam_sim_bus(sim); 2864 cpi->base_transfer_speed = 150000; 2865 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2866 strlcpy(cpi->hba_vid, "AHCI", HBA_IDLEN); 2867 strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2868 cpi->unit_number = cam_sim_unit(sim); 2869 cpi->transport = XPORT_SATA; 2870 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 2871 cpi->protocol = PROTO_ATA; 2872 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 2873 cpi->maxio = ctob(AHCI_SG_ENTRIES - 1); 2874 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */ 2875 if (ch->quirks & AHCI_Q_MAXIO_64K) 2876 cpi->maxio = min(cpi->maxio, 128 * 512); 2877 cpi->hba_vendor = ch->vendorid; 2878 cpi->hba_device = ch->deviceid; 2879 cpi->hba_subvendor = ch->subvendorid; 2880 cpi->hba_subdevice = ch->subdeviceid; 2881 cpi->ccb_h.status = CAM_REQ_CMP; 2882 break; 2883 } 2884 default: 2885 ccb->ccb_h.status = CAM_REQ_INVALID; 2886 break; 2887 } 2888 ahci_done(ch, ccb); 2889 } 2890 2891 static void 2892 ahcipoll(struct cam_sim *sim) 2893 { 2894 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim); 2895 uint32_t istatus; 2896 2897 /* Read interrupt statuses and process if any. */ 2898 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 2899 if (istatus != 0) 2900 ahci_ch_intr_main(ch, istatus); 2901 if (ch->resetting != 0 && 2902 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) { 2903 ch->resetpolldiv = 1000; 2904 ahci_reset_to(ch); 2905 } 2906 } 2907 2908 MODULE_VERSION(ahci, 1); 2909 MODULE_DEPEND(ahci, cam, 1, 1, 1);
Cache object: 32fdb342f790db102c90e55b98f69835
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