Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/ahci/ahci.c
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1 /*- 2 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/module.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/bus.h> 35 #include <sys/conf.h> 36 #include <sys/endian.h> 37 #include <sys/malloc.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <machine/stdarg.h> 41 #include <machine/resource.h> 42 #include <machine/bus.h> 43 #include <sys/rman.h> 44 #include "ahci.h" 45 46 #include <cam/cam.h> 47 #include <cam/cam_ccb.h> 48 #include <cam/cam_sim.h> 49 #include <cam/cam_xpt_sim.h> 50 #include <cam/cam_debug.h> 51 52 /* local prototypes */ 53 static void ahci_intr(void *data); 54 static void ahci_intr_one(void *data); 55 static void ahci_intr_one_edge(void *data); 56 static int ahci_ch_init(device_t dev); 57 static int ahci_ch_deinit(device_t dev); 58 static int ahci_ch_suspend(device_t dev); 59 static int ahci_ch_resume(device_t dev); 60 static void ahci_ch_pm(void *arg); 61 static void ahci_ch_intr(void *arg); 62 static void ahci_ch_intr_direct(void *arg); 63 static void ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus); 64 static void ahci_begin_transaction(struct ahci_channel *ch, union ccb *ccb); 65 static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 66 static void ahci_execute_transaction(struct ahci_slot *slot); 67 static void ahci_timeout(struct ahci_slot *slot); 68 static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et); 69 static int ahci_setup_fis(struct ahci_channel *ch, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag); 70 static void ahci_dmainit(device_t dev); 71 static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 72 static void ahci_dmafini(device_t dev); 73 static void ahci_slotsalloc(device_t dev); 74 static void ahci_slotsfree(device_t dev); 75 static void ahci_reset(struct ahci_channel *ch); 76 static void ahci_start(struct ahci_channel *ch, int fbs); 77 static void ahci_stop(struct ahci_channel *ch); 78 static void ahci_clo(struct ahci_channel *ch); 79 static void ahci_start_fr(struct ahci_channel *ch); 80 static void ahci_stop_fr(struct ahci_channel *ch); 81 82 static int ahci_sata_connect(struct ahci_channel *ch); 83 static int ahci_sata_phy_reset(struct ahci_channel *ch); 84 static int ahci_wait_ready(struct ahci_channel *ch, int t, int t0); 85 86 static void ahci_issue_recovery(struct ahci_channel *ch); 87 static void ahci_process_read_log(struct ahci_channel *ch, union ccb *ccb); 88 static void ahci_process_request_sense(struct ahci_channel *ch, union ccb *ccb); 89 90 static void ahciaction(struct cam_sim *sim, union ccb *ccb); 91 static void ahcipoll(struct cam_sim *sim); 92 93 static MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers"); 94 95 #define recovery_type spriv_field0 96 #define RECOVERY_NONE 0 97 #define RECOVERY_READ_LOG 1 98 #define RECOVERY_REQUEST_SENSE 2 99 #define recovery_slot spriv_field1 100 101 int 102 ahci_ctlr_setup(device_t dev) 103 { 104 struct ahci_controller *ctlr = device_get_softc(dev); 105 /* Clear interrupts */ 106 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS)); 107 /* Configure CCC */ 108 if (ctlr->ccc) { 109 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI)); 110 ATA_OUTL(ctlr->r_mem, AHCI_CCCC, 111 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) | 112 (4 << AHCI_CCCC_CC_SHIFT) | 113 AHCI_CCCC_EN); 114 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) & 115 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT; 116 if (bootverbose) { 117 device_printf(dev, 118 "CCC with %dms/4cmd enabled on vector %d\n", 119 ctlr->ccc, ctlr->cccv); 120 } 121 } 122 /* Enable AHCI interrupts */ 123 ATA_OUTL(ctlr->r_mem, AHCI_GHC, 124 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE); 125 return (0); 126 } 127 128 int 129 ahci_ctlr_reset(device_t dev) 130 { 131 struct ahci_controller *ctlr = device_get_softc(dev); 132 int timeout; 133 134 /* Enable AHCI mode */ 135 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 136 /* Reset AHCI controller */ 137 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR); 138 for (timeout = 1000; timeout > 0; timeout--) { 139 DELAY(1000); 140 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0) 141 break; 142 } 143 if (timeout == 0) { 144 device_printf(dev, "AHCI controller reset failure\n"); 145 return (ENXIO); 146 } 147 /* Reenable AHCI mode */ 148 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE); 149 return (0); 150 } 151 152 153 int 154 ahci_attach(device_t dev) 155 { 156 struct ahci_controller *ctlr = device_get_softc(dev); 157 int error, i, speed, unit; 158 uint32_t u, version; 159 device_t child; 160 161 ctlr->dev = dev; 162 ctlr->ccc = 0; 163 resource_int_value(device_get_name(dev), 164 device_get_unit(dev), "ccc", &ctlr->ccc); 165 166 /* Setup our own memory management for channels. */ 167 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 168 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 169 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 170 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 171 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 172 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 173 return (error); 174 } 175 if ((error = rman_manage_region(&ctlr->sc_iomem, 176 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 177 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 178 rman_fini(&ctlr->sc_iomem); 179 return (error); 180 } 181 /* Get the HW capabilities */ 182 version = ATA_INL(ctlr->r_mem, AHCI_VS); 183 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP); 184 if (version >= 0x00010200) 185 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2); 186 if (ctlr->caps & AHCI_CAP_EMS) 187 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL); 188 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI); 189 190 /* Identify and set separate quirks for HBA and RAID f/w Marvells. */ 191 if ((ctlr->quirks & AHCI_Q_ALTSIG) && 192 (ctlr->caps & AHCI_CAP_SPM) == 0) 193 ctlr->quirks |= AHCI_Q_NOBSYRES; 194 195 if (ctlr->quirks & AHCI_Q_1CH) { 196 ctlr->caps &= ~AHCI_CAP_NPMASK; 197 ctlr->ichannels &= 0x01; 198 } 199 if (ctlr->quirks & AHCI_Q_2CH) { 200 ctlr->caps &= ~AHCI_CAP_NPMASK; 201 ctlr->caps |= 1; 202 ctlr->ichannels &= 0x03; 203 } 204 if (ctlr->quirks & AHCI_Q_4CH) { 205 ctlr->caps &= ~AHCI_CAP_NPMASK; 206 ctlr->caps |= 3; 207 ctlr->ichannels &= 0x0f; 208 } 209 ctlr->channels = MAX(flsl(ctlr->ichannels), 210 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 211 if (ctlr->quirks & AHCI_Q_NOPMP) 212 ctlr->caps &= ~AHCI_CAP_SPM; 213 if (ctlr->quirks & AHCI_Q_NONCQ) 214 ctlr->caps &= ~AHCI_CAP_SNCQ; 215 if ((ctlr->caps & AHCI_CAP_CCCS) == 0) 216 ctlr->ccc = 0; 217 ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC); 218 219 /* Create controller-wide DMA tag. */ 220 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 221 (ctlr->caps & AHCI_CAP_64BIT) ? BUS_SPACE_MAXADDR : 222 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 223 BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, 224 0, NULL, NULL, &ctlr->dma_tag)) { 225 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, 226 ctlr->r_mem); 227 rman_fini(&ctlr->sc_iomem); 228 return (ENXIO); 229 } 230 231 ahci_ctlr_setup(dev); 232 233 /* Setup interrupts. */ 234 if ((error = ahci_setup_interrupt(dev)) != 0) { 235 bus_dma_tag_destroy(ctlr->dma_tag); 236 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, 237 ctlr->r_mem); 238 rman_fini(&ctlr->sc_iomem); 239 return (error); 240 } 241 242 i = 0; 243 for (u = ctlr->ichannels; u != 0; u >>= 1) 244 i += (u & 1); 245 ctlr->direct = (ctlr->msi && (ctlr->numirqs > 1 || i <= 3)); 246 resource_int_value(device_get_name(dev), device_get_unit(dev), 247 "direct", &ctlr->direct); 248 /* Announce HW capabilities. */ 249 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT; 250 device_printf(dev, 251 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n", 252 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f), 253 ((version >> 4) & 0xf0) + (version & 0x0f), 254 (ctlr->caps & AHCI_CAP_NPMASK) + 1, 255 ((speed == 1) ? "1.5":((speed == 2) ? "3": 256 ((speed == 3) ? "6":"?"))), 257 (ctlr->caps & AHCI_CAP_SPM) ? 258 "supported" : "not supported", 259 (ctlr->caps & AHCI_CAP_FBSS) ? 260 " with FBS" : ""); 261 if (ctlr->quirks != 0) { 262 device_printf(dev, "quirks=0x%b\n", ctlr->quirks, 263 AHCI_Q_BIT_STRING); 264 } 265 if (bootverbose) { 266 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps", 267 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"", 268 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"", 269 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"", 270 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"", 271 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"", 272 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"", 273 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"", 274 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"", 275 ((speed == 1) ? "1.5":((speed == 2) ? "3": 276 ((speed == 3) ? "6":"?")))); 277 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n", 278 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"", 279 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"", 280 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"", 281 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"", 282 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"", 283 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"", 284 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1, 285 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"", 286 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"", 287 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"", 288 (ctlr->caps & AHCI_CAP_NPMASK) + 1); 289 } 290 if (bootverbose && version >= 0x00010200) { 291 device_printf(dev, "Caps2:%s%s%s%s%s%s\n", 292 (ctlr->caps2 & AHCI_CAP2_DESO) ? " DESO":"", 293 (ctlr->caps2 & AHCI_CAP2_SADM) ? " SADM":"", 294 (ctlr->caps2 & AHCI_CAP2_SDS) ? " SDS":"", 295 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"", 296 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"", 297 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":""); 298 } 299 /* Attach all channels on this controller */ 300 for (unit = 0; unit < ctlr->channels; unit++) { 301 child = device_add_child(dev, "ahcich", -1); 302 if (child == NULL) { 303 device_printf(dev, "failed to add channel device\n"); 304 continue; 305 } 306 device_set_ivars(child, (void *)(intptr_t)unit); 307 if ((ctlr->ichannels & (1 << unit)) == 0) 308 device_disable(child); 309 } 310 if (ctlr->caps & AHCI_CAP_EMS) { 311 child = device_add_child(dev, "ahciem", -1); 312 if (child == NULL) 313 device_printf(dev, "failed to add enclosure device\n"); 314 else 315 device_set_ivars(child, (void *)(intptr_t)-1); 316 } 317 bus_generic_attach(dev); 318 return (0); 319 } 320 321 int 322 ahci_detach(device_t dev) 323 { 324 struct ahci_controller *ctlr = device_get_softc(dev); 325 int i; 326 327 /* Detach & delete all children */ 328 device_delete_children(dev); 329 330 /* Free interrupts. */ 331 for (i = 0; i < ctlr->numirqs; i++) { 332 if (ctlr->irqs[i].r_irq) { 333 bus_teardown_intr(dev, ctlr->irqs[i].r_irq, 334 ctlr->irqs[i].handle); 335 bus_release_resource(dev, SYS_RES_IRQ, 336 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq); 337 } 338 } 339 bus_dma_tag_destroy(ctlr->dma_tag); 340 /* Free memory. */ 341 rman_fini(&ctlr->sc_iomem); 342 if (ctlr->r_mem) 343 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 344 return (0); 345 } 346 347 int 348 ahci_setup_interrupt(device_t dev) 349 { 350 struct ahci_controller *ctlr = device_get_softc(dev); 351 int i; 352 353 /* Check for single MSI vector fallback. */ 354 if (ctlr->numirqs > 1 && 355 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) { 356 device_printf(dev, "Falling back to one MSI\n"); 357 ctlr->numirqs = 1; 358 } 359 360 /* Ensure we don't overrun irqs. */ 361 if (ctlr->numirqs > AHCI_MAX_IRQS) { 362 device_printf(dev, "Too many irqs %d > %d (clamping)\n", 363 ctlr->numirqs, AHCI_MAX_IRQS); 364 ctlr->numirqs = AHCI_MAX_IRQS; 365 } 366 367 /* Allocate all IRQs. */ 368 for (i = 0; i < ctlr->numirqs; i++) { 369 ctlr->irqs[i].ctlr = ctlr; 370 ctlr->irqs[i].r_irq_rid = i + (ctlr->msi ? 1 : 0); 371 if (ctlr->channels == 1 && !ctlr->ccc && ctlr->msi) 372 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 373 else if (ctlr->numirqs == 1 || i >= ctlr->channels || 374 (ctlr->ccc && i == ctlr->cccv)) 375 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL; 376 else if (ctlr->channels > ctlr->numirqs && 377 i == ctlr->numirqs - 1) 378 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER; 379 else 380 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE; 381 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 382 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 383 device_printf(dev, "unable to map interrupt\n"); 384 return (ENXIO); 385 } 386 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL, 387 (ctlr->irqs[i].mode != AHCI_IRQ_MODE_ONE) ? ahci_intr : 388 ((ctlr->quirks & AHCI_Q_EDGEIS) ? ahci_intr_one_edge : 389 ahci_intr_one), 390 &ctlr->irqs[i], &ctlr->irqs[i].handle))) { 391 /* SOS XXX release r_irq */ 392 device_printf(dev, "unable to setup interrupt\n"); 393 return (ENXIO); 394 } 395 if (ctlr->numirqs > 1) { 396 bus_describe_intr(dev, ctlr->irqs[i].r_irq, 397 ctlr->irqs[i].handle, 398 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ? 399 "ch%d" : "%d", i); 400 } 401 } 402 return (0); 403 } 404 405 /* 406 * Common case interrupt handler. 407 */ 408 static void 409 ahci_intr(void *data) 410 { 411 struct ahci_controller_irq *irq = data; 412 struct ahci_controller *ctlr = irq->ctlr; 413 u_int32_t is, ise = 0; 414 void *arg; 415 int unit; 416 417 if (irq->mode == AHCI_IRQ_MODE_ALL) { 418 unit = 0; 419 if (ctlr->ccc) 420 is = ctlr->ichannels; 421 else 422 is = ATA_INL(ctlr->r_mem, AHCI_IS); 423 } else { /* AHCI_IRQ_MODE_AFTER */ 424 unit = irq->r_irq_rid - 1; 425 is = ATA_INL(ctlr->r_mem, AHCI_IS); 426 is &= (0xffffffff << unit); 427 } 428 /* CCC interrupt is edge triggered. */ 429 if (ctlr->ccc) 430 ise = 1 << ctlr->cccv; 431 /* Some controllers have edge triggered IS. */ 432 if (ctlr->quirks & AHCI_Q_EDGEIS) 433 ise |= is; 434 if (ise != 0) 435 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise); 436 for (; unit < ctlr->channels; unit++) { 437 if ((is & (1 << unit)) != 0 && 438 (arg = ctlr->interrupt[unit].argument)) { 439 ctlr->interrupt[unit].function(arg); 440 } 441 } 442 /* AHCI declares level triggered IS. */ 443 if (!(ctlr->quirks & AHCI_Q_EDGEIS)) 444 ATA_OUTL(ctlr->r_mem, AHCI_IS, is); 445 } 446 447 /* 448 * Simplified interrupt handler for multivector MSI mode. 449 */ 450 static void 451 ahci_intr_one(void *data) 452 { 453 struct ahci_controller_irq *irq = data; 454 struct ahci_controller *ctlr = irq->ctlr; 455 void *arg; 456 int unit; 457 458 unit = irq->r_irq_rid - 1; 459 if ((arg = ctlr->interrupt[unit].argument)) 460 ctlr->interrupt[unit].function(arg); 461 /* AHCI declares level triggered IS. */ 462 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 463 } 464 465 static void 466 ahci_intr_one_edge(void *data) 467 { 468 struct ahci_controller_irq *irq = data; 469 struct ahci_controller *ctlr = irq->ctlr; 470 void *arg; 471 int unit; 472 473 unit = irq->r_irq_rid - 1; 474 /* Some controllers have edge triggered IS. */ 475 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); 476 if ((arg = ctlr->interrupt[unit].argument)) 477 ctlr->interrupt[unit].function(arg); 478 } 479 480 struct resource * 481 ahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 482 u_long start, u_long end, u_long count, u_int flags) 483 { 484 struct ahci_controller *ctlr = device_get_softc(dev); 485 struct resource *res; 486 long st; 487 int offset, size, unit; 488 489 unit = (intptr_t)device_get_ivars(child); 490 res = NULL; 491 switch (type) { 492 case SYS_RES_MEMORY: 493 if (unit >= 0) { 494 offset = AHCI_OFFSET + (unit << 7); 495 size = 128; 496 } else if (*rid == 0) { 497 offset = AHCI_EM_CTL; 498 size = 4; 499 } else { 500 offset = (ctlr->emloc & 0xffff0000) >> 14; 501 size = (ctlr->emloc & 0x0000ffff) << 2; 502 if (*rid != 1) { 503 if (*rid == 2 && (ctlr->capsem & 504 (AHCI_EM_XMT | AHCI_EM_SMB)) == 0) 505 offset += size; 506 else 507 break; 508 } 509 } 510 st = rman_get_start(ctlr->r_mem); 511 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 512 st + offset + size - 1, size, RF_ACTIVE, child); 513 if (res) { 514 bus_space_handle_t bsh; 515 bus_space_tag_t bst; 516 bsh = rman_get_bushandle(ctlr->r_mem); 517 bst = rman_get_bustag(ctlr->r_mem); 518 bus_space_subregion(bst, bsh, offset, 128, &bsh); 519 rman_set_bushandle(res, bsh); 520 rman_set_bustag(res, bst); 521 } 522 break; 523 case SYS_RES_IRQ: 524 if (*rid == ATA_IRQ_RID) 525 res = ctlr->irqs[0].r_irq; 526 break; 527 } 528 return (res); 529 } 530 531 int 532 ahci_release_resource(device_t dev, device_t child, int type, int rid, 533 struct resource *r) 534 { 535 536 switch (type) { 537 case SYS_RES_MEMORY: 538 rman_release_resource(r); 539 return (0); 540 case SYS_RES_IRQ: 541 if (rid != ATA_IRQ_RID) 542 return (ENOENT); 543 return (0); 544 } 545 return (EINVAL); 546 } 547 548 int 549 ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 550 int flags, driver_filter_t *filter, driver_intr_t *function, 551 void *argument, void **cookiep) 552 { 553 struct ahci_controller *ctlr = device_get_softc(dev); 554 int unit = (intptr_t)device_get_ivars(child); 555 556 if (filter != NULL) { 557 printf("ahci.c: we cannot use a filter here\n"); 558 return (EINVAL); 559 } 560 ctlr->interrupt[unit].function = function; 561 ctlr->interrupt[unit].argument = argument; 562 return (0); 563 } 564 565 int 566 ahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 567 void *cookie) 568 { 569 struct ahci_controller *ctlr = device_get_softc(dev); 570 int unit = (intptr_t)device_get_ivars(child); 571 572 ctlr->interrupt[unit].function = NULL; 573 ctlr->interrupt[unit].argument = NULL; 574 return (0); 575 } 576 577 int 578 ahci_print_child(device_t dev, device_t child) 579 { 580 int retval, channel; 581 582 retval = bus_print_child_header(dev, child); 583 channel = (int)(intptr_t)device_get_ivars(child); 584 if (channel >= 0) 585 retval += printf(" at channel %d", channel); 586 retval += bus_print_child_footer(dev, child); 587 return (retval); 588 } 589 590 int 591 ahci_child_location_str(device_t dev, device_t child, char *buf, 592 size_t buflen) 593 { 594 int channel; 595 596 channel = (int)(intptr_t)device_get_ivars(child); 597 if (channel >= 0) 598 snprintf(buf, buflen, "channel=%d", channel); 599 return (0); 600 } 601 602 bus_dma_tag_t 603 ahci_get_dma_tag(device_t dev, device_t child) 604 { 605 struct ahci_controller *ctlr = device_get_softc(dev); 606 607 return (ctlr->dma_tag); 608 } 609 610 static int 611 ahci_ch_probe(device_t dev) 612 { 613 614 device_set_desc_copy(dev, "AHCI channel"); 615 return (BUS_PROBE_DEFAULT); 616 } 617 618 static int 619 ahci_ch_attach(device_t dev) 620 { 621 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev)); 622 struct ahci_channel *ch = device_get_softc(dev); 623 struct cam_devq *devq; 624 int rid, error, i, sata_rev = 0; 625 u_int32_t version; 626 627 ch->dev = dev; 628 ch->unit = (intptr_t)device_get_ivars(dev); 629 ch->caps = ctlr->caps; 630 ch->caps2 = ctlr->caps2; 631 ch->quirks = ctlr->quirks; 632 ch->vendorid = ctlr->vendorid; 633 ch->deviceid = ctlr->deviceid; 634 ch->subvendorid = ctlr->subvendorid; 635 ch->subdeviceid = ctlr->subdeviceid; 636 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1; 637 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF); 638 ch->pm_level = 0; 639 resource_int_value(device_get_name(dev), 640 device_get_unit(dev), "pm_level", &ch->pm_level); 641 STAILQ_INIT(&ch->doneq); 642 if (ch->pm_level > 3) 643 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 644 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0); 645 /* JMicron external ports (0) sometimes limited */ 646 if ((ctlr->quirks & AHCI_Q_SATA1_UNIT0) && ch->unit == 0) 647 sata_rev = 1; 648 if (ch->quirks & AHCI_Q_SATA2) 649 sata_rev = 2; 650 resource_int_value(device_get_name(dev), 651 device_get_unit(dev), "sata_rev", &sata_rev); 652 for (i = 0; i < 16; i++) { 653 ch->user[i].revision = sata_rev; 654 ch->user[i].mode = 0; 655 ch->user[i].bytecount = 8192; 656 ch->user[i].tags = ch->numslots; 657 ch->user[i].caps = 0; 658 ch->curr[i] = ch->user[i]; 659 if (ch->pm_level) { 660 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ | 661 CTS_SATA_CAPS_H_APST | 662 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST; 663 } 664 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA | 665 CTS_SATA_CAPS_H_AN; 666 } 667 rid = 0; 668 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 669 &rid, RF_ACTIVE))) 670 return (ENXIO); 671 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD); 672 version = ATA_INL(ctlr->r_mem, AHCI_VS); 673 if (version < 0x00010200 && (ctlr->caps & AHCI_CAP_FBSS)) 674 ch->chcaps |= AHCI_P_CMD_FBSCP; 675 if (ch->caps2 & AHCI_CAP2_SDS) 676 ch->chscaps = ATA_INL(ch->r_mem, AHCI_P_DEVSLP); 677 if (bootverbose) { 678 device_printf(dev, "Caps:%s%s%s%s%s%s\n", 679 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"", 680 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"", 681 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"", 682 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"", 683 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":"", 684 (ch->chscaps & AHCI_P_DEVSLP_DSP) ? " DSP":""); 685 } 686 ahci_dmainit(dev); 687 ahci_slotsalloc(dev); 688 mtx_lock(&ch->mtx); 689 ahci_ch_init(dev); 690 rid = ATA_IRQ_RID; 691 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 692 &rid, RF_SHAREABLE | RF_ACTIVE))) { 693 device_printf(dev, "Unable to map interrupt\n"); 694 error = ENXIO; 695 goto err0; 696 } 697 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 698 ctlr->direct ? ahci_ch_intr_direct : ahci_ch_intr, 699 ch, &ch->ih))) { 700 device_printf(dev, "Unable to setup interrupt\n"); 701 error = ENXIO; 702 goto err1; 703 } 704 /* Create the device queue for our SIM. */ 705 devq = cam_simq_alloc(ch->numslots); 706 if (devq == NULL) { 707 device_printf(dev, "Unable to allocate simq\n"); 708 error = ENOMEM; 709 goto err1; 710 } 711 /* Construct SIM entry */ 712 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch, 713 device_get_unit(dev), (struct mtx *)&ch->mtx, 714 (ch->quirks & AHCI_Q_NOCCS) ? 1 : min(2, ch->numslots), 715 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0, 716 devq); 717 if (ch->sim == NULL) { 718 cam_simq_free(devq); 719 device_printf(dev, "unable to allocate sim\n"); 720 error = ENOMEM; 721 goto err1; 722 } 723 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 724 device_printf(dev, "unable to register xpt bus\n"); 725 error = ENXIO; 726 goto err2; 727 } 728 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 729 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 730 device_printf(dev, "unable to create path\n"); 731 error = ENXIO; 732 goto err3; 733 } 734 if (ch->pm_level > 3) { 735 callout_reset(&ch->pm_timer, 736 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 737 ahci_ch_pm, ch); 738 } 739 mtx_unlock(&ch->mtx); 740 return (0); 741 742 err3: 743 xpt_bus_deregister(cam_sim_path(ch->sim)); 744 err2: 745 cam_sim_free(ch->sim, /*free_devq*/TRUE); 746 err1: 747 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 748 err0: 749 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 750 mtx_unlock(&ch->mtx); 751 mtx_destroy(&ch->mtx); 752 return (error); 753 } 754 755 static int 756 ahci_ch_detach(device_t dev) 757 { 758 struct ahci_channel *ch = device_get_softc(dev); 759 760 mtx_lock(&ch->mtx); 761 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 762 /* Forget about reset. */ 763 if (ch->resetting) { 764 ch->resetting = 0; 765 xpt_release_simq(ch->sim, TRUE); 766 } 767 xpt_free_path(ch->path); 768 xpt_bus_deregister(cam_sim_path(ch->sim)); 769 cam_sim_free(ch->sim, /*free_devq*/TRUE); 770 mtx_unlock(&ch->mtx); 771 772 if (ch->pm_level > 3) 773 callout_drain(&ch->pm_timer); 774 callout_drain(&ch->reset_timer); 775 bus_teardown_intr(dev, ch->r_irq, ch->ih); 776 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 777 778 ahci_ch_deinit(dev); 779 ahci_slotsfree(dev); 780 ahci_dmafini(dev); 781 782 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 783 mtx_destroy(&ch->mtx); 784 return (0); 785 } 786 787 static int 788 ahci_ch_init(device_t dev) 789 { 790 struct ahci_channel *ch = device_get_softc(dev); 791 uint64_t work; 792 793 /* Disable port interrupts */ 794 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 795 /* Setup work areas */ 796 work = ch->dma.work_bus + AHCI_CL_OFFSET; 797 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff); 798 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32); 799 work = ch->dma.rfis_bus; 800 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff); 801 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32); 802 /* Activate the channel and power/spin up device */ 803 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 804 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 805 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) | 806 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 ))); 807 ahci_start_fr(ch); 808 ahci_start(ch, 1); 809 return (0); 810 } 811 812 static int 813 ahci_ch_deinit(device_t dev) 814 { 815 struct ahci_channel *ch = device_get_softc(dev); 816 817 /* Disable port interrupts. */ 818 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 819 /* Reset command register. */ 820 ahci_stop(ch); 821 ahci_stop_fr(ch); 822 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0); 823 /* Allow everything, including partial and slumber modes. */ 824 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0); 825 /* Request slumber mode transition and give some time to get there. */ 826 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER); 827 DELAY(100); 828 /* Disable PHY. */ 829 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 830 return (0); 831 } 832 833 static int 834 ahci_ch_suspend(device_t dev) 835 { 836 struct ahci_channel *ch = device_get_softc(dev); 837 838 mtx_lock(&ch->mtx); 839 xpt_freeze_simq(ch->sim, 1); 840 /* Forget about reset. */ 841 if (ch->resetting) { 842 ch->resetting = 0; 843 callout_stop(&ch->reset_timer); 844 xpt_release_simq(ch->sim, TRUE); 845 } 846 while (ch->oslots) 847 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100); 848 ahci_ch_deinit(dev); 849 mtx_unlock(&ch->mtx); 850 return (0); 851 } 852 853 static int 854 ahci_ch_resume(device_t dev) 855 { 856 struct ahci_channel *ch = device_get_softc(dev); 857 858 mtx_lock(&ch->mtx); 859 ahci_ch_init(dev); 860 ahci_reset(ch); 861 xpt_release_simq(ch->sim, TRUE); 862 mtx_unlock(&ch->mtx); 863 return (0); 864 } 865 866 devclass_t ahcich_devclass; 867 static device_method_t ahcich_methods[] = { 868 DEVMETHOD(device_probe, ahci_ch_probe), 869 DEVMETHOD(device_attach, ahci_ch_attach), 870 DEVMETHOD(device_detach, ahci_ch_detach), 871 DEVMETHOD(device_suspend, ahci_ch_suspend), 872 DEVMETHOD(device_resume, ahci_ch_resume), 873 DEVMETHOD_END 874 }; 875 static driver_t ahcich_driver = { 876 "ahcich", 877 ahcich_methods, 878 sizeof(struct ahci_channel) 879 }; 880 DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, NULL, NULL); 881 882 struct ahci_dc_cb_args { 883 bus_addr_t maddr; 884 int error; 885 }; 886 887 static void 888 ahci_dmainit(device_t dev) 889 { 890 struct ahci_channel *ch = device_get_softc(dev); 891 struct ahci_dc_cb_args dcba; 892 size_t rfsize; 893 894 /* Command area. */ 895 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 896 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 897 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE, 898 0, NULL, NULL, &ch->dma.work_tag)) 899 goto error; 900 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 901 BUS_DMA_ZERO, &ch->dma.work_map)) 902 goto error; 903 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work, 904 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 905 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 906 goto error; 907 } 908 ch->dma.work_bus = dcba.maddr; 909 /* FIS receive area. */ 910 if (ch->chcaps & AHCI_P_CMD_FBSCP) 911 rfsize = 4096; 912 else 913 rfsize = 256; 914 if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0, 915 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 916 NULL, NULL, rfsize, 1, rfsize, 917 0, NULL, NULL, &ch->dma.rfis_tag)) 918 goto error; 919 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0, 920 &ch->dma.rfis_map)) 921 goto error; 922 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis, 923 rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) { 924 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 925 goto error; 926 } 927 ch->dma.rfis_bus = dcba.maddr; 928 /* Data area. */ 929 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0, 930 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 931 NULL, NULL, 932 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots, 933 AHCI_SG_ENTRIES, AHCI_PRD_MAX, 934 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 935 goto error; 936 } 937 return; 938 939 error: 940 device_printf(dev, "WARNING - DMA initialization failed\n"); 941 ahci_dmafini(dev); 942 } 943 944 static void 945 ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 946 { 947 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc; 948 949 if (!(dcba->error = error)) 950 dcba->maddr = segs[0].ds_addr; 951 } 952 953 static void 954 ahci_dmafini(device_t dev) 955 { 956 struct ahci_channel *ch = device_get_softc(dev); 957 958 if (ch->dma.data_tag) { 959 bus_dma_tag_destroy(ch->dma.data_tag); 960 ch->dma.data_tag = NULL; 961 } 962 if (ch->dma.rfis_bus) { 963 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map); 964 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map); 965 ch->dma.rfis_bus = 0; 966 ch->dma.rfis = NULL; 967 } 968 if (ch->dma.work_bus) { 969 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map); 970 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map); 971 ch->dma.work_bus = 0; 972 ch->dma.work = NULL; 973 } 974 if (ch->dma.work_tag) { 975 bus_dma_tag_destroy(ch->dma.work_tag); 976 ch->dma.work_tag = NULL; 977 } 978 } 979 980 static void 981 ahci_slotsalloc(device_t dev) 982 { 983 struct ahci_channel *ch = device_get_softc(dev); 984 int i; 985 986 /* Alloc and setup command/dma slots */ 987 bzero(ch->slot, sizeof(ch->slot)); 988 for (i = 0; i < ch->numslots; i++) { 989 struct ahci_slot *slot = &ch->slot[i]; 990 991 slot->ch = ch; 992 slot->slot = i; 993 slot->state = AHCI_SLOT_EMPTY; 994 slot->ccb = NULL; 995 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 996 997 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 998 device_printf(ch->dev, "FAILURE - create data_map\n"); 999 } 1000 } 1001 1002 static void 1003 ahci_slotsfree(device_t dev) 1004 { 1005 struct ahci_channel *ch = device_get_softc(dev); 1006 int i; 1007 1008 /* Free all dma slots */ 1009 for (i = 0; i < ch->numslots; i++) { 1010 struct ahci_slot *slot = &ch->slot[i]; 1011 1012 callout_drain(&slot->timeout); 1013 if (slot->dma.data_map) { 1014 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 1015 slot->dma.data_map = NULL; 1016 } 1017 } 1018 } 1019 1020 static int 1021 ahci_phy_check_events(struct ahci_channel *ch, u_int32_t serr) 1022 { 1023 1024 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) || 1025 ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) { 1026 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 1027 union ccb *ccb; 1028 1029 if (bootverbose) { 1030 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 1031 device_printf(ch->dev, "CONNECT requested\n"); 1032 else 1033 device_printf(ch->dev, "DISCONNECT requested\n"); 1034 } 1035 ahci_reset(ch); 1036 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1037 return (0); 1038 if (xpt_create_path(&ccb->ccb_h.path, NULL, 1039 cam_sim_path(ch->sim), 1040 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1041 xpt_free_ccb(ccb); 1042 return (0); 1043 } 1044 xpt_rescan(ccb); 1045 return (1); 1046 } 1047 return (0); 1048 } 1049 1050 static void 1051 ahci_cpd_check_events(struct ahci_channel *ch) 1052 { 1053 u_int32_t status; 1054 union ccb *ccb; 1055 device_t dev; 1056 1057 if (ch->pm_level == 0) 1058 return; 1059 1060 status = ATA_INL(ch->r_mem, AHCI_P_CMD); 1061 if ((status & AHCI_P_CMD_CPD) == 0) 1062 return; 1063 1064 if (bootverbose) { 1065 dev = ch->dev; 1066 if (status & AHCI_P_CMD_CPS) { 1067 device_printf(dev, "COLD CONNECT requested\n"); 1068 } else 1069 device_printf(dev, "COLD DISCONNECT requested\n"); 1070 } 1071 ahci_reset(ch); 1072 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 1073 return; 1074 if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim), 1075 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 1076 xpt_free_ccb(ccb); 1077 return; 1078 } 1079 xpt_rescan(ccb); 1080 } 1081 1082 static void 1083 ahci_notify_events(struct ahci_channel *ch, u_int32_t status) 1084 { 1085 struct cam_path *dpath; 1086 int i; 1087 1088 if (ch->caps & AHCI_CAP_SSNTF) 1089 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status); 1090 if (bootverbose) 1091 device_printf(ch->dev, "SNTF 0x%04x\n", status); 1092 for (i = 0; i < 16; i++) { 1093 if ((status & (1 << i)) == 0) 1094 continue; 1095 if (xpt_create_path(&dpath, NULL, 1096 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) { 1097 xpt_async(AC_SCSI_AEN, dpath, NULL); 1098 xpt_free_path(dpath); 1099 } 1100 } 1101 } 1102 1103 static void 1104 ahci_done(struct ahci_channel *ch, union ccb *ccb) 1105 { 1106 1107 mtx_assert(&ch->mtx, MA_OWNED); 1108 if ((ccb->ccb_h.func_code & XPT_FC_QUEUED) == 0 || 1109 ch->batch == 0) { 1110 xpt_done(ccb); 1111 return; 1112 } 1113 1114 STAILQ_INSERT_TAIL(&ch->doneq, &ccb->ccb_h, sim_links.stqe); 1115 } 1116 1117 static void 1118 ahci_ch_intr(void *arg) 1119 { 1120 struct ahci_channel *ch = (struct ahci_channel *)arg; 1121 uint32_t istatus; 1122 1123 /* Read interrupt statuses. */ 1124 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1125 1126 mtx_lock(&ch->mtx); 1127 ahci_ch_intr_main(ch, istatus); 1128 mtx_unlock(&ch->mtx); 1129 } 1130 1131 static void 1132 ahci_ch_intr_direct(void *arg) 1133 { 1134 struct ahci_channel *ch = (struct ahci_channel *)arg; 1135 struct ccb_hdr *ccb_h; 1136 uint32_t istatus; 1137 STAILQ_HEAD(, ccb_hdr) tmp_doneq = STAILQ_HEAD_INITIALIZER(tmp_doneq); 1138 1139 /* Read interrupt statuses. */ 1140 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 1141 1142 mtx_lock(&ch->mtx); 1143 ch->batch = 1; 1144 ahci_ch_intr_main(ch, istatus); 1145 ch->batch = 0; 1146 /* 1147 * Prevent the possibility of issues caused by processing the queue 1148 * while unlocked below by moving the contents to a local queue. 1149 */ 1150 STAILQ_CONCAT(&tmp_doneq, &ch->doneq); 1151 mtx_unlock(&ch->mtx); 1152 while ((ccb_h = STAILQ_FIRST(&tmp_doneq)) != NULL) { 1153 STAILQ_REMOVE_HEAD(&tmp_doneq, sim_links.stqe); 1154 xpt_done_direct((union ccb *)ccb_h); 1155 } 1156 } 1157 1158 static void 1159 ahci_ch_pm(void *arg) 1160 { 1161 struct ahci_channel *ch = (struct ahci_channel *)arg; 1162 uint32_t work; 1163 1164 if (ch->numrslots != 0) 1165 return; 1166 work = ATA_INL(ch->r_mem, AHCI_P_CMD); 1167 if (ch->pm_level == 4) 1168 work |= AHCI_P_CMD_PARTIAL; 1169 else 1170 work |= AHCI_P_CMD_SLUMBER; 1171 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work); 1172 } 1173 1174 static void 1175 ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus) 1176 { 1177 uint32_t cstatus, serr = 0, sntf = 0, ok, err; 1178 enum ahci_err_type et; 1179 int i, ccs, port, reset = 0; 1180 1181 /* Clear interrupt statuses. */ 1182 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus); 1183 /* Read command statuses. */ 1184 if (ch->numtslots != 0) 1185 cstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1186 else 1187 cstatus = 0; 1188 if (ch->numrslots != ch->numtslots) 1189 cstatus |= ATA_INL(ch->r_mem, AHCI_P_CI); 1190 /* Read SNTF in one of possible ways. */ 1191 if ((istatus & AHCI_P_IX_SDB) && 1192 (ch->pm_present || ch->curr[0].atapi != 0)) { 1193 if (ch->caps & AHCI_CAP_SSNTF) 1194 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF); 1195 else if (ch->fbs_enabled) { 1196 u_int8_t *fis = ch->dma.rfis + 0x58; 1197 1198 for (i = 0; i < 16; i++) { 1199 if (fis[1] & 0x80) { 1200 fis[1] &= 0x7f; 1201 sntf |= 1 << i; 1202 } 1203 fis += 256; 1204 } 1205 } else { 1206 u_int8_t *fis = ch->dma.rfis + 0x58; 1207 1208 if (fis[1] & 0x80) 1209 sntf = (1 << (fis[1] & 0x0f)); 1210 } 1211 } 1212 /* Process PHY events */ 1213 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF | 1214 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1215 serr = ATA_INL(ch->r_mem, AHCI_P_SERR); 1216 if (serr) { 1217 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr); 1218 reset = ahci_phy_check_events(ch, serr); 1219 } 1220 } 1221 /* Process cold presence detection events */ 1222 if ((istatus & AHCI_P_IX_CPD) && !reset) 1223 ahci_cpd_check_events(ch); 1224 /* Process command errors */ 1225 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF | 1226 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) { 1227 if (ch->quirks & AHCI_Q_NOCCS) { 1228 /* 1229 * ASMedia chips sometimes report failed commands as 1230 * completed. Count all running commands as failed. 1231 */ 1232 cstatus |= ch->rslots; 1233 1234 /* They also report wrong CCS, so try to guess one. */ 1235 ccs = powerof2(cstatus) ? ffs(cstatus) - 1 : -1; 1236 } else { 1237 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & 1238 AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT; 1239 } 1240 //device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n", 1241 // __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD), 1242 // serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs); 1243 port = -1; 1244 if (ch->fbs_enabled) { 1245 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS); 1246 if (fbs & AHCI_P_FBS_SDE) { 1247 port = (fbs & AHCI_P_FBS_DWE) 1248 >> AHCI_P_FBS_DWE_SHIFT; 1249 } else { 1250 for (i = 0; i < 16; i++) { 1251 if (ch->numrslotspd[i] == 0) 1252 continue; 1253 if (port == -1) 1254 port = i; 1255 else if (port != i) { 1256 port = -2; 1257 break; 1258 } 1259 } 1260 } 1261 } 1262 err = ch->rslots & cstatus; 1263 } else { 1264 ccs = 0; 1265 err = 0; 1266 port = -1; 1267 } 1268 /* Complete all successfull commands. */ 1269 ok = ch->rslots & ~cstatus; 1270 for (i = 0; i < ch->numslots; i++) { 1271 if ((ok >> i) & 1) 1272 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE); 1273 } 1274 /* On error, complete the rest of commands with error statuses. */ 1275 if (err) { 1276 if (ch->frozen) { 1277 union ccb *fccb = ch->frozen; 1278 ch->frozen = NULL; 1279 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1280 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1281 xpt_freeze_devq(fccb->ccb_h.path, 1); 1282 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1283 } 1284 ahci_done(ch, fccb); 1285 } 1286 for (i = 0; i < ch->numslots; i++) { 1287 /* XXX: reqests in loading state. */ 1288 if (((err >> i) & 1) == 0) 1289 continue; 1290 if (port >= 0 && 1291 ch->slot[i].ccb->ccb_h.target_id != port) 1292 continue; 1293 if (istatus & AHCI_P_IX_TFE) { 1294 if (port != -2) { 1295 /* Task File Error */ 1296 if (ch->numtslotspd[ 1297 ch->slot[i].ccb->ccb_h.target_id] == 0) { 1298 /* Untagged operation. */ 1299 if (i == ccs) 1300 et = AHCI_ERR_TFE; 1301 else 1302 et = AHCI_ERR_INNOCENT; 1303 } else { 1304 /* Tagged operation. */ 1305 et = AHCI_ERR_NCQ; 1306 } 1307 } else { 1308 et = AHCI_ERR_TFE; 1309 ch->fatalerr = 1; 1310 } 1311 } else if (istatus & AHCI_P_IX_IF) { 1312 if (ch->numtslots == 0 && i != ccs && port != -2) 1313 et = AHCI_ERR_INNOCENT; 1314 else 1315 et = AHCI_ERR_SATA; 1316 } else 1317 et = AHCI_ERR_INVALID; 1318 ahci_end_transaction(&ch->slot[i], et); 1319 } 1320 /* 1321 * We can't reinit port if there are some other 1322 * commands active, use resume to complete them. 1323 */ 1324 if (ch->rslots != 0 && !ch->recoverycmd) 1325 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC); 1326 } 1327 /* Process NOTIFY events */ 1328 if (sntf) 1329 ahci_notify_events(ch, sntf); 1330 } 1331 1332 /* Must be called with channel locked. */ 1333 static int 1334 ahci_check_collision(struct ahci_channel *ch, union ccb *ccb) 1335 { 1336 int t = ccb->ccb_h.target_id; 1337 1338 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1339 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1340 /* Tagged command while we have no supported tag free. */ 1341 if (((~ch->oslots) & (0xffffffff >> (32 - 1342 ch->curr[t].tags))) == 0) 1343 return (1); 1344 /* If we have FBS */ 1345 if (ch->fbs_enabled) { 1346 /* Tagged command while untagged are active. */ 1347 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0) 1348 return (1); 1349 } else { 1350 /* Tagged command while untagged are active. */ 1351 if (ch->numrslots != 0 && ch->numtslots == 0) 1352 return (1); 1353 /* Tagged command while tagged to other target is active. */ 1354 if (ch->numtslots != 0 && 1355 ch->taggedtarget != ccb->ccb_h.target_id) 1356 return (1); 1357 } 1358 } else { 1359 /* If we have FBS */ 1360 if (ch->fbs_enabled) { 1361 /* Untagged command while tagged are active. */ 1362 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0) 1363 return (1); 1364 } else { 1365 /* Untagged command while tagged are active. */ 1366 if (ch->numrslots != 0 && ch->numtslots != 0) 1367 return (1); 1368 } 1369 } 1370 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1371 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) { 1372 /* Atomic command while anything active. */ 1373 if (ch->numrslots != 0) 1374 return (1); 1375 } 1376 /* We have some atomic command running. */ 1377 if (ch->aslots != 0) 1378 return (1); 1379 return (0); 1380 } 1381 1382 /* Must be called with channel locked. */ 1383 static void 1384 ahci_begin_transaction(struct ahci_channel *ch, union ccb *ccb) 1385 { 1386 struct ahci_slot *slot; 1387 int tag, tags; 1388 1389 /* Choose empty slot. */ 1390 tags = ch->numslots; 1391 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1392 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) 1393 tags = ch->curr[ccb->ccb_h.target_id].tags; 1394 if (ch->lastslot + 1 < tags) 1395 tag = ffs(~(ch->oslots >> (ch->lastslot + 1))); 1396 else 1397 tag = 0; 1398 if (tag == 0 || tag + ch->lastslot >= tags) 1399 tag = ffs(~ch->oslots) - 1; 1400 else 1401 tag += ch->lastslot; 1402 ch->lastslot = tag; 1403 /* Occupy chosen slot. */ 1404 slot = &ch->slot[tag]; 1405 slot->ccb = ccb; 1406 /* Stop PM timer. */ 1407 if (ch->numrslots == 0 && ch->pm_level > 3) 1408 callout_stop(&ch->pm_timer); 1409 /* Update channel stats. */ 1410 ch->oslots |= (1 << tag); 1411 ch->numrslots++; 1412 ch->numrslotspd[ccb->ccb_h.target_id]++; 1413 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1414 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1415 ch->numtslots++; 1416 ch->numtslotspd[ccb->ccb_h.target_id]++; 1417 ch->taggedtarget = ccb->ccb_h.target_id; 1418 } 1419 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1420 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) 1421 ch->aslots |= (1 << tag); 1422 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1423 slot->state = AHCI_SLOT_LOADING; 1424 bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map, ccb, 1425 ahci_dmasetprd, slot, 0); 1426 } else { 1427 slot->dma.nsegs = 0; 1428 ahci_execute_transaction(slot); 1429 } 1430 } 1431 1432 /* Locked by busdma engine. */ 1433 static void 1434 ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1435 { 1436 struct ahci_slot *slot = arg; 1437 struct ahci_channel *ch = slot->ch; 1438 struct ahci_cmd_tab *ctp; 1439 struct ahci_dma_prd *prd; 1440 int i; 1441 1442 if (error) { 1443 device_printf(ch->dev, "DMA load error\n"); 1444 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1445 return; 1446 } 1447 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n")); 1448 /* Get a piece of the workspace for this request */ 1449 ctp = (struct ahci_cmd_tab *) 1450 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1451 /* Fill S/G table */ 1452 prd = &ctp->prd_tab[0]; 1453 for (i = 0; i < nsegs; i++) { 1454 prd[i].dba = htole64(segs[i].ds_addr); 1455 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK); 1456 } 1457 slot->dma.nsegs = nsegs; 1458 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1459 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1460 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1461 ahci_execute_transaction(slot); 1462 } 1463 1464 /* Must be called with channel locked. */ 1465 static void 1466 ahci_execute_transaction(struct ahci_slot *slot) 1467 { 1468 struct ahci_channel *ch = slot->ch; 1469 struct ahci_cmd_tab *ctp; 1470 struct ahci_cmd_list *clp; 1471 union ccb *ccb = slot->ccb; 1472 int port = ccb->ccb_h.target_id & 0x0f; 1473 int fis_size, i, softreset; 1474 uint8_t *fis = ch->dma.rfis + 0x40; 1475 uint8_t val; 1476 1477 /* Get a piece of the workspace for this request */ 1478 ctp = (struct ahci_cmd_tab *) 1479 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot)); 1480 /* Setup the FIS for this request */ 1481 if (!(fis_size = ahci_setup_fis(ch, ctp, ccb, slot->slot))) { 1482 device_printf(ch->dev, "Setting up SATA FIS failed\n"); 1483 ahci_end_transaction(slot, AHCI_ERR_INVALID); 1484 return; 1485 } 1486 /* Setup the command list entry */ 1487 clp = (struct ahci_cmd_list *) 1488 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1489 clp->cmd_flags = htole16( 1490 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) | 1491 (ccb->ccb_h.func_code == XPT_SCSI_IO ? 1492 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) | 1493 (fis_size / sizeof(u_int32_t)) | 1494 (port << 12)); 1495 clp->prd_length = htole16(slot->dma.nsegs); 1496 /* Special handling for Soft Reset command. */ 1497 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1498 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1499 if (ccb->ataio.cmd.control & ATA_A_RESET) { 1500 softreset = 1; 1501 /* Kick controller into sane state */ 1502 ahci_stop(ch); 1503 ahci_clo(ch); 1504 ahci_start(ch, 0); 1505 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY; 1506 } else { 1507 softreset = 2; 1508 /* Prepare FIS receive area for check. */ 1509 for (i = 0; i < 20; i++) 1510 fis[i] = 0xff; 1511 } 1512 } else 1513 softreset = 0; 1514 clp->bytecount = 0; 1515 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET + 1516 (AHCI_CT_SIZE * slot->slot)); 1517 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1518 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1519 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1520 BUS_DMASYNC_PREREAD); 1521 /* Set ACTIVE bit for NCQ commands. */ 1522 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1523 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1524 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot); 1525 } 1526 /* If FBS is enabled, set PMP port. */ 1527 if (ch->fbs_enabled) { 1528 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | 1529 (port << AHCI_P_FBS_DEV_SHIFT)); 1530 } 1531 /* Issue command to the controller. */ 1532 slot->state = AHCI_SLOT_RUNNING; 1533 ch->rslots |= (1 << slot->slot); 1534 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot)); 1535 /* Device reset commands doesn't interrupt. Poll them. */ 1536 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1537 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) { 1538 int count, timeout = ccb->ccb_h.timeout * 100; 1539 enum ahci_err_type et = AHCI_ERR_NONE; 1540 1541 for (count = 0; count < timeout; count++) { 1542 DELAY(10); 1543 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot))) 1544 break; 1545 if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) && 1546 softreset != 1) { 1547 #if 0 1548 device_printf(ch->dev, 1549 "Poll error on slot %d, TFD: %04x\n", 1550 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD)); 1551 #endif 1552 et = AHCI_ERR_TFE; 1553 break; 1554 } 1555 /* Workaround for ATI SB600/SB700 chipsets. */ 1556 if (ccb->ccb_h.target_id == 15 && 1557 (ch->quirks & AHCI_Q_ATI_PMP_BUG) && 1558 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) { 1559 et = AHCI_ERR_TIMEOUT; 1560 break; 1561 } 1562 } 1563 1564 /* 1565 * Marvell HBAs with non-RAID firmware do not wait for 1566 * readiness after soft reset, so we have to wait here. 1567 * Marvell RAIDs do not have this problem, but instead 1568 * sometimes forget to update FIS receive area, breaking 1569 * this wait. 1570 */ 1571 if ((ch->quirks & AHCI_Q_NOBSYRES) == 0 && 1572 (ch->quirks & AHCI_Q_ATI_PMP_BUG) == 0 && 1573 softreset == 2 && et == AHCI_ERR_NONE) { 1574 while ((val = fis[2]) & ATA_S_BUSY) { 1575 DELAY(10); 1576 if (count++ >= timeout) 1577 break; 1578 } 1579 } 1580 1581 if (timeout && (count >= timeout)) { 1582 device_printf(ch->dev, "Poll timeout on slot %d port %d\n", 1583 slot->slot, port); 1584 device_printf(ch->dev, "is %08x cs %08x ss %08x " 1585 "rs %08x tfd %02x serr %08x cmd %08x\n", 1586 ATA_INL(ch->r_mem, AHCI_P_IS), 1587 ATA_INL(ch->r_mem, AHCI_P_CI), 1588 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1589 ATA_INL(ch->r_mem, AHCI_P_TFD), 1590 ATA_INL(ch->r_mem, AHCI_P_SERR), 1591 ATA_INL(ch->r_mem, AHCI_P_CMD)); 1592 et = AHCI_ERR_TIMEOUT; 1593 } 1594 1595 /* Kick controller into sane state and enable FBS. */ 1596 if (softreset == 2) 1597 ch->eslots |= (1 << slot->slot); 1598 ahci_end_transaction(slot, et); 1599 return; 1600 } 1601 /* Start command execution timeout */ 1602 callout_reset_sbt(&slot->timeout, SBT_1MS * ccb->ccb_h.timeout / 2, 1603 0, (timeout_t*)ahci_timeout, slot, 0); 1604 return; 1605 } 1606 1607 /* Must be called with channel locked. */ 1608 static void 1609 ahci_process_timeout(struct ahci_channel *ch) 1610 { 1611 int i; 1612 1613 mtx_assert(&ch->mtx, MA_OWNED); 1614 /* Handle the rest of commands. */ 1615 for (i = 0; i < ch->numslots; i++) { 1616 /* Do we have a running request on slot? */ 1617 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1618 continue; 1619 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT); 1620 } 1621 } 1622 1623 /* Must be called with channel locked. */ 1624 static void 1625 ahci_rearm_timeout(struct ahci_channel *ch) 1626 { 1627 int i; 1628 1629 mtx_assert(&ch->mtx, MA_OWNED); 1630 for (i = 0; i < ch->numslots; i++) { 1631 struct ahci_slot *slot = &ch->slot[i]; 1632 1633 /* Do we have a running request on slot? */ 1634 if (slot->state < AHCI_SLOT_RUNNING) 1635 continue; 1636 if ((ch->toslots & (1 << i)) == 0) 1637 continue; 1638 callout_reset_sbt(&slot->timeout, 1639 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0, 1640 (timeout_t*)ahci_timeout, slot, 0); 1641 } 1642 } 1643 1644 /* Locked by callout mechanism. */ 1645 static void 1646 ahci_timeout(struct ahci_slot *slot) 1647 { 1648 struct ahci_channel *ch = slot->ch; 1649 device_t dev = ch->dev; 1650 uint32_t sstatus; 1651 int ccs; 1652 int i; 1653 1654 /* Check for stale timeout. */ 1655 if (slot->state < AHCI_SLOT_RUNNING) 1656 return; 1657 1658 /* Check if slot was not being executed last time we checked. */ 1659 if (slot->state < AHCI_SLOT_EXECUTING) { 1660 /* Check if slot started executing. */ 1661 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT); 1662 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK) 1663 >> AHCI_P_CMD_CCS_SHIFT; 1664 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot || 1665 ch->fbs_enabled || ch->wrongccs) 1666 slot->state = AHCI_SLOT_EXECUTING; 1667 else if ((ch->rslots & (1 << ccs)) == 0) { 1668 ch->wrongccs = 1; 1669 slot->state = AHCI_SLOT_EXECUTING; 1670 } 1671 1672 callout_reset_sbt(&slot->timeout, 1673 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0, 1674 (timeout_t*)ahci_timeout, slot, 0); 1675 return; 1676 } 1677 1678 device_printf(dev, "Timeout on slot %d port %d\n", 1679 slot->slot, slot->ccb->ccb_h.target_id & 0x0f); 1680 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x " 1681 "serr %08x cmd %08x\n", 1682 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI), 1683 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots, 1684 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR), 1685 ATA_INL(ch->r_mem, AHCI_P_CMD)); 1686 1687 /* Handle frozen command. */ 1688 if (ch->frozen) { 1689 union ccb *fccb = ch->frozen; 1690 ch->frozen = NULL; 1691 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1692 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1693 xpt_freeze_devq(fccb->ccb_h.path, 1); 1694 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1695 } 1696 ahci_done(ch, fccb); 1697 } 1698 if (!ch->fbs_enabled && !ch->wrongccs) { 1699 /* Without FBS we know real timeout source. */ 1700 ch->fatalerr = 1; 1701 /* Handle command with timeout. */ 1702 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT); 1703 /* Handle the rest of commands. */ 1704 for (i = 0; i < ch->numslots; i++) { 1705 /* Do we have a running request on slot? */ 1706 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 1707 continue; 1708 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 1709 } 1710 } else { 1711 /* With FBS we wait for other commands timeout and pray. */ 1712 if (ch->toslots == 0) 1713 xpt_freeze_simq(ch->sim, 1); 1714 ch->toslots |= (1 << slot->slot); 1715 if ((ch->rslots & ~ch->toslots) == 0) 1716 ahci_process_timeout(ch); 1717 else 1718 device_printf(dev, " ... waiting for slots %08x\n", 1719 ch->rslots & ~ch->toslots); 1720 } 1721 } 1722 1723 /* Must be called with channel locked. */ 1724 static void 1725 ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et) 1726 { 1727 struct ahci_channel *ch = slot->ch; 1728 union ccb *ccb = slot->ccb; 1729 struct ahci_cmd_list *clp; 1730 int lastto; 1731 uint32_t sig; 1732 1733 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, 1734 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1735 clp = (struct ahci_cmd_list *) 1736 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot)); 1737 /* Read result registers to the result struct 1738 * May be incorrect if several commands finished same time, 1739 * so read only when sure or have to. 1740 */ 1741 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1742 struct ata_res *res = &ccb->ataio.res; 1743 1744 if ((et == AHCI_ERR_TFE) || 1745 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 1746 u_int8_t *fis = ch->dma.rfis + 0x40; 1747 1748 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map, 1749 BUS_DMASYNC_POSTREAD); 1750 if (ch->fbs_enabled) { 1751 fis += ccb->ccb_h.target_id * 256; 1752 res->status = fis[2]; 1753 res->error = fis[3]; 1754 } else { 1755 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD); 1756 1757 res->status = tfd; 1758 res->error = tfd >> 8; 1759 } 1760 res->lba_low = fis[4]; 1761 res->lba_mid = fis[5]; 1762 res->lba_high = fis[6]; 1763 res->device = fis[7]; 1764 res->lba_low_exp = fis[8]; 1765 res->lba_mid_exp = fis[9]; 1766 res->lba_high_exp = fis[10]; 1767 res->sector_count = fis[12]; 1768 res->sector_count_exp = fis[13]; 1769 1770 /* 1771 * Some weird controllers do not return signature in 1772 * FIS receive area. Read it from PxSIG register. 1773 */ 1774 if ((ch->quirks & AHCI_Q_ALTSIG) && 1775 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1776 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) { 1777 sig = ATA_INL(ch->r_mem, AHCI_P_SIG); 1778 res->lba_high = sig >> 24; 1779 res->lba_mid = sig >> 16; 1780 res->lba_low = sig >> 8; 1781 res->sector_count = sig; 1782 } 1783 } else 1784 bzero(res, sizeof(*res)); 1785 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 && 1786 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 1787 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 1788 ccb->ataio.resid = 1789 ccb->ataio.dxfer_len - le32toh(clp->bytecount); 1790 } 1791 } else { 1792 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 1793 (ch->quirks & AHCI_Q_NOCOUNT) == 0) { 1794 ccb->csio.resid = 1795 ccb->csio.dxfer_len - le32toh(clp->bytecount); 1796 } 1797 } 1798 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1799 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1800 (ccb->ccb_h.flags & CAM_DIR_IN) ? 1801 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1802 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 1803 } 1804 if (et != AHCI_ERR_NONE) 1805 ch->eslots |= (1 << slot->slot); 1806 /* In case of error, freeze device for proper recovery. */ 1807 if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) && 1808 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 1809 xpt_freeze_devq(ccb->ccb_h.path, 1); 1810 ccb->ccb_h.status |= CAM_DEV_QFRZN; 1811 } 1812 /* Set proper result status. */ 1813 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1814 switch (et) { 1815 case AHCI_ERR_NONE: 1816 ccb->ccb_h.status |= CAM_REQ_CMP; 1817 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 1818 ccb->csio.scsi_status = SCSI_STATUS_OK; 1819 break; 1820 case AHCI_ERR_INVALID: 1821 ch->fatalerr = 1; 1822 ccb->ccb_h.status |= CAM_REQ_INVALID; 1823 break; 1824 case AHCI_ERR_INNOCENT: 1825 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 1826 break; 1827 case AHCI_ERR_TFE: 1828 case AHCI_ERR_NCQ: 1829 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 1830 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 1831 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 1832 } else { 1833 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 1834 } 1835 break; 1836 case AHCI_ERR_SATA: 1837 ch->fatalerr = 1; 1838 if (!ch->recoverycmd) { 1839 xpt_freeze_simq(ch->sim, 1); 1840 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1841 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1842 } 1843 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 1844 break; 1845 case AHCI_ERR_TIMEOUT: 1846 if (!ch->recoverycmd) { 1847 xpt_freeze_simq(ch->sim, 1); 1848 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1849 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1850 } 1851 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 1852 break; 1853 default: 1854 ch->fatalerr = 1; 1855 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 1856 } 1857 /* Free slot. */ 1858 ch->oslots &= ~(1 << slot->slot); 1859 ch->rslots &= ~(1 << slot->slot); 1860 ch->aslots &= ~(1 << slot->slot); 1861 slot->state = AHCI_SLOT_EMPTY; 1862 slot->ccb = NULL; 1863 /* Update channel stats. */ 1864 ch->numrslots--; 1865 ch->numrslotspd[ccb->ccb_h.target_id]--; 1866 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1867 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1868 ch->numtslots--; 1869 ch->numtslotspd[ccb->ccb_h.target_id]--; 1870 } 1871 /* Cancel timeout state if request completed normally. */ 1872 if (et != AHCI_ERR_TIMEOUT) { 1873 lastto = (ch->toslots == (1 << slot->slot)); 1874 ch->toslots &= ~(1 << slot->slot); 1875 if (lastto) 1876 xpt_release_simq(ch->sim, TRUE); 1877 } 1878 /* If it was first request of reset sequence and there is no error, 1879 * proceed to second request. */ 1880 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1881 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) && 1882 (ccb->ataio.cmd.control & ATA_A_RESET) && 1883 et == AHCI_ERR_NONE) { 1884 ccb->ataio.cmd.control &= ~ATA_A_RESET; 1885 ahci_begin_transaction(ch, ccb); 1886 return; 1887 } 1888 /* If it was our READ LOG command - process it. */ 1889 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) { 1890 ahci_process_read_log(ch, ccb); 1891 /* If it was our REQUEST SENSE command - process it. */ 1892 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) { 1893 ahci_process_request_sense(ch, ccb); 1894 /* If it was NCQ or ATAPI command error, put result on hold. */ 1895 } else if (et == AHCI_ERR_NCQ || 1896 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR && 1897 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) { 1898 ch->hold[slot->slot] = ccb; 1899 ch->numhslots++; 1900 } else 1901 ahci_done(ch, ccb); 1902 /* If we have no other active commands, ... */ 1903 if (ch->rslots == 0) { 1904 /* if there was fatal error - reset port. */ 1905 if (ch->toslots != 0 || ch->fatalerr) { 1906 ahci_reset(ch); 1907 } else { 1908 /* if we have slots in error, we can reinit port. */ 1909 if (ch->eslots != 0) { 1910 ahci_stop(ch); 1911 ahci_clo(ch); 1912 ahci_start(ch, 1); 1913 } 1914 /* if there commands on hold, we can do READ LOG. */ 1915 if (!ch->recoverycmd && ch->numhslots) 1916 ahci_issue_recovery(ch); 1917 } 1918 /* If all the rest of commands are in timeout - give them chance. */ 1919 } else if ((ch->rslots & ~ch->toslots) == 0 && 1920 et != AHCI_ERR_TIMEOUT) 1921 ahci_rearm_timeout(ch); 1922 /* Unfreeze frozen command. */ 1923 if (ch->frozen && !ahci_check_collision(ch, ch->frozen)) { 1924 union ccb *fccb = ch->frozen; 1925 ch->frozen = NULL; 1926 ahci_begin_transaction(ch, fccb); 1927 xpt_release_simq(ch->sim, TRUE); 1928 } 1929 /* Start PM timer. */ 1930 if (ch->numrslots == 0 && ch->pm_level > 3 && 1931 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) { 1932 callout_schedule(&ch->pm_timer, 1933 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 1934 } 1935 } 1936 1937 static void 1938 ahci_issue_recovery(struct ahci_channel *ch) 1939 { 1940 union ccb *ccb; 1941 struct ccb_ataio *ataio; 1942 struct ccb_scsiio *csio; 1943 int i; 1944 1945 /* Find some held command. */ 1946 for (i = 0; i < ch->numslots; i++) { 1947 if (ch->hold[i]) 1948 break; 1949 } 1950 ccb = xpt_alloc_ccb_nowait(); 1951 if (ccb == NULL) { 1952 device_printf(ch->dev, "Unable to allocate recovery command\n"); 1953 completeall: 1954 /* We can't do anything -- complete held commands. */ 1955 for (i = 0; i < ch->numslots; i++) { 1956 if (ch->hold[i] == NULL) 1957 continue; 1958 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 1959 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL; 1960 ahci_done(ch, ch->hold[i]); 1961 ch->hold[i] = NULL; 1962 ch->numhslots--; 1963 } 1964 ahci_reset(ch); 1965 return; 1966 } 1967 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 1968 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1969 /* READ LOG */ 1970 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG; 1971 ccb->ccb_h.func_code = XPT_ATA_IO; 1972 ccb->ccb_h.flags = CAM_DIR_IN; 1973 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 1974 ataio = &ccb->ataio; 1975 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT); 1976 if (ataio->data_ptr == NULL) { 1977 xpt_free_ccb(ccb); 1978 device_printf(ch->dev, 1979 "Unable to allocate memory for READ LOG command\n"); 1980 goto completeall; 1981 } 1982 ataio->dxfer_len = 512; 1983 bzero(&ataio->cmd, sizeof(ataio->cmd)); 1984 ataio->cmd.flags = CAM_ATAIO_48BIT; 1985 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 1986 ataio->cmd.sector_count = 1; 1987 ataio->cmd.sector_count_exp = 0; 1988 ataio->cmd.lba_low = 0x10; 1989 ataio->cmd.lba_mid = 0; 1990 ataio->cmd.lba_mid_exp = 0; 1991 } else { 1992 /* REQUEST SENSE */ 1993 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE; 1994 ccb->ccb_h.recovery_slot = i; 1995 ccb->ccb_h.func_code = XPT_SCSI_IO; 1996 ccb->ccb_h.flags = CAM_DIR_IN; 1997 ccb->ccb_h.status = 0; 1998 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 1999 csio = &ccb->csio; 2000 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data; 2001 csio->dxfer_len = ch->hold[i]->csio.sense_len; 2002 csio->cdb_len = 6; 2003 bzero(&csio->cdb_io, sizeof(csio->cdb_io)); 2004 csio->cdb_io.cdb_bytes[0] = 0x03; 2005 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len; 2006 } 2007 /* Freeze SIM while doing recovery. */ 2008 ch->recoverycmd = 1; 2009 xpt_freeze_simq(ch->sim, 1); 2010 ahci_begin_transaction(ch, ccb); 2011 } 2012 2013 static void 2014 ahci_process_read_log(struct ahci_channel *ch, union ccb *ccb) 2015 { 2016 uint8_t *data; 2017 struct ata_res *res; 2018 int i; 2019 2020 ch->recoverycmd = 0; 2021 2022 data = ccb->ataio.data_ptr; 2023 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 2024 (data[0] & 0x80) == 0) { 2025 for (i = 0; i < ch->numslots; i++) { 2026 if (!ch->hold[i]) 2027 continue; 2028 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2029 continue; 2030 if ((data[0] & 0x1F) == i) { 2031 res = &ch->hold[i]->ataio.res; 2032 res->status = data[2]; 2033 res->error = data[3]; 2034 res->lba_low = data[4]; 2035 res->lba_mid = data[5]; 2036 res->lba_high = data[6]; 2037 res->device = data[7]; 2038 res->lba_low_exp = data[8]; 2039 res->lba_mid_exp = data[9]; 2040 res->lba_high_exp = data[10]; 2041 res->sector_count = data[12]; 2042 res->sector_count_exp = data[13]; 2043 } else { 2044 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2045 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 2046 } 2047 ahci_done(ch, ch->hold[i]); 2048 ch->hold[i] = NULL; 2049 ch->numhslots--; 2050 } 2051 } else { 2052 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 2053 device_printf(ch->dev, "Error while READ LOG EXT\n"); 2054 else if ((data[0] & 0x80) == 0) { 2055 device_printf(ch->dev, "Non-queued command error in READ LOG EXT\n"); 2056 } 2057 for (i = 0; i < ch->numslots; i++) { 2058 if (!ch->hold[i]) 2059 continue; 2060 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO) 2061 continue; 2062 ahci_done(ch, ch->hold[i]); 2063 ch->hold[i] = NULL; 2064 ch->numhslots--; 2065 } 2066 } 2067 free(ccb->ataio.data_ptr, M_AHCI); 2068 xpt_free_ccb(ccb); 2069 xpt_release_simq(ch->sim, TRUE); 2070 } 2071 2072 static void 2073 ahci_process_request_sense(struct ahci_channel *ch, union ccb *ccb) 2074 { 2075 int i; 2076 2077 ch->recoverycmd = 0; 2078 2079 i = ccb->ccb_h.recovery_slot; 2080 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) { 2081 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID; 2082 } else { 2083 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 2084 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL; 2085 } 2086 ahci_done(ch, ch->hold[i]); 2087 ch->hold[i] = NULL; 2088 ch->numhslots--; 2089 xpt_free_ccb(ccb); 2090 xpt_release_simq(ch->sim, TRUE); 2091 } 2092 2093 static void 2094 ahci_start(struct ahci_channel *ch, int fbs) 2095 { 2096 u_int32_t cmd; 2097 2098 /* Clear SATA error register */ 2099 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF); 2100 /* Clear any interrupts pending on this channel */ 2101 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF); 2102 /* Configure FIS-based switching if supported. */ 2103 if (ch->chcaps & AHCI_P_CMD_FBSCP) { 2104 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0; 2105 ATA_OUTL(ch->r_mem, AHCI_P_FBS, 2106 ch->fbs_enabled ? AHCI_P_FBS_EN : 0); 2107 } 2108 /* Start operations on this channel */ 2109 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2110 cmd &= ~AHCI_P_CMD_PMA; 2111 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST | 2112 (ch->pm_present ? AHCI_P_CMD_PMA : 0)); 2113 } 2114 2115 static void 2116 ahci_stop(struct ahci_channel *ch) 2117 { 2118 u_int32_t cmd; 2119 int timeout; 2120 2121 /* Kill all activity on this channel */ 2122 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2123 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST); 2124 /* Wait for activity stop. */ 2125 timeout = 0; 2126 do { 2127 DELAY(10); 2128 if (timeout++ > 50000) { 2129 device_printf(ch->dev, "stopping AHCI engine failed\n"); 2130 break; 2131 } 2132 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR); 2133 ch->eslots = 0; 2134 } 2135 2136 static void 2137 ahci_clo(struct ahci_channel *ch) 2138 { 2139 u_int32_t cmd; 2140 int timeout; 2141 2142 /* Issue Command List Override if supported */ 2143 if (ch->caps & AHCI_CAP_SCLO) { 2144 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2145 cmd |= AHCI_P_CMD_CLO; 2146 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd); 2147 timeout = 0; 2148 do { 2149 DELAY(10); 2150 if (timeout++ > 50000) { 2151 device_printf(ch->dev, "executing CLO failed\n"); 2152 break; 2153 } 2154 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO); 2155 } 2156 } 2157 2158 static void 2159 ahci_stop_fr(struct ahci_channel *ch) 2160 { 2161 u_int32_t cmd; 2162 int timeout; 2163 2164 /* Kill all FIS reception on this channel */ 2165 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2166 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE); 2167 /* Wait for FIS reception stop. */ 2168 timeout = 0; 2169 do { 2170 DELAY(10); 2171 if (timeout++ > 50000) { 2172 device_printf(ch->dev, "stopping AHCI FR engine failed\n"); 2173 break; 2174 } 2175 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR); 2176 } 2177 2178 static void 2179 ahci_start_fr(struct ahci_channel *ch) 2180 { 2181 u_int32_t cmd; 2182 2183 /* Start FIS reception on this channel */ 2184 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD); 2185 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE); 2186 } 2187 2188 static int 2189 ahci_wait_ready(struct ahci_channel *ch, int t, int t0) 2190 { 2191 int timeout = 0; 2192 uint32_t val; 2193 2194 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) & 2195 (ATA_S_BUSY | ATA_S_DRQ)) { 2196 if (timeout > t) { 2197 if (t != 0) { 2198 device_printf(ch->dev, 2199 "AHCI reset: device not ready after %dms " 2200 "(tfd = %08x)\n", 2201 MAX(t, 0) + t0, val); 2202 } 2203 return (EBUSY); 2204 } 2205 DELAY(1000); 2206 timeout++; 2207 } 2208 if (bootverbose) 2209 device_printf(ch->dev, "AHCI reset: device ready after %dms\n", 2210 timeout + t0); 2211 return (0); 2212 } 2213 2214 static void 2215 ahci_reset_to(void *arg) 2216 { 2217 struct ahci_channel *ch = arg; 2218 2219 if (ch->resetting == 0) 2220 return; 2221 ch->resetting--; 2222 if (ahci_wait_ready(ch, ch->resetting == 0 ? -1 : 0, 2223 (310 - ch->resetting) * 100) == 0) { 2224 ch->resetting = 0; 2225 ahci_start(ch, 1); 2226 xpt_release_simq(ch->sim, TRUE); 2227 return; 2228 } 2229 if (ch->resetting == 0) { 2230 ahci_clo(ch); 2231 ahci_start(ch, 1); 2232 xpt_release_simq(ch->sim, TRUE); 2233 return; 2234 } 2235 callout_schedule(&ch->reset_timer, hz / 10); 2236 } 2237 2238 static void 2239 ahci_reset(struct ahci_channel *ch) 2240 { 2241 struct ahci_controller *ctlr = device_get_softc(device_get_parent(ch->dev)); 2242 int i; 2243 2244 xpt_freeze_simq(ch->sim, 1); 2245 if (bootverbose) 2246 device_printf(ch->dev, "AHCI reset...\n"); 2247 /* Forget about previous reset. */ 2248 if (ch->resetting) { 2249 ch->resetting = 0; 2250 callout_stop(&ch->reset_timer); 2251 xpt_release_simq(ch->sim, TRUE); 2252 } 2253 /* Requeue freezed command. */ 2254 if (ch->frozen) { 2255 union ccb *fccb = ch->frozen; 2256 ch->frozen = NULL; 2257 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 2258 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 2259 xpt_freeze_devq(fccb->ccb_h.path, 1); 2260 fccb->ccb_h.status |= CAM_DEV_QFRZN; 2261 } 2262 ahci_done(ch, fccb); 2263 } 2264 /* Kill the engine and requeue all running commands. */ 2265 ahci_stop(ch); 2266 for (i = 0; i < ch->numslots; i++) { 2267 /* Do we have a running request on slot? */ 2268 if (ch->slot[i].state < AHCI_SLOT_RUNNING) 2269 continue; 2270 /* XXX; Commands in loading state. */ 2271 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT); 2272 } 2273 for (i = 0; i < ch->numslots; i++) { 2274 if (!ch->hold[i]) 2275 continue; 2276 ahci_done(ch, ch->hold[i]); 2277 ch->hold[i] = NULL; 2278 ch->numhslots--; 2279 } 2280 if (ch->toslots != 0) 2281 xpt_release_simq(ch->sim, TRUE); 2282 ch->eslots = 0; 2283 ch->toslots = 0; 2284 ch->wrongccs = 0; 2285 ch->fatalerr = 0; 2286 /* Tell the XPT about the event */ 2287 xpt_async(AC_BUS_RESET, ch->path, NULL); 2288 /* Disable port interrupts */ 2289 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0); 2290 /* Reset and reconnect PHY, */ 2291 if (!ahci_sata_phy_reset(ch)) { 2292 if (bootverbose) 2293 device_printf(ch->dev, 2294 "AHCI reset: device not found\n"); 2295 ch->devices = 0; 2296 /* Enable wanted port interrupts */ 2297 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2298 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2299 AHCI_P_IX_PRC | AHCI_P_IX_PC)); 2300 xpt_release_simq(ch->sim, TRUE); 2301 return; 2302 } 2303 if (bootverbose) 2304 device_printf(ch->dev, "AHCI reset: device found\n"); 2305 /* Wait for clearing busy status. */ 2306 if (ahci_wait_ready(ch, dumping ? 31000 : 0, 0)) { 2307 if (dumping) 2308 ahci_clo(ch); 2309 else 2310 ch->resetting = 310; 2311 } 2312 ch->devices = 1; 2313 /* Enable wanted port interrupts */ 2314 ATA_OUTL(ch->r_mem, AHCI_P_IE, 2315 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) | 2316 AHCI_P_IX_TFE | AHCI_P_IX_HBF | 2317 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF | 2318 ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC | 2319 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) | 2320 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR))); 2321 if (ch->resetting) 2322 callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, ch); 2323 else { 2324 ahci_start(ch, 1); 2325 xpt_release_simq(ch->sim, TRUE); 2326 } 2327 } 2328 2329 static int 2330 ahci_setup_fis(struct ahci_channel *ch, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag) 2331 { 2332 u_int8_t *fis = &ctp->cfis[0]; 2333 2334 bzero(fis, 20); 2335 fis[0] = 0x27; /* host to device */ 2336 fis[1] = (ccb->ccb_h.target_id & 0x0f); 2337 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 2338 fis[1] |= 0x80; 2339 fis[2] = ATA_PACKET_CMD; 2340 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 2341 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA) 2342 fis[3] = ATA_F_DMA; 2343 else { 2344 fis[5] = ccb->csio.dxfer_len; 2345 fis[6] = ccb->csio.dxfer_len >> 8; 2346 } 2347 fis[7] = ATA_D_LBA; 2348 fis[15] = ATA_A_4BIT; 2349 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 2350 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes, 2351 ctp->acmd, ccb->csio.cdb_len); 2352 bzero(ctp->acmd + ccb->csio.cdb_len, 32 - ccb->csio.cdb_len); 2353 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) { 2354 fis[1] |= 0x80; 2355 fis[2] = ccb->ataio.cmd.command; 2356 fis[3] = ccb->ataio.cmd.features; 2357 fis[4] = ccb->ataio.cmd.lba_low; 2358 fis[5] = ccb->ataio.cmd.lba_mid; 2359 fis[6] = ccb->ataio.cmd.lba_high; 2360 fis[7] = ccb->ataio.cmd.device; 2361 fis[8] = ccb->ataio.cmd.lba_low_exp; 2362 fis[9] = ccb->ataio.cmd.lba_mid_exp; 2363 fis[10] = ccb->ataio.cmd.lba_high_exp; 2364 fis[11] = ccb->ataio.cmd.features_exp; 2365 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 2366 fis[12] = tag << 3; 2367 fis[13] = 0; 2368 } else { 2369 fis[12] = ccb->ataio.cmd.sector_count; 2370 fis[13] = ccb->ataio.cmd.sector_count_exp; 2371 } 2372 fis[15] = ATA_A_4BIT; 2373 } else { 2374 fis[15] = ccb->ataio.cmd.control; 2375 } 2376 return (20); 2377 } 2378 2379 static int 2380 ahci_sata_connect(struct ahci_channel *ch) 2381 { 2382 u_int32_t status; 2383 int timeout, found = 0; 2384 2385 /* Wait up to 100ms for "connect well" */ 2386 for (timeout = 0; timeout < 1000 ; timeout++) { 2387 status = ATA_INL(ch->r_mem, AHCI_P_SSTS); 2388 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE) 2389 found = 1; 2390 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) && 2391 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) && 2392 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) 2393 break; 2394 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) { 2395 if (bootverbose) { 2396 device_printf(ch->dev, "SATA offline status=%08x\n", 2397 status); 2398 } 2399 return (0); 2400 } 2401 if (found == 0 && timeout >= 100) 2402 break; 2403 DELAY(100); 2404 } 2405 if (timeout >= 1000 || !found) { 2406 if (bootverbose) { 2407 device_printf(ch->dev, 2408 "SATA connect timeout time=%dus status=%08x\n", 2409 timeout * 100, status); 2410 } 2411 return (0); 2412 } 2413 if (bootverbose) { 2414 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n", 2415 timeout * 100, status); 2416 } 2417 /* Clear SATA error register */ 2418 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff); 2419 return (1); 2420 } 2421 2422 static int 2423 ahci_sata_phy_reset(struct ahci_channel *ch) 2424 { 2425 int sata_rev; 2426 uint32_t val; 2427 2428 if (ch->listening) { 2429 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2430 val |= AHCI_P_CMD_SUD; 2431 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2432 ch->listening = 0; 2433 } 2434 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 2435 if (sata_rev == 1) 2436 val = ATA_SC_SPD_SPEED_GEN1; 2437 else if (sata_rev == 2) 2438 val = ATA_SC_SPD_SPEED_GEN2; 2439 else if (sata_rev == 3) 2440 val = ATA_SC_SPD_SPEED_GEN3; 2441 else 2442 val = 0; 2443 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2444 ATA_SC_DET_RESET | val | 2445 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER); 2446 DELAY(1000); 2447 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 2448 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 2449 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER))); 2450 if (!ahci_sata_connect(ch)) { 2451 if (ch->caps & AHCI_CAP_SSS) { 2452 val = ATA_INL(ch->r_mem, AHCI_P_CMD); 2453 val &= ~AHCI_P_CMD_SUD; 2454 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val); 2455 ch->listening = 1; 2456 } else if (ch->pm_level > 0) 2457 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE); 2458 return (0); 2459 } 2460 return (1); 2461 } 2462 2463 static int 2464 ahci_check_ids(struct ahci_channel *ch, union ccb *ccb) 2465 { 2466 2467 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) { 2468 ccb->ccb_h.status = CAM_TID_INVALID; 2469 ahci_done(ch, ccb); 2470 return (-1); 2471 } 2472 if (ccb->ccb_h.target_lun != 0) { 2473 ccb->ccb_h.status = CAM_LUN_INVALID; 2474 ahci_done(ch, ccb); 2475 return (-1); 2476 } 2477 return (0); 2478 } 2479 2480 static void 2481 ahciaction(struct cam_sim *sim, union ccb *ccb) 2482 { 2483 struct ahci_channel *ch; 2484 2485 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n", 2486 ccb->ccb_h.func_code)); 2487 2488 ch = (struct ahci_channel *)cam_sim_softc(sim); 2489 switch (ccb->ccb_h.func_code) { 2490 /* Common cases first */ 2491 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2492 case XPT_SCSI_IO: 2493 if (ahci_check_ids(ch, ccb)) 2494 return; 2495 if (ch->devices == 0 || 2496 (ch->pm_present == 0 && 2497 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) { 2498 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2499 break; 2500 } 2501 ccb->ccb_h.recovery_type = RECOVERY_NONE; 2502 /* Check for command collision. */ 2503 if (ahci_check_collision(ch, ccb)) { 2504 /* Freeze command. */ 2505 ch->frozen = ccb; 2506 /* We have only one frozen slot, so freeze simq also. */ 2507 xpt_freeze_simq(ch->sim, 1); 2508 return; 2509 } 2510 ahci_begin_transaction(ch, ccb); 2511 return; 2512 case XPT_EN_LUN: /* Enable LUN as a target */ 2513 case XPT_TARGET_IO: /* Execute target I/O request */ 2514 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2515 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2516 case XPT_ABORT: /* Abort the specified CCB */ 2517 /* XXX Implement */ 2518 ccb->ccb_h.status = CAM_REQ_INVALID; 2519 break; 2520 case XPT_SET_TRAN_SETTINGS: 2521 { 2522 struct ccb_trans_settings *cts = &ccb->cts; 2523 struct ahci_device *d; 2524 2525 if (ahci_check_ids(ch, ccb)) 2526 return; 2527 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2528 d = &ch->curr[ccb->ccb_h.target_id]; 2529 else 2530 d = &ch->user[ccb->ccb_h.target_id]; 2531 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2532 d->revision = cts->xport_specific.sata.revision; 2533 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2534 d->mode = cts->xport_specific.sata.mode; 2535 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) 2536 d->bytecount = min(8192, cts->xport_specific.sata.bytecount); 2537 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2538 d->tags = min(ch->numslots, cts->xport_specific.sata.tags); 2539 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2540 ch->pm_present = cts->xport_specific.sata.pm_present; 2541 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 2542 d->atapi = cts->xport_specific.sata.atapi; 2543 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 2544 d->caps = cts->xport_specific.sata.caps; 2545 ccb->ccb_h.status = CAM_REQ_CMP; 2546 break; 2547 } 2548 case XPT_GET_TRAN_SETTINGS: 2549 /* Get default/user set transfer settings for the target */ 2550 { 2551 struct ccb_trans_settings *cts = &ccb->cts; 2552 struct ahci_device *d; 2553 uint32_t status; 2554 2555 if (ahci_check_ids(ch, ccb)) 2556 return; 2557 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2558 d = &ch->curr[ccb->ccb_h.target_id]; 2559 else 2560 d = &ch->user[ccb->ccb_h.target_id]; 2561 cts->protocol = PROTO_UNSPECIFIED; 2562 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2563 cts->transport = XPORT_SATA; 2564 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2565 cts->proto_specific.valid = 0; 2566 cts->xport_specific.sata.valid = 0; 2567 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 2568 (ccb->ccb_h.target_id == 15 || 2569 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 2570 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK; 2571 if (status & 0x0f0) { 2572 cts->xport_specific.sata.revision = 2573 (status & 0x0f0) >> 4; 2574 cts->xport_specific.sata.valid |= 2575 CTS_SATA_VALID_REVISION; 2576 } 2577 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D; 2578 if (ch->pm_level) { 2579 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC)) 2580 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ; 2581 if (ch->caps2 & AHCI_CAP2_APST) 2582 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST; 2583 } 2584 if ((ch->caps & AHCI_CAP_SNCQ) && 2585 (ch->quirks & AHCI_Q_NOAA) == 0) 2586 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA; 2587 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN; 2588 cts->xport_specific.sata.caps &= 2589 ch->user[ccb->ccb_h.target_id].caps; 2590 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2591 } else { 2592 cts->xport_specific.sata.revision = d->revision; 2593 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 2594 cts->xport_specific.sata.caps = d->caps; 2595 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2596 } 2597 cts->xport_specific.sata.mode = d->mode; 2598 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 2599 cts->xport_specific.sata.bytecount = d->bytecount; 2600 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 2601 cts->xport_specific.sata.pm_present = ch->pm_present; 2602 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 2603 cts->xport_specific.sata.tags = d->tags; 2604 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 2605 cts->xport_specific.sata.atapi = d->atapi; 2606 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 2607 ccb->ccb_h.status = CAM_REQ_CMP; 2608 break; 2609 } 2610 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 2611 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2612 ahci_reset(ch); 2613 ccb->ccb_h.status = CAM_REQ_CMP; 2614 break; 2615 case XPT_TERM_IO: /* Terminate the I/O process */ 2616 /* XXX Implement */ 2617 ccb->ccb_h.status = CAM_REQ_INVALID; 2618 break; 2619 case XPT_PATH_INQ: /* Path routing inquiry */ 2620 { 2621 struct ccb_pathinq *cpi = &ccb->cpi; 2622 2623 cpi->version_num = 1; /* XXX??? */ 2624 cpi->hba_inquiry = PI_SDTR_ABLE; 2625 if (ch->caps & AHCI_CAP_SNCQ) 2626 cpi->hba_inquiry |= PI_TAG_ABLE; 2627 if (ch->caps & AHCI_CAP_SPM) 2628 cpi->hba_inquiry |= PI_SATAPM; 2629 cpi->target_sprt = 0; 2630 cpi->hba_misc = PIM_SEQSCAN | PIM_UNMAPPED; 2631 cpi->hba_eng_cnt = 0; 2632 if (ch->caps & AHCI_CAP_SPM) 2633 cpi->max_target = 15; 2634 else 2635 cpi->max_target = 0; 2636 cpi->max_lun = 0; 2637 cpi->initiator_id = 0; 2638 cpi->bus_id = cam_sim_bus(sim); 2639 cpi->base_transfer_speed = 150000; 2640 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2641 strlcpy(cpi->hba_vid, "AHCI", HBA_IDLEN); 2642 strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2643 cpi->unit_number = cam_sim_unit(sim); 2644 cpi->transport = XPORT_SATA; 2645 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 2646 cpi->protocol = PROTO_ATA; 2647 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 2648 cpi->maxio = MAXPHYS; 2649 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */ 2650 if (ch->quirks & AHCI_Q_MAXIO_64K) 2651 cpi->maxio = min(cpi->maxio, 128 * 512); 2652 cpi->hba_vendor = ch->vendorid; 2653 cpi->hba_device = ch->deviceid; 2654 cpi->hba_subvendor = ch->subvendorid; 2655 cpi->hba_subdevice = ch->subdeviceid; 2656 cpi->ccb_h.status = CAM_REQ_CMP; 2657 break; 2658 } 2659 default: 2660 ccb->ccb_h.status = CAM_REQ_INVALID; 2661 break; 2662 } 2663 ahci_done(ch, ccb); 2664 } 2665 2666 static void 2667 ahcipoll(struct cam_sim *sim) 2668 { 2669 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim); 2670 uint32_t istatus; 2671 2672 /* Read interrupt statuses and process if any. */ 2673 istatus = ATA_INL(ch->r_mem, AHCI_P_IS); 2674 if (istatus != 0) 2675 ahci_ch_intr_main(ch, istatus); 2676 if (ch->resetting != 0 && 2677 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) { 2678 ch->resetpolldiv = 1000; 2679 ahci_reset_to(ch); 2680 } 2681 } 2682 MODULE_VERSION(ahci, 1); 2683 MODULE_DEPEND(ahci, cam, 1, 1, 1);
Cache object: ab9fbf995e2c401fea04c8cf0fb05031
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