FreeBSD/Linux Kernel Cross Reference
sys/dev/ahci/ahci.c
1 /*-
2 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD: releng/11.2/sys/dev/ahci/ahci.c 331722 2018-03-29 02:50:57Z eadler $");
29
30 #include <sys/param.h>
31 #include <sys/module.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/bus.h>
35 #include <sys/conf.h>
36 #include <sys/endian.h>
37 #include <sys/malloc.h>
38 #include <sys/lock.h>
39 #include <sys/mutex.h>
40 #include <machine/stdarg.h>
41 #include <machine/resource.h>
42 #include <machine/bus.h>
43 #include <sys/rman.h>
44 #include "ahci.h"
45
46 #include <cam/cam.h>
47 #include <cam/cam_ccb.h>
48 #include <cam/cam_sim.h>
49 #include <cam/cam_xpt_sim.h>
50 #include <cam/cam_debug.h>
51
52 /* local prototypes */
53 static void ahci_intr(void *data);
54 static void ahci_intr_one(void *data);
55 static void ahci_intr_one_edge(void *data);
56 static int ahci_ch_init(device_t dev);
57 static int ahci_ch_deinit(device_t dev);
58 static int ahci_ch_suspend(device_t dev);
59 static int ahci_ch_resume(device_t dev);
60 static void ahci_ch_pm(void *arg);
61 static void ahci_ch_intr(void *arg);
62 static void ahci_ch_intr_direct(void *arg);
63 static void ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus);
64 static void ahci_begin_transaction(struct ahci_channel *ch, union ccb *ccb);
65 static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error);
66 static void ahci_execute_transaction(struct ahci_slot *slot);
67 static void ahci_timeout(struct ahci_slot *slot);
68 static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et);
69 static int ahci_setup_fis(struct ahci_channel *ch, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag);
70 static void ahci_dmainit(device_t dev);
71 static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
72 static void ahci_dmafini(device_t dev);
73 static void ahci_slotsalloc(device_t dev);
74 static void ahci_slotsfree(device_t dev);
75 static void ahci_reset(struct ahci_channel *ch);
76 static void ahci_start(struct ahci_channel *ch, int fbs);
77 static void ahci_stop(struct ahci_channel *ch);
78 static void ahci_clo(struct ahci_channel *ch);
79 static void ahci_start_fr(struct ahci_channel *ch);
80 static void ahci_stop_fr(struct ahci_channel *ch);
81
82 static int ahci_sata_connect(struct ahci_channel *ch);
83 static int ahci_sata_phy_reset(struct ahci_channel *ch);
84 static int ahci_wait_ready(struct ahci_channel *ch, int t, int t0);
85
86 static void ahci_issue_recovery(struct ahci_channel *ch);
87 static void ahci_process_read_log(struct ahci_channel *ch, union ccb *ccb);
88 static void ahci_process_request_sense(struct ahci_channel *ch, union ccb *ccb);
89
90 static void ahciaction(struct cam_sim *sim, union ccb *ccb);
91 static void ahcipoll(struct cam_sim *sim);
92
93 static MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers");
94
95 #define recovery_type spriv_field0
96 #define RECOVERY_NONE 0
97 #define RECOVERY_READ_LOG 1
98 #define RECOVERY_REQUEST_SENSE 2
99 #define recovery_slot spriv_field1
100
101 int
102 ahci_ctlr_setup(device_t dev)
103 {
104 struct ahci_controller *ctlr = device_get_softc(dev);
105 /* Clear interrupts */
106 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS));
107 /* Configure CCC */
108 if (ctlr->ccc) {
109 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI));
110 ATA_OUTL(ctlr->r_mem, AHCI_CCCC,
111 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) |
112 (4 << AHCI_CCCC_CC_SHIFT) |
113 AHCI_CCCC_EN);
114 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) &
115 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT;
116 if (bootverbose) {
117 device_printf(dev,
118 "CCC with %dms/4cmd enabled on vector %d\n",
119 ctlr->ccc, ctlr->cccv);
120 }
121 }
122 /* Enable AHCI interrupts */
123 ATA_OUTL(ctlr->r_mem, AHCI_GHC,
124 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE);
125 return (0);
126 }
127
128 int
129 ahci_ctlr_reset(device_t dev)
130 {
131 struct ahci_controller *ctlr = device_get_softc(dev);
132 int timeout;
133
134 /* Enable AHCI mode */
135 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
136 /* Reset AHCI controller */
137 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR);
138 for (timeout = 1000; timeout > 0; timeout--) {
139 DELAY(1000);
140 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0)
141 break;
142 }
143 if (timeout == 0) {
144 device_printf(dev, "AHCI controller reset failure\n");
145 return (ENXIO);
146 }
147 /* Reenable AHCI mode */
148 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
149
150 if (ctlr->quirks & AHCI_Q_RESTORE_CAP) {
151 /*
152 * Restore capability field.
153 * This is write to a read-only register to restore its state.
154 * On fully standard-compliant hardware this is not needed and
155 * this operation shall not take place. See ahci_pci.c for
156 * platforms using this quirk.
157 */
158 ATA_OUTL(ctlr->r_mem, AHCI_CAP, ctlr->caps);
159 }
160
161 return (0);
162 }
163
164
165 int
166 ahci_attach(device_t dev)
167 {
168 struct ahci_controller *ctlr = device_get_softc(dev);
169 int error, i, speed, unit;
170 uint32_t u, version;
171 device_t child;
172
173 ctlr->dev = dev;
174 ctlr->ccc = 0;
175 resource_int_value(device_get_name(dev),
176 device_get_unit(dev), "ccc", &ctlr->ccc);
177
178 /* Setup our own memory management for channels. */
179 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem);
180 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem);
181 ctlr->sc_iomem.rm_type = RMAN_ARRAY;
182 ctlr->sc_iomem.rm_descr = "I/O memory addresses";
183 if ((error = rman_init(&ctlr->sc_iomem)) != 0) {
184 ahci_free_mem(dev);
185 return (error);
186 }
187 if ((error = rman_manage_region(&ctlr->sc_iomem,
188 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) {
189 ahci_free_mem(dev);
190 rman_fini(&ctlr->sc_iomem);
191 return (error);
192 }
193 /* Get the HW capabilities */
194 version = ATA_INL(ctlr->r_mem, AHCI_VS);
195 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP);
196 if (version >= 0x00010200)
197 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2);
198 if (ctlr->caps & AHCI_CAP_EMS)
199 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL);
200
201 if (ctlr->quirks & AHCI_Q_FORCE_PI) {
202 /*
203 * Enable ports.
204 * The spec says that BIOS sets up bits corresponding to
205 * available ports. On platforms where this information
206 * is missing, the driver can define available ports on its own.
207 */
208 int nports = (ctlr->caps & AHCI_CAP_NPMASK) + 1;
209 int nmask = (1 << nports) - 1;
210
211 ATA_OUTL(ctlr->r_mem, AHCI_PI, nmask);
212 device_printf(dev, "Forcing PI to %d ports (mask = %x)\n",
213 nports, nmask);
214 }
215
216 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI);
217
218 /* Identify and set separate quirks for HBA and RAID f/w Marvells. */
219 if ((ctlr->quirks & AHCI_Q_ALTSIG) &&
220 (ctlr->caps & AHCI_CAP_SPM) == 0)
221 ctlr->quirks |= AHCI_Q_NOBSYRES;
222
223 if (ctlr->quirks & AHCI_Q_1CH) {
224 ctlr->caps &= ~AHCI_CAP_NPMASK;
225 ctlr->ichannels &= 0x01;
226 }
227 if (ctlr->quirks & AHCI_Q_2CH) {
228 ctlr->caps &= ~AHCI_CAP_NPMASK;
229 ctlr->caps |= 1;
230 ctlr->ichannels &= 0x03;
231 }
232 if (ctlr->quirks & AHCI_Q_4CH) {
233 ctlr->caps &= ~AHCI_CAP_NPMASK;
234 ctlr->caps |= 3;
235 ctlr->ichannels &= 0x0f;
236 }
237 ctlr->channels = MAX(flsl(ctlr->ichannels),
238 (ctlr->caps & AHCI_CAP_NPMASK) + 1);
239 if (ctlr->quirks & AHCI_Q_NOPMP)
240 ctlr->caps &= ~AHCI_CAP_SPM;
241 if (ctlr->quirks & AHCI_Q_NONCQ)
242 ctlr->caps &= ~AHCI_CAP_SNCQ;
243 if ((ctlr->caps & AHCI_CAP_CCCS) == 0)
244 ctlr->ccc = 0;
245 ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC);
246
247 /* Create controller-wide DMA tag. */
248 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
249 (ctlr->caps & AHCI_CAP_64BIT) ? BUS_SPACE_MAXADDR :
250 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
251 BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE,
252 0, NULL, NULL, &ctlr->dma_tag)) {
253 ahci_free_mem(dev);
254 rman_fini(&ctlr->sc_iomem);
255 return (ENXIO);
256 }
257
258 ahci_ctlr_setup(dev);
259
260 /* Setup interrupts. */
261 if ((error = ahci_setup_interrupt(dev)) != 0) {
262 bus_dma_tag_destroy(ctlr->dma_tag);
263 ahci_free_mem(dev);
264 rman_fini(&ctlr->sc_iomem);
265 return (error);
266 }
267
268 i = 0;
269 for (u = ctlr->ichannels; u != 0; u >>= 1)
270 i += (u & 1);
271 ctlr->direct = (ctlr->msi && (ctlr->numirqs > 1 || i <= 3));
272 resource_int_value(device_get_name(dev), device_get_unit(dev),
273 "direct", &ctlr->direct);
274 /* Announce HW capabilities. */
275 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT;
276 device_printf(dev,
277 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n",
278 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f),
279 ((version >> 4) & 0xf0) + (version & 0x0f),
280 (ctlr->caps & AHCI_CAP_NPMASK) + 1,
281 ((speed == 1) ? "1.5":((speed == 2) ? "3":
282 ((speed == 3) ? "6":"?"))),
283 (ctlr->caps & AHCI_CAP_SPM) ?
284 "supported" : "not supported",
285 (ctlr->caps & AHCI_CAP_FBSS) ?
286 " with FBS" : "");
287 if (ctlr->quirks != 0) {
288 device_printf(dev, "quirks=0x%b\n", ctlr->quirks,
289 AHCI_Q_BIT_STRING);
290 }
291 if (bootverbose) {
292 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps",
293 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"",
294 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"",
295 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"",
296 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"",
297 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"",
298 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"",
299 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"",
300 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"",
301 ((speed == 1) ? "1.5":((speed == 2) ? "3":
302 ((speed == 3) ? "6":"?"))));
303 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n",
304 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"",
305 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"",
306 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"",
307 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"",
308 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"",
309 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"",
310 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1,
311 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"",
312 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"",
313 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"",
314 (ctlr->caps & AHCI_CAP_NPMASK) + 1);
315 }
316 if (bootverbose && version >= 0x00010200) {
317 device_printf(dev, "Caps2:%s%s%s%s%s%s\n",
318 (ctlr->caps2 & AHCI_CAP2_DESO) ? " DESO":"",
319 (ctlr->caps2 & AHCI_CAP2_SADM) ? " SADM":"",
320 (ctlr->caps2 & AHCI_CAP2_SDS) ? " SDS":"",
321 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"",
322 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"",
323 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":"");
324 }
325 /* Attach all channels on this controller */
326 for (unit = 0; unit < ctlr->channels; unit++) {
327 child = device_add_child(dev, "ahcich", -1);
328 if (child == NULL) {
329 device_printf(dev, "failed to add channel device\n");
330 continue;
331 }
332 device_set_ivars(child, (void *)(intptr_t)unit);
333 if ((ctlr->ichannels & (1 << unit)) == 0)
334 device_disable(child);
335 }
336 if (ctlr->caps & AHCI_CAP_EMS) {
337 child = device_add_child(dev, "ahciem", -1);
338 if (child == NULL)
339 device_printf(dev, "failed to add enclosure device\n");
340 else
341 device_set_ivars(child, (void *)(intptr_t)-1);
342 }
343 bus_generic_attach(dev);
344 return (0);
345 }
346
347 int
348 ahci_detach(device_t dev)
349 {
350 struct ahci_controller *ctlr = device_get_softc(dev);
351 int i;
352
353 /* Detach & delete all children */
354 device_delete_children(dev);
355
356 /* Free interrupts. */
357 for (i = 0; i < ctlr->numirqs; i++) {
358 if (ctlr->irqs[i].r_irq) {
359 bus_teardown_intr(dev, ctlr->irqs[i].r_irq,
360 ctlr->irqs[i].handle);
361 bus_release_resource(dev, SYS_RES_IRQ,
362 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq);
363 }
364 }
365 bus_dma_tag_destroy(ctlr->dma_tag);
366 /* Free memory. */
367 rman_fini(&ctlr->sc_iomem);
368 ahci_free_mem(dev);
369 return (0);
370 }
371
372 void
373 ahci_free_mem(device_t dev)
374 {
375 struct ahci_controller *ctlr = device_get_softc(dev);
376
377 /* Release memory resources */
378 if (ctlr->r_mem)
379 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
380 if (ctlr->r_msix_table)
381 bus_release_resource(dev, SYS_RES_MEMORY,
382 ctlr->r_msix_tab_rid, ctlr->r_msix_table);
383 if (ctlr->r_msix_pba)
384 bus_release_resource(dev, SYS_RES_MEMORY,
385 ctlr->r_msix_pba_rid, ctlr->r_msix_pba);
386
387 ctlr->r_msix_pba = ctlr->r_mem = ctlr->r_msix_table = NULL;
388 }
389
390 int
391 ahci_setup_interrupt(device_t dev)
392 {
393 struct ahci_controller *ctlr = device_get_softc(dev);
394 int i;
395
396 /* Check for single MSI vector fallback. */
397 if (ctlr->numirqs > 1 &&
398 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) {
399 device_printf(dev, "Falling back to one MSI\n");
400 ctlr->numirqs = 1;
401 }
402
403 /* Ensure we don't overrun irqs. */
404 if (ctlr->numirqs > AHCI_MAX_IRQS) {
405 device_printf(dev, "Too many irqs %d > %d (clamping)\n",
406 ctlr->numirqs, AHCI_MAX_IRQS);
407 ctlr->numirqs = AHCI_MAX_IRQS;
408 }
409
410 /* Allocate all IRQs. */
411 for (i = 0; i < ctlr->numirqs; i++) {
412 ctlr->irqs[i].ctlr = ctlr;
413 ctlr->irqs[i].r_irq_rid = i + (ctlr->msi ? 1 : 0);
414 if (ctlr->channels == 1 && !ctlr->ccc && ctlr->msi)
415 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE;
416 else if (ctlr->numirqs == 1 || i >= ctlr->channels ||
417 (ctlr->ccc && i == ctlr->cccv))
418 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL;
419 else if (ctlr->channels > ctlr->numirqs &&
420 i == ctlr->numirqs - 1)
421 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER;
422 else
423 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE;
424 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
425 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) {
426 device_printf(dev, "unable to map interrupt\n");
427 return (ENXIO);
428 }
429 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL,
430 (ctlr->irqs[i].mode != AHCI_IRQ_MODE_ONE) ? ahci_intr :
431 ((ctlr->quirks & AHCI_Q_EDGEIS) ? ahci_intr_one_edge :
432 ahci_intr_one),
433 &ctlr->irqs[i], &ctlr->irqs[i].handle))) {
434 /* SOS XXX release r_irq */
435 device_printf(dev, "unable to setup interrupt\n");
436 return (ENXIO);
437 }
438 if (ctlr->numirqs > 1) {
439 bus_describe_intr(dev, ctlr->irqs[i].r_irq,
440 ctlr->irqs[i].handle,
441 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ?
442 "ch%d" : "%d", i);
443 }
444 }
445 return (0);
446 }
447
448 /*
449 * Common case interrupt handler.
450 */
451 static void
452 ahci_intr(void *data)
453 {
454 struct ahci_controller_irq *irq = data;
455 struct ahci_controller *ctlr = irq->ctlr;
456 u_int32_t is, ise = 0;
457 void *arg;
458 int unit;
459
460 if (irq->mode == AHCI_IRQ_MODE_ALL) {
461 unit = 0;
462 if (ctlr->ccc)
463 is = ctlr->ichannels;
464 else
465 is = ATA_INL(ctlr->r_mem, AHCI_IS);
466 } else { /* AHCI_IRQ_MODE_AFTER */
467 unit = irq->r_irq_rid - 1;
468 is = ATA_INL(ctlr->r_mem, AHCI_IS);
469 is &= (0xffffffff << unit);
470 }
471 /* CCC interrupt is edge triggered. */
472 if (ctlr->ccc)
473 ise = 1 << ctlr->cccv;
474 /* Some controllers have edge triggered IS. */
475 if (ctlr->quirks & AHCI_Q_EDGEIS)
476 ise |= is;
477 if (ise != 0)
478 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise);
479 for (; unit < ctlr->channels; unit++) {
480 if ((is & (1 << unit)) != 0 &&
481 (arg = ctlr->interrupt[unit].argument)) {
482 ctlr->interrupt[unit].function(arg);
483 }
484 }
485 /* AHCI declares level triggered IS. */
486 if (!(ctlr->quirks & AHCI_Q_EDGEIS))
487 ATA_OUTL(ctlr->r_mem, AHCI_IS, is);
488 ATA_RBL(ctlr->r_mem, AHCI_IS);
489 }
490
491 /*
492 * Simplified interrupt handler for multivector MSI mode.
493 */
494 static void
495 ahci_intr_one(void *data)
496 {
497 struct ahci_controller_irq *irq = data;
498 struct ahci_controller *ctlr = irq->ctlr;
499 void *arg;
500 int unit;
501
502 unit = irq->r_irq_rid - 1;
503 if ((arg = ctlr->interrupt[unit].argument))
504 ctlr->interrupt[unit].function(arg);
505 /* AHCI declares level triggered IS. */
506 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
507 ATA_RBL(ctlr->r_mem, AHCI_IS);
508 }
509
510 static void
511 ahci_intr_one_edge(void *data)
512 {
513 struct ahci_controller_irq *irq = data;
514 struct ahci_controller *ctlr = irq->ctlr;
515 void *arg;
516 int unit;
517
518 unit = irq->r_irq_rid - 1;
519 /* Some controllers have edge triggered IS. */
520 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
521 if ((arg = ctlr->interrupt[unit].argument))
522 ctlr->interrupt[unit].function(arg);
523 ATA_RBL(ctlr->r_mem, AHCI_IS);
524 }
525
526 struct resource *
527 ahci_alloc_resource(device_t dev, device_t child, int type, int *rid,
528 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
529 {
530 struct ahci_controller *ctlr = device_get_softc(dev);
531 struct resource *res;
532 rman_res_t st;
533 int offset, size, unit;
534
535 unit = (intptr_t)device_get_ivars(child);
536 res = NULL;
537 switch (type) {
538 case SYS_RES_MEMORY:
539 if (unit >= 0) {
540 offset = AHCI_OFFSET + (unit << 7);
541 size = 128;
542 } else if (*rid == 0) {
543 offset = AHCI_EM_CTL;
544 size = 4;
545 } else {
546 offset = (ctlr->emloc & 0xffff0000) >> 14;
547 size = (ctlr->emloc & 0x0000ffff) << 2;
548 if (*rid != 1) {
549 if (*rid == 2 && (ctlr->capsem &
550 (AHCI_EM_XMT | AHCI_EM_SMB)) == 0)
551 offset += size;
552 else
553 break;
554 }
555 }
556 st = rman_get_start(ctlr->r_mem);
557 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset,
558 st + offset + size - 1, size, RF_ACTIVE, child);
559 if (res) {
560 bus_space_handle_t bsh;
561 bus_space_tag_t bst;
562 bsh = rman_get_bushandle(ctlr->r_mem);
563 bst = rman_get_bustag(ctlr->r_mem);
564 bus_space_subregion(bst, bsh, offset, 128, &bsh);
565 rman_set_bushandle(res, bsh);
566 rman_set_bustag(res, bst);
567 }
568 break;
569 case SYS_RES_IRQ:
570 if (*rid == ATA_IRQ_RID)
571 res = ctlr->irqs[0].r_irq;
572 break;
573 }
574 return (res);
575 }
576
577 int
578 ahci_release_resource(device_t dev, device_t child, int type, int rid,
579 struct resource *r)
580 {
581
582 switch (type) {
583 case SYS_RES_MEMORY:
584 rman_release_resource(r);
585 return (0);
586 case SYS_RES_IRQ:
587 if (rid != ATA_IRQ_RID)
588 return (ENOENT);
589 return (0);
590 }
591 return (EINVAL);
592 }
593
594 int
595 ahci_setup_intr(device_t dev, device_t child, struct resource *irq,
596 int flags, driver_filter_t *filter, driver_intr_t *function,
597 void *argument, void **cookiep)
598 {
599 struct ahci_controller *ctlr = device_get_softc(dev);
600 int unit = (intptr_t)device_get_ivars(child);
601
602 if (filter != NULL) {
603 printf("ahci.c: we cannot use a filter here\n");
604 return (EINVAL);
605 }
606 ctlr->interrupt[unit].function = function;
607 ctlr->interrupt[unit].argument = argument;
608 return (0);
609 }
610
611 int
612 ahci_teardown_intr(device_t dev, device_t child, struct resource *irq,
613 void *cookie)
614 {
615 struct ahci_controller *ctlr = device_get_softc(dev);
616 int unit = (intptr_t)device_get_ivars(child);
617
618 ctlr->interrupt[unit].function = NULL;
619 ctlr->interrupt[unit].argument = NULL;
620 return (0);
621 }
622
623 int
624 ahci_print_child(device_t dev, device_t child)
625 {
626 int retval, channel;
627
628 retval = bus_print_child_header(dev, child);
629 channel = (int)(intptr_t)device_get_ivars(child);
630 if (channel >= 0)
631 retval += printf(" at channel %d", channel);
632 retval += bus_print_child_footer(dev, child);
633 return (retval);
634 }
635
636 int
637 ahci_child_location_str(device_t dev, device_t child, char *buf,
638 size_t buflen)
639 {
640 int channel;
641
642 channel = (int)(intptr_t)device_get_ivars(child);
643 if (channel >= 0)
644 snprintf(buf, buflen, "channel=%d", channel);
645 return (0);
646 }
647
648 bus_dma_tag_t
649 ahci_get_dma_tag(device_t dev, device_t child)
650 {
651 struct ahci_controller *ctlr = device_get_softc(dev);
652
653 return (ctlr->dma_tag);
654 }
655
656 static int
657 ahci_ch_probe(device_t dev)
658 {
659
660 device_set_desc_copy(dev, "AHCI channel");
661 return (BUS_PROBE_DEFAULT);
662 }
663
664 static int
665 ahci_ch_attach(device_t dev)
666 {
667 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev));
668 struct ahci_channel *ch = device_get_softc(dev);
669 struct cam_devq *devq;
670 int rid, error, i, sata_rev = 0;
671 u_int32_t version;
672
673 ch->dev = dev;
674 ch->unit = (intptr_t)device_get_ivars(dev);
675 ch->caps = ctlr->caps;
676 ch->caps2 = ctlr->caps2;
677 ch->start = ctlr->ch_start;
678 ch->quirks = ctlr->quirks;
679 ch->vendorid = ctlr->vendorid;
680 ch->deviceid = ctlr->deviceid;
681 ch->subvendorid = ctlr->subvendorid;
682 ch->subdeviceid = ctlr->subdeviceid;
683 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1;
684 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF);
685 ch->pm_level = 0;
686 resource_int_value(device_get_name(dev),
687 device_get_unit(dev), "pm_level", &ch->pm_level);
688 STAILQ_INIT(&ch->doneq);
689 if (ch->pm_level > 3)
690 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0);
691 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0);
692 /* JMicron external ports (0) sometimes limited */
693 if ((ctlr->quirks & AHCI_Q_SATA1_UNIT0) && ch->unit == 0)
694 sata_rev = 1;
695 if (ch->quirks & AHCI_Q_SATA2)
696 sata_rev = 2;
697 resource_int_value(device_get_name(dev),
698 device_get_unit(dev), "sata_rev", &sata_rev);
699 for (i = 0; i < 16; i++) {
700 ch->user[i].revision = sata_rev;
701 ch->user[i].mode = 0;
702 ch->user[i].bytecount = 8192;
703 ch->user[i].tags = ch->numslots;
704 ch->user[i].caps = 0;
705 ch->curr[i] = ch->user[i];
706 if (ch->pm_level) {
707 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ |
708 CTS_SATA_CAPS_H_APST |
709 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST;
710 }
711 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA |
712 CTS_SATA_CAPS_H_AN;
713 }
714 rid = 0;
715 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
716 &rid, RF_ACTIVE)))
717 return (ENXIO);
718 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD);
719 version = ATA_INL(ctlr->r_mem, AHCI_VS);
720 if (version < 0x00010200 && (ctlr->caps & AHCI_CAP_FBSS))
721 ch->chcaps |= AHCI_P_CMD_FBSCP;
722 if (ch->caps2 & AHCI_CAP2_SDS)
723 ch->chscaps = ATA_INL(ch->r_mem, AHCI_P_DEVSLP);
724 if (bootverbose) {
725 device_printf(dev, "Caps:%s%s%s%s%s%s\n",
726 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"",
727 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"",
728 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"",
729 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"",
730 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":"",
731 (ch->chscaps & AHCI_P_DEVSLP_DSP) ? " DSP":"");
732 }
733 ahci_dmainit(dev);
734 ahci_slotsalloc(dev);
735 mtx_lock(&ch->mtx);
736 ahci_ch_init(dev);
737 rid = ATA_IRQ_RID;
738 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
739 &rid, RF_SHAREABLE | RF_ACTIVE))) {
740 device_printf(dev, "Unable to map interrupt\n");
741 error = ENXIO;
742 goto err0;
743 }
744 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL,
745 ctlr->direct ? ahci_ch_intr_direct : ahci_ch_intr,
746 ch, &ch->ih))) {
747 device_printf(dev, "Unable to setup interrupt\n");
748 error = ENXIO;
749 goto err1;
750 }
751 /* Create the device queue for our SIM. */
752 devq = cam_simq_alloc(ch->numslots);
753 if (devq == NULL) {
754 device_printf(dev, "Unable to allocate simq\n");
755 error = ENOMEM;
756 goto err1;
757 }
758 /* Construct SIM entry */
759 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch,
760 device_get_unit(dev), (struct mtx *)&ch->mtx,
761 (ch->quirks & AHCI_Q_NOCCS) ? 1 : min(2, ch->numslots),
762 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0,
763 devq);
764 if (ch->sim == NULL) {
765 cam_simq_free(devq);
766 device_printf(dev, "unable to allocate sim\n");
767 error = ENOMEM;
768 goto err1;
769 }
770 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) {
771 device_printf(dev, "unable to register xpt bus\n");
772 error = ENXIO;
773 goto err2;
774 }
775 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim),
776 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
777 device_printf(dev, "unable to create path\n");
778 error = ENXIO;
779 goto err3;
780 }
781 if (ch->pm_level > 3) {
782 callout_reset(&ch->pm_timer,
783 (ch->pm_level == 4) ? hz / 1000 : hz / 8,
784 ahci_ch_pm, ch);
785 }
786 mtx_unlock(&ch->mtx);
787 return (0);
788
789 err3:
790 xpt_bus_deregister(cam_sim_path(ch->sim));
791 err2:
792 cam_sim_free(ch->sim, /*free_devq*/TRUE);
793 err1:
794 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
795 err0:
796 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
797 mtx_unlock(&ch->mtx);
798 mtx_destroy(&ch->mtx);
799 return (error);
800 }
801
802 static int
803 ahci_ch_detach(device_t dev)
804 {
805 struct ahci_channel *ch = device_get_softc(dev);
806
807 mtx_lock(&ch->mtx);
808 xpt_async(AC_LOST_DEVICE, ch->path, NULL);
809 /* Forget about reset. */
810 if (ch->resetting) {
811 ch->resetting = 0;
812 xpt_release_simq(ch->sim, TRUE);
813 }
814 xpt_free_path(ch->path);
815 xpt_bus_deregister(cam_sim_path(ch->sim));
816 cam_sim_free(ch->sim, /*free_devq*/TRUE);
817 mtx_unlock(&ch->mtx);
818
819 if (ch->pm_level > 3)
820 callout_drain(&ch->pm_timer);
821 callout_drain(&ch->reset_timer);
822 bus_teardown_intr(dev, ch->r_irq, ch->ih);
823 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
824
825 ahci_ch_deinit(dev);
826 ahci_slotsfree(dev);
827 ahci_dmafini(dev);
828
829 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
830 mtx_destroy(&ch->mtx);
831 return (0);
832 }
833
834 static int
835 ahci_ch_init(device_t dev)
836 {
837 struct ahci_channel *ch = device_get_softc(dev);
838 uint64_t work;
839
840 /* Disable port interrupts */
841 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
842 /* Setup work areas */
843 work = ch->dma.work_bus + AHCI_CL_OFFSET;
844 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff);
845 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32);
846 work = ch->dma.rfis_bus;
847 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff);
848 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32);
849 /* Activate the channel and power/spin up device */
850 ATA_OUTL(ch->r_mem, AHCI_P_CMD,
851 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD |
852 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) |
853 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 )));
854 ahci_start_fr(ch);
855 ahci_start(ch, 1);
856 return (0);
857 }
858
859 static int
860 ahci_ch_deinit(device_t dev)
861 {
862 struct ahci_channel *ch = device_get_softc(dev);
863
864 /* Disable port interrupts. */
865 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
866 /* Reset command register. */
867 ahci_stop(ch);
868 ahci_stop_fr(ch);
869 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0);
870 /* Allow everything, including partial and slumber modes. */
871 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0);
872 /* Request slumber mode transition and give some time to get there. */
873 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER);
874 DELAY(100);
875 /* Disable PHY. */
876 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
877 return (0);
878 }
879
880 static int
881 ahci_ch_suspend(device_t dev)
882 {
883 struct ahci_channel *ch = device_get_softc(dev);
884
885 mtx_lock(&ch->mtx);
886 xpt_freeze_simq(ch->sim, 1);
887 /* Forget about reset. */
888 if (ch->resetting) {
889 ch->resetting = 0;
890 callout_stop(&ch->reset_timer);
891 xpt_release_simq(ch->sim, TRUE);
892 }
893 while (ch->oslots)
894 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100);
895 ahci_ch_deinit(dev);
896 mtx_unlock(&ch->mtx);
897 return (0);
898 }
899
900 static int
901 ahci_ch_resume(device_t dev)
902 {
903 struct ahci_channel *ch = device_get_softc(dev);
904
905 mtx_lock(&ch->mtx);
906 ahci_ch_init(dev);
907 ahci_reset(ch);
908 xpt_release_simq(ch->sim, TRUE);
909 mtx_unlock(&ch->mtx);
910 return (0);
911 }
912
913 devclass_t ahcich_devclass;
914 static device_method_t ahcich_methods[] = {
915 DEVMETHOD(device_probe, ahci_ch_probe),
916 DEVMETHOD(device_attach, ahci_ch_attach),
917 DEVMETHOD(device_detach, ahci_ch_detach),
918 DEVMETHOD(device_suspend, ahci_ch_suspend),
919 DEVMETHOD(device_resume, ahci_ch_resume),
920 DEVMETHOD_END
921 };
922 static driver_t ahcich_driver = {
923 "ahcich",
924 ahcich_methods,
925 sizeof(struct ahci_channel)
926 };
927 DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, NULL, NULL);
928
929 struct ahci_dc_cb_args {
930 bus_addr_t maddr;
931 int error;
932 };
933
934 static void
935 ahci_dmainit(device_t dev)
936 {
937 struct ahci_channel *ch = device_get_softc(dev);
938 struct ahci_dc_cb_args dcba;
939 size_t rfsize;
940
941 /* Command area. */
942 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0,
943 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
944 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE,
945 0, NULL, NULL, &ch->dma.work_tag))
946 goto error;
947 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work,
948 BUS_DMA_ZERO, &ch->dma.work_map))
949 goto error;
950 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work,
951 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) {
952 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
953 goto error;
954 }
955 ch->dma.work_bus = dcba.maddr;
956 /* FIS receive area. */
957 if (ch->chcaps & AHCI_P_CMD_FBSCP)
958 rfsize = 4096;
959 else
960 rfsize = 256;
961 if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0,
962 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
963 NULL, NULL, rfsize, 1, rfsize,
964 0, NULL, NULL, &ch->dma.rfis_tag))
965 goto error;
966 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0,
967 &ch->dma.rfis_map))
968 goto error;
969 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis,
970 rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) {
971 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
972 goto error;
973 }
974 ch->dma.rfis_bus = dcba.maddr;
975 /* Data area. */
976 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
977 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
978 NULL, NULL,
979 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots,
980 AHCI_SG_ENTRIES, AHCI_PRD_MAX,
981 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) {
982 goto error;
983 }
984 return;
985
986 error:
987 device_printf(dev, "WARNING - DMA initialization failed\n");
988 ahci_dmafini(dev);
989 }
990
991 static void
992 ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
993 {
994 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc;
995
996 if (!(dcba->error = error))
997 dcba->maddr = segs[0].ds_addr;
998 }
999
1000 static void
1001 ahci_dmafini(device_t dev)
1002 {
1003 struct ahci_channel *ch = device_get_softc(dev);
1004
1005 if (ch->dma.data_tag) {
1006 bus_dma_tag_destroy(ch->dma.data_tag);
1007 ch->dma.data_tag = NULL;
1008 }
1009 if (ch->dma.rfis_bus) {
1010 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map);
1011 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
1012 ch->dma.rfis_bus = 0;
1013 ch->dma.rfis = NULL;
1014 }
1015 if (ch->dma.work_bus) {
1016 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map);
1017 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
1018 ch->dma.work_bus = 0;
1019 ch->dma.work = NULL;
1020 }
1021 if (ch->dma.work_tag) {
1022 bus_dma_tag_destroy(ch->dma.work_tag);
1023 ch->dma.work_tag = NULL;
1024 }
1025 }
1026
1027 static void
1028 ahci_slotsalloc(device_t dev)
1029 {
1030 struct ahci_channel *ch = device_get_softc(dev);
1031 int i;
1032
1033 /* Alloc and setup command/dma slots */
1034 bzero(ch->slot, sizeof(ch->slot));
1035 for (i = 0; i < ch->numslots; i++) {
1036 struct ahci_slot *slot = &ch->slot[i];
1037
1038 slot->ch = ch;
1039 slot->slot = i;
1040 slot->state = AHCI_SLOT_EMPTY;
1041 slot->ccb = NULL;
1042 callout_init_mtx(&slot->timeout, &ch->mtx, 0);
1043
1044 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map))
1045 device_printf(ch->dev, "FAILURE - create data_map\n");
1046 }
1047 }
1048
1049 static void
1050 ahci_slotsfree(device_t dev)
1051 {
1052 struct ahci_channel *ch = device_get_softc(dev);
1053 int i;
1054
1055 /* Free all dma slots */
1056 for (i = 0; i < ch->numslots; i++) {
1057 struct ahci_slot *slot = &ch->slot[i];
1058
1059 callout_drain(&slot->timeout);
1060 if (slot->dma.data_map) {
1061 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map);
1062 slot->dma.data_map = NULL;
1063 }
1064 }
1065 }
1066
1067 static int
1068 ahci_phy_check_events(struct ahci_channel *ch, u_int32_t serr)
1069 {
1070
1071 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) ||
1072 ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) {
1073 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
1074 union ccb *ccb;
1075
1076 if (bootverbose) {
1077 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE)
1078 device_printf(ch->dev, "CONNECT requested\n");
1079 else
1080 device_printf(ch->dev, "DISCONNECT requested\n");
1081 }
1082 ahci_reset(ch);
1083 if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
1084 return (0);
1085 if (xpt_create_path(&ccb->ccb_h.path, NULL,
1086 cam_sim_path(ch->sim),
1087 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
1088 xpt_free_ccb(ccb);
1089 return (0);
1090 }
1091 xpt_rescan(ccb);
1092 return (1);
1093 }
1094 return (0);
1095 }
1096
1097 static void
1098 ahci_cpd_check_events(struct ahci_channel *ch)
1099 {
1100 u_int32_t status;
1101 union ccb *ccb;
1102 device_t dev;
1103
1104 if (ch->pm_level == 0)
1105 return;
1106
1107 status = ATA_INL(ch->r_mem, AHCI_P_CMD);
1108 if ((status & AHCI_P_CMD_CPD) == 0)
1109 return;
1110
1111 if (bootverbose) {
1112 dev = ch->dev;
1113 if (status & AHCI_P_CMD_CPS) {
1114 device_printf(dev, "COLD CONNECT requested\n");
1115 } else
1116 device_printf(dev, "COLD DISCONNECT requested\n");
1117 }
1118 ahci_reset(ch);
1119 if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
1120 return;
1121 if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim),
1122 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
1123 xpt_free_ccb(ccb);
1124 return;
1125 }
1126 xpt_rescan(ccb);
1127 }
1128
1129 static void
1130 ahci_notify_events(struct ahci_channel *ch, u_int32_t status)
1131 {
1132 struct cam_path *dpath;
1133 int i;
1134
1135 if (ch->caps & AHCI_CAP_SSNTF)
1136 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status);
1137 if (bootverbose)
1138 device_printf(ch->dev, "SNTF 0x%04x\n", status);
1139 for (i = 0; i < 16; i++) {
1140 if ((status & (1 << i)) == 0)
1141 continue;
1142 if (xpt_create_path(&dpath, NULL,
1143 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) {
1144 xpt_async(AC_SCSI_AEN, dpath, NULL);
1145 xpt_free_path(dpath);
1146 }
1147 }
1148 }
1149
1150 static void
1151 ahci_done(struct ahci_channel *ch, union ccb *ccb)
1152 {
1153
1154 mtx_assert(&ch->mtx, MA_OWNED);
1155 if ((ccb->ccb_h.func_code & XPT_FC_QUEUED) == 0 ||
1156 ch->batch == 0) {
1157 xpt_done(ccb);
1158 return;
1159 }
1160
1161 STAILQ_INSERT_TAIL(&ch->doneq, &ccb->ccb_h, sim_links.stqe);
1162 }
1163
1164 static void
1165 ahci_ch_intr(void *arg)
1166 {
1167 struct ahci_channel *ch = (struct ahci_channel *)arg;
1168 uint32_t istatus;
1169
1170 /* Read interrupt statuses. */
1171 istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
1172
1173 mtx_lock(&ch->mtx);
1174 ahci_ch_intr_main(ch, istatus);
1175 mtx_unlock(&ch->mtx);
1176 }
1177
1178 static void
1179 ahci_ch_intr_direct(void *arg)
1180 {
1181 struct ahci_channel *ch = (struct ahci_channel *)arg;
1182 struct ccb_hdr *ccb_h;
1183 uint32_t istatus;
1184 STAILQ_HEAD(, ccb_hdr) tmp_doneq = STAILQ_HEAD_INITIALIZER(tmp_doneq);
1185
1186 /* Read interrupt statuses. */
1187 istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
1188
1189 mtx_lock(&ch->mtx);
1190 ch->batch = 1;
1191 ahci_ch_intr_main(ch, istatus);
1192 ch->batch = 0;
1193 /*
1194 * Prevent the possibility of issues caused by processing the queue
1195 * while unlocked below by moving the contents to a local queue.
1196 */
1197 STAILQ_CONCAT(&tmp_doneq, &ch->doneq);
1198 mtx_unlock(&ch->mtx);
1199 while ((ccb_h = STAILQ_FIRST(&tmp_doneq)) != NULL) {
1200 STAILQ_REMOVE_HEAD(&tmp_doneq, sim_links.stqe);
1201 xpt_done_direct((union ccb *)ccb_h);
1202 }
1203 }
1204
1205 static void
1206 ahci_ch_pm(void *arg)
1207 {
1208 struct ahci_channel *ch = (struct ahci_channel *)arg;
1209 uint32_t work;
1210
1211 if (ch->numrslots != 0)
1212 return;
1213 work = ATA_INL(ch->r_mem, AHCI_P_CMD);
1214 if (ch->pm_level == 4)
1215 work |= AHCI_P_CMD_PARTIAL;
1216 else
1217 work |= AHCI_P_CMD_SLUMBER;
1218 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work);
1219 }
1220
1221 static void
1222 ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus)
1223 {
1224 uint32_t cstatus, serr = 0, sntf = 0, ok, err;
1225 enum ahci_err_type et;
1226 int i, ccs, port, reset = 0;
1227
1228 /* Clear interrupt statuses. */
1229 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus);
1230 /* Read command statuses. */
1231 if (ch->numtslots != 0)
1232 cstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
1233 else
1234 cstatus = 0;
1235 if (ch->numrslots != ch->numtslots)
1236 cstatus |= ATA_INL(ch->r_mem, AHCI_P_CI);
1237 /* Read SNTF in one of possible ways. */
1238 if ((istatus & AHCI_P_IX_SDB) &&
1239 (ch->pm_present || ch->curr[0].atapi != 0)) {
1240 if (ch->caps & AHCI_CAP_SSNTF)
1241 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF);
1242 else if (ch->fbs_enabled) {
1243 u_int8_t *fis = ch->dma.rfis + 0x58;
1244
1245 for (i = 0; i < 16; i++) {
1246 if (fis[1] & 0x80) {
1247 fis[1] &= 0x7f;
1248 sntf |= 1 << i;
1249 }
1250 fis += 256;
1251 }
1252 } else {
1253 u_int8_t *fis = ch->dma.rfis + 0x58;
1254
1255 if (fis[1] & 0x80)
1256 sntf = (1 << (fis[1] & 0x0f));
1257 }
1258 }
1259 /* Process PHY events */
1260 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF |
1261 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) {
1262 serr = ATA_INL(ch->r_mem, AHCI_P_SERR);
1263 if (serr) {
1264 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr);
1265 reset = ahci_phy_check_events(ch, serr);
1266 }
1267 }
1268 /* Process cold presence detection events */
1269 if ((istatus & AHCI_P_IX_CPD) && !reset)
1270 ahci_cpd_check_events(ch);
1271 /* Process command errors */
1272 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF |
1273 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) {
1274 if (ch->quirks & AHCI_Q_NOCCS) {
1275 /*
1276 * ASMedia chips sometimes report failed commands as
1277 * completed. Count all running commands as failed.
1278 */
1279 cstatus |= ch->rslots;
1280
1281 /* They also report wrong CCS, so try to guess one. */
1282 ccs = powerof2(cstatus) ? ffs(cstatus) - 1 : -1;
1283 } else {
1284 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) &
1285 AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT;
1286 }
1287 //device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n",
1288 // __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD),
1289 // serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs);
1290 port = -1;
1291 if (ch->fbs_enabled) {
1292 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS);
1293 if (fbs & AHCI_P_FBS_SDE) {
1294 port = (fbs & AHCI_P_FBS_DWE)
1295 >> AHCI_P_FBS_DWE_SHIFT;
1296 } else {
1297 for (i = 0; i < 16; i++) {
1298 if (ch->numrslotspd[i] == 0)
1299 continue;
1300 if (port == -1)
1301 port = i;
1302 else if (port != i) {
1303 port = -2;
1304 break;
1305 }
1306 }
1307 }
1308 }
1309 err = ch->rslots & cstatus;
1310 } else {
1311 ccs = 0;
1312 err = 0;
1313 port = -1;
1314 }
1315 /* Complete all successful commands. */
1316 ok = ch->rslots & ~cstatus;
1317 for (i = 0; i < ch->numslots; i++) {
1318 if ((ok >> i) & 1)
1319 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE);
1320 }
1321 /* On error, complete the rest of commands with error statuses. */
1322 if (err) {
1323 if (ch->frozen) {
1324 union ccb *fccb = ch->frozen;
1325 ch->frozen = NULL;
1326 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1327 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1328 xpt_freeze_devq(fccb->ccb_h.path, 1);
1329 fccb->ccb_h.status |= CAM_DEV_QFRZN;
1330 }
1331 ahci_done(ch, fccb);
1332 }
1333 for (i = 0; i < ch->numslots; i++) {
1334 /* XXX: reqests in loading state. */
1335 if (((err >> i) & 1) == 0)
1336 continue;
1337 if (port >= 0 &&
1338 ch->slot[i].ccb->ccb_h.target_id != port)
1339 continue;
1340 if (istatus & AHCI_P_IX_TFE) {
1341 if (port != -2) {
1342 /* Task File Error */
1343 if (ch->numtslotspd[
1344 ch->slot[i].ccb->ccb_h.target_id] == 0) {
1345 /* Untagged operation. */
1346 if (i == ccs)
1347 et = AHCI_ERR_TFE;
1348 else
1349 et = AHCI_ERR_INNOCENT;
1350 } else {
1351 /* Tagged operation. */
1352 et = AHCI_ERR_NCQ;
1353 }
1354 } else {
1355 et = AHCI_ERR_TFE;
1356 ch->fatalerr = 1;
1357 }
1358 } else if (istatus & AHCI_P_IX_IF) {
1359 if (ch->numtslots == 0 && i != ccs && port != -2)
1360 et = AHCI_ERR_INNOCENT;
1361 else
1362 et = AHCI_ERR_SATA;
1363 } else
1364 et = AHCI_ERR_INVALID;
1365 ahci_end_transaction(&ch->slot[i], et);
1366 }
1367 /*
1368 * We can't reinit port if there are some other
1369 * commands active, use resume to complete them.
1370 */
1371 if (ch->rslots != 0 && !ch->recoverycmd)
1372 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC);
1373 }
1374 /* Process NOTIFY events */
1375 if (sntf)
1376 ahci_notify_events(ch, sntf);
1377 }
1378
1379 /* Must be called with channel locked. */
1380 static int
1381 ahci_check_collision(struct ahci_channel *ch, union ccb *ccb)
1382 {
1383 int t = ccb->ccb_h.target_id;
1384
1385 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1386 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1387 /* Tagged command while we have no supported tag free. */
1388 if (((~ch->oslots) & (0xffffffff >> (32 -
1389 ch->curr[t].tags))) == 0)
1390 return (1);
1391 /* If we have FBS */
1392 if (ch->fbs_enabled) {
1393 /* Tagged command while untagged are active. */
1394 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0)
1395 return (1);
1396 } else {
1397 /* Tagged command while untagged are active. */
1398 if (ch->numrslots != 0 && ch->numtslots == 0)
1399 return (1);
1400 /* Tagged command while tagged to other target is active. */
1401 if (ch->numtslots != 0 &&
1402 ch->taggedtarget != ccb->ccb_h.target_id)
1403 return (1);
1404 }
1405 } else {
1406 /* If we have FBS */
1407 if (ch->fbs_enabled) {
1408 /* Untagged command while tagged are active. */
1409 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0)
1410 return (1);
1411 } else {
1412 /* Untagged command while tagged are active. */
1413 if (ch->numrslots != 0 && ch->numtslots != 0)
1414 return (1);
1415 }
1416 }
1417 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1418 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) {
1419 /* Atomic command while anything active. */
1420 if (ch->numrslots != 0)
1421 return (1);
1422 }
1423 /* We have some atomic command running. */
1424 if (ch->aslots != 0)
1425 return (1);
1426 return (0);
1427 }
1428
1429 /* Must be called with channel locked. */
1430 static void
1431 ahci_begin_transaction(struct ahci_channel *ch, union ccb *ccb)
1432 {
1433 struct ahci_slot *slot;
1434 int tag, tags;
1435
1436 /* Choose empty slot. */
1437 tags = ch->numslots;
1438 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1439 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA))
1440 tags = ch->curr[ccb->ccb_h.target_id].tags;
1441 if (ch->lastslot + 1 < tags)
1442 tag = ffs(~(ch->oslots >> (ch->lastslot + 1)));
1443 else
1444 tag = 0;
1445 if (tag == 0 || tag + ch->lastslot >= tags)
1446 tag = ffs(~ch->oslots) - 1;
1447 else
1448 tag += ch->lastslot;
1449 ch->lastslot = tag;
1450 /* Occupy chosen slot. */
1451 slot = &ch->slot[tag];
1452 slot->ccb = ccb;
1453 /* Stop PM timer. */
1454 if (ch->numrslots == 0 && ch->pm_level > 3)
1455 callout_stop(&ch->pm_timer);
1456 /* Update channel stats. */
1457 ch->oslots |= (1 << tag);
1458 ch->numrslots++;
1459 ch->numrslotspd[ccb->ccb_h.target_id]++;
1460 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1461 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1462 ch->numtslots++;
1463 ch->numtslotspd[ccb->ccb_h.target_id]++;
1464 ch->taggedtarget = ccb->ccb_h.target_id;
1465 }
1466 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1467 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)))
1468 ch->aslots |= (1 << tag);
1469 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1470 slot->state = AHCI_SLOT_LOADING;
1471 bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map, ccb,
1472 ahci_dmasetprd, slot, 0);
1473 } else {
1474 slot->dma.nsegs = 0;
1475 ahci_execute_transaction(slot);
1476 }
1477 }
1478
1479 /* Locked by busdma engine. */
1480 static void
1481 ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1482 {
1483 struct ahci_slot *slot = arg;
1484 struct ahci_channel *ch = slot->ch;
1485 struct ahci_cmd_tab *ctp;
1486 struct ahci_dma_prd *prd;
1487 int i;
1488
1489 if (error) {
1490 device_printf(ch->dev, "DMA load error\n");
1491 ahci_end_transaction(slot, AHCI_ERR_INVALID);
1492 return;
1493 }
1494 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n"));
1495 /* Get a piece of the workspace for this request */
1496 ctp = (struct ahci_cmd_tab *)
1497 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot));
1498 /* Fill S/G table */
1499 prd = &ctp->prd_tab[0];
1500 for (i = 0; i < nsegs; i++) {
1501 prd[i].dba = htole64(segs[i].ds_addr);
1502 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK);
1503 }
1504 slot->dma.nsegs = nsegs;
1505 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1506 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ?
1507 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE));
1508 ahci_execute_transaction(slot);
1509 }
1510
1511 /* Must be called with channel locked. */
1512 static void
1513 ahci_execute_transaction(struct ahci_slot *slot)
1514 {
1515 struct ahci_channel *ch = slot->ch;
1516 struct ahci_cmd_tab *ctp;
1517 struct ahci_cmd_list *clp;
1518 union ccb *ccb = slot->ccb;
1519 int port = ccb->ccb_h.target_id & 0x0f;
1520 int fis_size, i, softreset;
1521 uint8_t *fis = ch->dma.rfis + 0x40;
1522 uint8_t val;
1523
1524 /* Get a piece of the workspace for this request */
1525 ctp = (struct ahci_cmd_tab *)
1526 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot));
1527 /* Setup the FIS for this request */
1528 if (!(fis_size = ahci_setup_fis(ch, ctp, ccb, slot->slot))) {
1529 device_printf(ch->dev, "Setting up SATA FIS failed\n");
1530 ahci_end_transaction(slot, AHCI_ERR_INVALID);
1531 return;
1532 }
1533 /* Setup the command list entry */
1534 clp = (struct ahci_cmd_list *)
1535 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot));
1536 clp->cmd_flags = htole16(
1537 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) |
1538 (ccb->ccb_h.func_code == XPT_SCSI_IO ?
1539 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) |
1540 (fis_size / sizeof(u_int32_t)) |
1541 (port << 12));
1542 clp->prd_length = htole16(slot->dma.nsegs);
1543 /* Special handling for Soft Reset command. */
1544 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1545 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) {
1546 if (ccb->ataio.cmd.control & ATA_A_RESET) {
1547 softreset = 1;
1548 /* Kick controller into sane state */
1549 ahci_stop(ch);
1550 ahci_clo(ch);
1551 ahci_start(ch, 0);
1552 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY;
1553 } else {
1554 softreset = 2;
1555 /* Prepare FIS receive area for check. */
1556 for (i = 0; i < 20; i++)
1557 fis[i] = 0xff;
1558 }
1559 } else
1560 softreset = 0;
1561 clp->bytecount = 0;
1562 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET +
1563 (AHCI_CT_SIZE * slot->slot));
1564 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
1565 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1566 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
1567 BUS_DMASYNC_PREREAD);
1568 /* Set ACTIVE bit for NCQ commands. */
1569 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1570 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1571 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot);
1572 }
1573 /* If FBS is enabled, set PMP port. */
1574 if (ch->fbs_enabled) {
1575 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN |
1576 (port << AHCI_P_FBS_DEV_SHIFT));
1577 }
1578 /* Issue command to the controller. */
1579 slot->state = AHCI_SLOT_RUNNING;
1580 ch->rslots |= (1 << slot->slot);
1581 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot));
1582 /* Device reset commands doesn't interrupt. Poll them. */
1583 if (ccb->ccb_h.func_code == XPT_ATA_IO &&
1584 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) {
1585 int count, timeout = ccb->ccb_h.timeout * 100;
1586 enum ahci_err_type et = AHCI_ERR_NONE;
1587
1588 for (count = 0; count < timeout; count++) {
1589 DELAY(10);
1590 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot)))
1591 break;
1592 if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) &&
1593 softreset != 1) {
1594 #if 0
1595 device_printf(ch->dev,
1596 "Poll error on slot %d, TFD: %04x\n",
1597 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD));
1598 #endif
1599 et = AHCI_ERR_TFE;
1600 break;
1601 }
1602 /* Workaround for ATI SB600/SB700 chipsets. */
1603 if (ccb->ccb_h.target_id == 15 &&
1604 (ch->quirks & AHCI_Q_ATI_PMP_BUG) &&
1605 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) {
1606 et = AHCI_ERR_TIMEOUT;
1607 break;
1608 }
1609 }
1610
1611 /*
1612 * Marvell HBAs with non-RAID firmware do not wait for
1613 * readiness after soft reset, so we have to wait here.
1614 * Marvell RAIDs do not have this problem, but instead
1615 * sometimes forget to update FIS receive area, breaking
1616 * this wait.
1617 */
1618 if ((ch->quirks & AHCI_Q_NOBSYRES) == 0 &&
1619 (ch->quirks & AHCI_Q_ATI_PMP_BUG) == 0 &&
1620 softreset == 2 && et == AHCI_ERR_NONE) {
1621 for ( ; count < timeout; count++) {
1622 bus_dmamap_sync(ch->dma.rfis_tag,
1623 ch->dma.rfis_map, BUS_DMASYNC_POSTREAD);
1624 val = fis[2];
1625 bus_dmamap_sync(ch->dma.rfis_tag,
1626 ch->dma.rfis_map, BUS_DMASYNC_PREREAD);
1627 if ((val & ATA_S_BUSY) == 0)
1628 break;
1629 DELAY(10);
1630 }
1631 }
1632
1633 if (timeout && (count >= timeout)) {
1634 device_printf(ch->dev, "Poll timeout on slot %d port %d\n",
1635 slot->slot, port);
1636 device_printf(ch->dev, "is %08x cs %08x ss %08x "
1637 "rs %08x tfd %02x serr %08x cmd %08x\n",
1638 ATA_INL(ch->r_mem, AHCI_P_IS),
1639 ATA_INL(ch->r_mem, AHCI_P_CI),
1640 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
1641 ATA_INL(ch->r_mem, AHCI_P_TFD),
1642 ATA_INL(ch->r_mem, AHCI_P_SERR),
1643 ATA_INL(ch->r_mem, AHCI_P_CMD));
1644 et = AHCI_ERR_TIMEOUT;
1645 }
1646
1647 /* Kick controller into sane state and enable FBS. */
1648 if (softreset == 2)
1649 ch->eslots |= (1 << slot->slot);
1650 ahci_end_transaction(slot, et);
1651 return;
1652 }
1653 /* Start command execution timeout */
1654 callout_reset_sbt(&slot->timeout, SBT_1MS * ccb->ccb_h.timeout / 2,
1655 0, (timeout_t*)ahci_timeout, slot, 0);
1656 return;
1657 }
1658
1659 /* Must be called with channel locked. */
1660 static void
1661 ahci_process_timeout(struct ahci_channel *ch)
1662 {
1663 int i;
1664
1665 mtx_assert(&ch->mtx, MA_OWNED);
1666 /* Handle the rest of commands. */
1667 for (i = 0; i < ch->numslots; i++) {
1668 /* Do we have a running request on slot? */
1669 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
1670 continue;
1671 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT);
1672 }
1673 }
1674
1675 /* Must be called with channel locked. */
1676 static void
1677 ahci_rearm_timeout(struct ahci_channel *ch)
1678 {
1679 int i;
1680
1681 mtx_assert(&ch->mtx, MA_OWNED);
1682 for (i = 0; i < ch->numslots; i++) {
1683 struct ahci_slot *slot = &ch->slot[i];
1684
1685 /* Do we have a running request on slot? */
1686 if (slot->state < AHCI_SLOT_RUNNING)
1687 continue;
1688 if ((ch->toslots & (1 << i)) == 0)
1689 continue;
1690 callout_reset_sbt(&slot->timeout,
1691 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0,
1692 (timeout_t*)ahci_timeout, slot, 0);
1693 }
1694 }
1695
1696 /* Locked by callout mechanism. */
1697 static void
1698 ahci_timeout(struct ahci_slot *slot)
1699 {
1700 struct ahci_channel *ch = slot->ch;
1701 device_t dev = ch->dev;
1702 uint32_t sstatus;
1703 int ccs;
1704 int i;
1705
1706 /* Check for stale timeout. */
1707 if (slot->state < AHCI_SLOT_RUNNING)
1708 return;
1709
1710 /* Check if slot was not being executed last time we checked. */
1711 if (slot->state < AHCI_SLOT_EXECUTING) {
1712 /* Check if slot started executing. */
1713 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
1714 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK)
1715 >> AHCI_P_CMD_CCS_SHIFT;
1716 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot ||
1717 ch->fbs_enabled || ch->wrongccs)
1718 slot->state = AHCI_SLOT_EXECUTING;
1719 else if ((ch->rslots & (1 << ccs)) == 0) {
1720 ch->wrongccs = 1;
1721 slot->state = AHCI_SLOT_EXECUTING;
1722 }
1723
1724 callout_reset_sbt(&slot->timeout,
1725 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0,
1726 (timeout_t*)ahci_timeout, slot, 0);
1727 return;
1728 }
1729
1730 device_printf(dev, "Timeout on slot %d port %d\n",
1731 slot->slot, slot->ccb->ccb_h.target_id & 0x0f);
1732 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x "
1733 "serr %08x cmd %08x\n",
1734 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI),
1735 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
1736 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR),
1737 ATA_INL(ch->r_mem, AHCI_P_CMD));
1738
1739 /* Handle frozen command. */
1740 if (ch->frozen) {
1741 union ccb *fccb = ch->frozen;
1742 ch->frozen = NULL;
1743 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1744 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1745 xpt_freeze_devq(fccb->ccb_h.path, 1);
1746 fccb->ccb_h.status |= CAM_DEV_QFRZN;
1747 }
1748 ahci_done(ch, fccb);
1749 }
1750 if (!ch->fbs_enabled && !ch->wrongccs) {
1751 /* Without FBS we know real timeout source. */
1752 ch->fatalerr = 1;
1753 /* Handle command with timeout. */
1754 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT);
1755 /* Handle the rest of commands. */
1756 for (i = 0; i < ch->numslots; i++) {
1757 /* Do we have a running request on slot? */
1758 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
1759 continue;
1760 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
1761 }
1762 } else {
1763 /* With FBS we wait for other commands timeout and pray. */
1764 if (ch->toslots == 0)
1765 xpt_freeze_simq(ch->sim, 1);
1766 ch->toslots |= (1 << slot->slot);
1767 if ((ch->rslots & ~ch->toslots) == 0)
1768 ahci_process_timeout(ch);
1769 else
1770 device_printf(dev, " ... waiting for slots %08x\n",
1771 ch->rslots & ~ch->toslots);
1772 }
1773 }
1774
1775 /* Must be called with channel locked. */
1776 static void
1777 ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et)
1778 {
1779 struct ahci_channel *ch = slot->ch;
1780 union ccb *ccb = slot->ccb;
1781 struct ahci_cmd_list *clp;
1782 int lastto;
1783 uint32_t sig;
1784
1785 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
1786 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1787 clp = (struct ahci_cmd_list *)
1788 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot));
1789 /* Read result registers to the result struct
1790 * May be incorrect if several commands finished same time,
1791 * so read only when sure or have to.
1792 */
1793 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1794 struct ata_res *res = &ccb->ataio.res;
1795
1796 if ((et == AHCI_ERR_TFE) ||
1797 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) {
1798 u_int8_t *fis = ch->dma.rfis + 0x40;
1799
1800 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
1801 BUS_DMASYNC_POSTREAD);
1802 if (ch->fbs_enabled) {
1803 fis += ccb->ccb_h.target_id * 256;
1804 res->status = fis[2];
1805 res->error = fis[3];
1806 } else {
1807 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD);
1808
1809 res->status = tfd;
1810 res->error = tfd >> 8;
1811 }
1812 res->lba_low = fis[4];
1813 res->lba_mid = fis[5];
1814 res->lba_high = fis[6];
1815 res->device = fis[7];
1816 res->lba_low_exp = fis[8];
1817 res->lba_mid_exp = fis[9];
1818 res->lba_high_exp = fis[10];
1819 res->sector_count = fis[12];
1820 res->sector_count_exp = fis[13];
1821
1822 /*
1823 * Some weird controllers do not return signature in
1824 * FIS receive area. Read it from PxSIG register.
1825 */
1826 if ((ch->quirks & AHCI_Q_ALTSIG) &&
1827 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
1828 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) {
1829 sig = ATA_INL(ch->r_mem, AHCI_P_SIG);
1830 res->lba_high = sig >> 24;
1831 res->lba_mid = sig >> 16;
1832 res->lba_low = sig >> 8;
1833 res->sector_count = sig;
1834 }
1835 } else
1836 bzero(res, sizeof(*res));
1837 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 &&
1838 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
1839 (ch->quirks & AHCI_Q_NOCOUNT) == 0) {
1840 ccb->ataio.resid =
1841 ccb->ataio.dxfer_len - le32toh(clp->bytecount);
1842 }
1843 } else {
1844 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
1845 (ch->quirks & AHCI_Q_NOCOUNT) == 0) {
1846 ccb->csio.resid =
1847 ccb->csio.dxfer_len - le32toh(clp->bytecount);
1848 }
1849 }
1850 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1851 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1852 (ccb->ccb_h.flags & CAM_DIR_IN) ?
1853 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1854 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map);
1855 }
1856 if (et != AHCI_ERR_NONE)
1857 ch->eslots |= (1 << slot->slot);
1858 /* In case of error, freeze device for proper recovery. */
1859 if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) &&
1860 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) {
1861 xpt_freeze_devq(ccb->ccb_h.path, 1);
1862 ccb->ccb_h.status |= CAM_DEV_QFRZN;
1863 }
1864 /* Set proper result status. */
1865 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1866 switch (et) {
1867 case AHCI_ERR_NONE:
1868 ccb->ccb_h.status |= CAM_REQ_CMP;
1869 if (ccb->ccb_h.func_code == XPT_SCSI_IO)
1870 ccb->csio.scsi_status = SCSI_STATUS_OK;
1871 break;
1872 case AHCI_ERR_INVALID:
1873 ch->fatalerr = 1;
1874 ccb->ccb_h.status |= CAM_REQ_INVALID;
1875 break;
1876 case AHCI_ERR_INNOCENT:
1877 ccb->ccb_h.status |= CAM_REQUEUE_REQ;
1878 break;
1879 case AHCI_ERR_TFE:
1880 case AHCI_ERR_NCQ:
1881 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
1882 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
1883 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
1884 } else {
1885 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR;
1886 }
1887 break;
1888 case AHCI_ERR_SATA:
1889 ch->fatalerr = 1;
1890 if (!ch->recoverycmd) {
1891 xpt_freeze_simq(ch->sim, 1);
1892 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1893 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
1894 }
1895 ccb->ccb_h.status |= CAM_UNCOR_PARITY;
1896 break;
1897 case AHCI_ERR_TIMEOUT:
1898 if (!ch->recoverycmd) {
1899 xpt_freeze_simq(ch->sim, 1);
1900 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1901 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
1902 }
1903 ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
1904 break;
1905 default:
1906 ch->fatalerr = 1;
1907 ccb->ccb_h.status |= CAM_REQ_CMP_ERR;
1908 }
1909 /* Free slot. */
1910 ch->oslots &= ~(1 << slot->slot);
1911 ch->rslots &= ~(1 << slot->slot);
1912 ch->aslots &= ~(1 << slot->slot);
1913 slot->state = AHCI_SLOT_EMPTY;
1914 slot->ccb = NULL;
1915 /* Update channel stats. */
1916 ch->numrslots--;
1917 ch->numrslotspd[ccb->ccb_h.target_id]--;
1918 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1919 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1920 ch->numtslots--;
1921 ch->numtslotspd[ccb->ccb_h.target_id]--;
1922 }
1923 /* Cancel timeout state if request completed normally. */
1924 if (et != AHCI_ERR_TIMEOUT) {
1925 lastto = (ch->toslots == (1 << slot->slot));
1926 ch->toslots &= ~(1 << slot->slot);
1927 if (lastto)
1928 xpt_release_simq(ch->sim, TRUE);
1929 }
1930 /* If it was first request of reset sequence and there is no error,
1931 * proceed to second request. */
1932 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1933 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
1934 (ccb->ataio.cmd.control & ATA_A_RESET) &&
1935 et == AHCI_ERR_NONE) {
1936 ccb->ataio.cmd.control &= ~ATA_A_RESET;
1937 ahci_begin_transaction(ch, ccb);
1938 return;
1939 }
1940 /* If it was our READ LOG command - process it. */
1941 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) {
1942 ahci_process_read_log(ch, ccb);
1943 /* If it was our REQUEST SENSE command - process it. */
1944 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) {
1945 ahci_process_request_sense(ch, ccb);
1946 /* If it was NCQ or ATAPI command error, put result on hold. */
1947 } else if (et == AHCI_ERR_NCQ ||
1948 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR &&
1949 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) {
1950 ch->hold[slot->slot] = ccb;
1951 ch->numhslots++;
1952 } else
1953 ahci_done(ch, ccb);
1954 /* If we have no other active commands, ... */
1955 if (ch->rslots == 0) {
1956 /* if there was fatal error - reset port. */
1957 if (ch->toslots != 0 || ch->fatalerr) {
1958 ahci_reset(ch);
1959 } else {
1960 /* if we have slots in error, we can reinit port. */
1961 if (ch->eslots != 0) {
1962 ahci_stop(ch);
1963 ahci_clo(ch);
1964 ahci_start(ch, 1);
1965 }
1966 /* if there commands on hold, we can do READ LOG. */
1967 if (!ch->recoverycmd && ch->numhslots)
1968 ahci_issue_recovery(ch);
1969 }
1970 /* If all the rest of commands are in timeout - give them chance. */
1971 } else if ((ch->rslots & ~ch->toslots) == 0 &&
1972 et != AHCI_ERR_TIMEOUT)
1973 ahci_rearm_timeout(ch);
1974 /* Unfreeze frozen command. */
1975 if (ch->frozen && !ahci_check_collision(ch, ch->frozen)) {
1976 union ccb *fccb = ch->frozen;
1977 ch->frozen = NULL;
1978 ahci_begin_transaction(ch, fccb);
1979 xpt_release_simq(ch->sim, TRUE);
1980 }
1981 /* Start PM timer. */
1982 if (ch->numrslots == 0 && ch->pm_level > 3 &&
1983 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) {
1984 callout_schedule(&ch->pm_timer,
1985 (ch->pm_level == 4) ? hz / 1000 : hz / 8);
1986 }
1987 }
1988
1989 static void
1990 ahci_issue_recovery(struct ahci_channel *ch)
1991 {
1992 union ccb *ccb;
1993 struct ccb_ataio *ataio;
1994 struct ccb_scsiio *csio;
1995 int i;
1996
1997 /* Find some held command. */
1998 for (i = 0; i < ch->numslots; i++) {
1999 if (ch->hold[i])
2000 break;
2001 }
2002 ccb = xpt_alloc_ccb_nowait();
2003 if (ccb == NULL) {
2004 device_printf(ch->dev, "Unable to allocate recovery command\n");
2005 completeall:
2006 /* We can't do anything -- complete held commands. */
2007 for (i = 0; i < ch->numslots; i++) {
2008 if (ch->hold[i] == NULL)
2009 continue;
2010 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2011 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL;
2012 ahci_done(ch, ch->hold[i]);
2013 ch->hold[i] = NULL;
2014 ch->numhslots--;
2015 }
2016 ahci_reset(ch);
2017 return;
2018 }
2019 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */
2020 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
2021 /* READ LOG */
2022 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG;
2023 ccb->ccb_h.func_code = XPT_ATA_IO;
2024 ccb->ccb_h.flags = CAM_DIR_IN;
2025 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
2026 ataio = &ccb->ataio;
2027 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT);
2028 if (ataio->data_ptr == NULL) {
2029 xpt_free_ccb(ccb);
2030 device_printf(ch->dev,
2031 "Unable to allocate memory for READ LOG command\n");
2032 goto completeall;
2033 }
2034 ataio->dxfer_len = 512;
2035 bzero(&ataio->cmd, sizeof(ataio->cmd));
2036 ataio->cmd.flags = CAM_ATAIO_48BIT;
2037 ataio->cmd.command = 0x2F; /* READ LOG EXT */
2038 ataio->cmd.sector_count = 1;
2039 ataio->cmd.sector_count_exp = 0;
2040 ataio->cmd.lba_low = 0x10;
2041 ataio->cmd.lba_mid = 0;
2042 ataio->cmd.lba_mid_exp = 0;
2043 } else {
2044 /* REQUEST SENSE */
2045 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE;
2046 ccb->ccb_h.recovery_slot = i;
2047 ccb->ccb_h.func_code = XPT_SCSI_IO;
2048 ccb->ccb_h.flags = CAM_DIR_IN;
2049 ccb->ccb_h.status = 0;
2050 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
2051 csio = &ccb->csio;
2052 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data;
2053 csio->dxfer_len = ch->hold[i]->csio.sense_len;
2054 csio->cdb_len = 6;
2055 bzero(&csio->cdb_io, sizeof(csio->cdb_io));
2056 csio->cdb_io.cdb_bytes[0] = 0x03;
2057 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len;
2058 }
2059 /* Freeze SIM while doing recovery. */
2060 ch->recoverycmd = 1;
2061 xpt_freeze_simq(ch->sim, 1);
2062 ahci_begin_transaction(ch, ccb);
2063 }
2064
2065 static void
2066 ahci_process_read_log(struct ahci_channel *ch, union ccb *ccb)
2067 {
2068 uint8_t *data;
2069 struct ata_res *res;
2070 int i;
2071
2072 ch->recoverycmd = 0;
2073
2074 data = ccb->ataio.data_ptr;
2075 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP &&
2076 (data[0] & 0x80) == 0) {
2077 for (i = 0; i < ch->numslots; i++) {
2078 if (!ch->hold[i])
2079 continue;
2080 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO)
2081 continue;
2082 if ((data[0] & 0x1F) == i) {
2083 res = &ch->hold[i]->ataio.res;
2084 res->status = data[2];
2085 res->error = data[3];
2086 res->lba_low = data[4];
2087 res->lba_mid = data[5];
2088 res->lba_high = data[6];
2089 res->device = data[7];
2090 res->lba_low_exp = data[8];
2091 res->lba_mid_exp = data[9];
2092 res->lba_high_exp = data[10];
2093 res->sector_count = data[12];
2094 res->sector_count_exp = data[13];
2095 } else {
2096 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2097 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ;
2098 }
2099 ahci_done(ch, ch->hold[i]);
2100 ch->hold[i] = NULL;
2101 ch->numhslots--;
2102 }
2103 } else {
2104 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP)
2105 device_printf(ch->dev, "Error while READ LOG EXT\n");
2106 else if ((data[0] & 0x80) == 0) {
2107 device_printf(ch->dev, "Non-queued command error in READ LOG EXT\n");
2108 }
2109 for (i = 0; i < ch->numslots; i++) {
2110 if (!ch->hold[i])
2111 continue;
2112 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO)
2113 continue;
2114 ahci_done(ch, ch->hold[i]);
2115 ch->hold[i] = NULL;
2116 ch->numhslots--;
2117 }
2118 }
2119 free(ccb->ataio.data_ptr, M_AHCI);
2120 xpt_free_ccb(ccb);
2121 xpt_release_simq(ch->sim, TRUE);
2122 }
2123
2124 static void
2125 ahci_process_request_sense(struct ahci_channel *ch, union ccb *ccb)
2126 {
2127 int i;
2128
2129 ch->recoverycmd = 0;
2130
2131 i = ccb->ccb_h.recovery_slot;
2132 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) {
2133 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID;
2134 } else {
2135 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2136 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL;
2137 }
2138 ahci_done(ch, ch->hold[i]);
2139 ch->hold[i] = NULL;
2140 ch->numhslots--;
2141 xpt_free_ccb(ccb);
2142 xpt_release_simq(ch->sim, TRUE);
2143 }
2144
2145 static void
2146 ahci_start(struct ahci_channel *ch, int fbs)
2147 {
2148 u_int32_t cmd;
2149
2150 /* Run the channel start callback, if any. */
2151 if (ch->start)
2152 ch->start(ch);
2153
2154 /* Clear SATA error register */
2155 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF);
2156 /* Clear any interrupts pending on this channel */
2157 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF);
2158 /* Configure FIS-based switching if supported. */
2159 if (ch->chcaps & AHCI_P_CMD_FBSCP) {
2160 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0;
2161 ATA_OUTL(ch->r_mem, AHCI_P_FBS,
2162 ch->fbs_enabled ? AHCI_P_FBS_EN : 0);
2163 }
2164 /* Start operations on this channel */
2165 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2166 cmd &= ~AHCI_P_CMD_PMA;
2167 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST |
2168 (ch->pm_present ? AHCI_P_CMD_PMA : 0));
2169 }
2170
2171 static void
2172 ahci_stop(struct ahci_channel *ch)
2173 {
2174 u_int32_t cmd;
2175 int timeout;
2176
2177 /* Kill all activity on this channel */
2178 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2179 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST);
2180 /* Wait for activity stop. */
2181 timeout = 0;
2182 do {
2183 DELAY(10);
2184 if (timeout++ > 50000) {
2185 device_printf(ch->dev, "stopping AHCI engine failed\n");
2186 break;
2187 }
2188 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR);
2189 ch->eslots = 0;
2190 }
2191
2192 static void
2193 ahci_clo(struct ahci_channel *ch)
2194 {
2195 u_int32_t cmd;
2196 int timeout;
2197
2198 /* Issue Command List Override if supported */
2199 if (ch->caps & AHCI_CAP_SCLO) {
2200 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2201 cmd |= AHCI_P_CMD_CLO;
2202 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd);
2203 timeout = 0;
2204 do {
2205 DELAY(10);
2206 if (timeout++ > 50000) {
2207 device_printf(ch->dev, "executing CLO failed\n");
2208 break;
2209 }
2210 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO);
2211 }
2212 }
2213
2214 static void
2215 ahci_stop_fr(struct ahci_channel *ch)
2216 {
2217 u_int32_t cmd;
2218 int timeout;
2219
2220 /* Kill all FIS reception on this channel */
2221 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2222 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE);
2223 /* Wait for FIS reception stop. */
2224 timeout = 0;
2225 do {
2226 DELAY(10);
2227 if (timeout++ > 50000) {
2228 device_printf(ch->dev, "stopping AHCI FR engine failed\n");
2229 break;
2230 }
2231 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR);
2232 }
2233
2234 static void
2235 ahci_start_fr(struct ahci_channel *ch)
2236 {
2237 u_int32_t cmd;
2238
2239 /* Start FIS reception on this channel */
2240 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2241 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE);
2242 }
2243
2244 static int
2245 ahci_wait_ready(struct ahci_channel *ch, int t, int t0)
2246 {
2247 int timeout = 0;
2248 uint32_t val;
2249
2250 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) &
2251 (ATA_S_BUSY | ATA_S_DRQ)) {
2252 if (timeout > t) {
2253 if (t != 0) {
2254 device_printf(ch->dev,
2255 "AHCI reset: device not ready after %dms "
2256 "(tfd = %08x)\n",
2257 MAX(t, 0) + t0, val);
2258 }
2259 return (EBUSY);
2260 }
2261 DELAY(1000);
2262 timeout++;
2263 }
2264 if (bootverbose)
2265 device_printf(ch->dev, "AHCI reset: device ready after %dms\n",
2266 timeout + t0);
2267 return (0);
2268 }
2269
2270 static void
2271 ahci_reset_to(void *arg)
2272 {
2273 struct ahci_channel *ch = arg;
2274
2275 if (ch->resetting == 0)
2276 return;
2277 ch->resetting--;
2278 if (ahci_wait_ready(ch, ch->resetting == 0 ? -1 : 0,
2279 (310 - ch->resetting) * 100) == 0) {
2280 ch->resetting = 0;
2281 ahci_start(ch, 1);
2282 xpt_release_simq(ch->sim, TRUE);
2283 return;
2284 }
2285 if (ch->resetting == 0) {
2286 ahci_clo(ch);
2287 ahci_start(ch, 1);
2288 xpt_release_simq(ch->sim, TRUE);
2289 return;
2290 }
2291 callout_schedule(&ch->reset_timer, hz / 10);
2292 }
2293
2294 static void
2295 ahci_reset(struct ahci_channel *ch)
2296 {
2297 struct ahci_controller *ctlr = device_get_softc(device_get_parent(ch->dev));
2298 int i;
2299
2300 xpt_freeze_simq(ch->sim, 1);
2301 if (bootverbose)
2302 device_printf(ch->dev, "AHCI reset...\n");
2303 /* Forget about previous reset. */
2304 if (ch->resetting) {
2305 ch->resetting = 0;
2306 callout_stop(&ch->reset_timer);
2307 xpt_release_simq(ch->sim, TRUE);
2308 }
2309 /* Requeue freezed command. */
2310 if (ch->frozen) {
2311 union ccb *fccb = ch->frozen;
2312 ch->frozen = NULL;
2313 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
2314 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
2315 xpt_freeze_devq(fccb->ccb_h.path, 1);
2316 fccb->ccb_h.status |= CAM_DEV_QFRZN;
2317 }
2318 ahci_done(ch, fccb);
2319 }
2320 /* Kill the engine and requeue all running commands. */
2321 ahci_stop(ch);
2322 for (i = 0; i < ch->numslots; i++) {
2323 /* Do we have a running request on slot? */
2324 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
2325 continue;
2326 /* XXX; Commands in loading state. */
2327 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
2328 }
2329 for (i = 0; i < ch->numslots; i++) {
2330 if (!ch->hold[i])
2331 continue;
2332 ahci_done(ch, ch->hold[i]);
2333 ch->hold[i] = NULL;
2334 ch->numhslots--;
2335 }
2336 if (ch->toslots != 0)
2337 xpt_release_simq(ch->sim, TRUE);
2338 ch->eslots = 0;
2339 ch->toslots = 0;
2340 ch->wrongccs = 0;
2341 ch->fatalerr = 0;
2342 /* Tell the XPT about the event */
2343 xpt_async(AC_BUS_RESET, ch->path, NULL);
2344 /* Disable port interrupts */
2345 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
2346 /* Reset and reconnect PHY, */
2347 if (!ahci_sata_phy_reset(ch)) {
2348 if (bootverbose)
2349 device_printf(ch->dev,
2350 "AHCI reset: device not found\n");
2351 ch->devices = 0;
2352 /* Enable wanted port interrupts */
2353 ATA_OUTL(ch->r_mem, AHCI_P_IE,
2354 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) |
2355 AHCI_P_IX_PRC | AHCI_P_IX_PC));
2356 xpt_release_simq(ch->sim, TRUE);
2357 return;
2358 }
2359 if (bootverbose)
2360 device_printf(ch->dev, "AHCI reset: device found\n");
2361 /* Wait for clearing busy status. */
2362 if (ahci_wait_ready(ch, dumping ? 31000 : 0, 0)) {
2363 if (dumping)
2364 ahci_clo(ch);
2365 else
2366 ch->resetting = 310;
2367 }
2368 ch->devices = 1;
2369 /* Enable wanted port interrupts */
2370 ATA_OUTL(ch->r_mem, AHCI_P_IE,
2371 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) |
2372 AHCI_P_IX_TFE | AHCI_P_IX_HBF |
2373 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF |
2374 ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC |
2375 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) |
2376 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR)));
2377 if (ch->resetting)
2378 callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, ch);
2379 else {
2380 ahci_start(ch, 1);
2381 xpt_release_simq(ch->sim, TRUE);
2382 }
2383 }
2384
2385 static int
2386 ahci_setup_fis(struct ahci_channel *ch, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag)
2387 {
2388 u_int8_t *fis = &ctp->cfis[0];
2389
2390 bzero(fis, 20);
2391 fis[0] = 0x27; /* host to device */
2392 fis[1] = (ccb->ccb_h.target_id & 0x0f);
2393 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
2394 fis[1] |= 0x80;
2395 fis[2] = ATA_PACKET_CMD;
2396 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2397 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA)
2398 fis[3] = ATA_F_DMA;
2399 else {
2400 fis[5] = ccb->csio.dxfer_len;
2401 fis[6] = ccb->csio.dxfer_len >> 8;
2402 }
2403 fis[7] = ATA_D_LBA;
2404 fis[15] = ATA_A_4BIT;
2405 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ?
2406 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes,
2407 ctp->acmd, ccb->csio.cdb_len);
2408 bzero(ctp->acmd + ccb->csio.cdb_len, 32 - ccb->csio.cdb_len);
2409 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) {
2410 fis[1] |= 0x80;
2411 fis[2] = ccb->ataio.cmd.command;
2412 fis[3] = ccb->ataio.cmd.features;
2413 fis[4] = ccb->ataio.cmd.lba_low;
2414 fis[5] = ccb->ataio.cmd.lba_mid;
2415 fis[6] = ccb->ataio.cmd.lba_high;
2416 fis[7] = ccb->ataio.cmd.device;
2417 fis[8] = ccb->ataio.cmd.lba_low_exp;
2418 fis[9] = ccb->ataio.cmd.lba_mid_exp;
2419 fis[10] = ccb->ataio.cmd.lba_high_exp;
2420 fis[11] = ccb->ataio.cmd.features_exp;
2421 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
2422 fis[12] = tag << 3;
2423 } else {
2424 fis[12] = ccb->ataio.cmd.sector_count;
2425 }
2426 fis[13] = ccb->ataio.cmd.sector_count_exp;
2427 fis[15] = ATA_A_4BIT;
2428 } else {
2429 fis[15] = ccb->ataio.cmd.control;
2430 }
2431 if (ccb->ataio.ata_flags & ATA_FLAG_AUX) {
2432 fis[16] = ccb->ataio.aux & 0xff;
2433 fis[17] = (ccb->ataio.aux >> 8) & 0xff;
2434 fis[18] = (ccb->ataio.aux >> 16) & 0xff;
2435 fis[19] = (ccb->ataio.aux >> 24) & 0xff;
2436 }
2437 return (20);
2438 }
2439
2440 static int
2441 ahci_sata_connect(struct ahci_channel *ch)
2442 {
2443 u_int32_t status;
2444 int timeout, found = 0;
2445
2446 /* Wait up to 100ms for "connect well" */
2447 for (timeout = 0; timeout < 1000 ; timeout++) {
2448 status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
2449 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE)
2450 found = 1;
2451 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) &&
2452 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) &&
2453 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE))
2454 break;
2455 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) {
2456 if (bootverbose) {
2457 device_printf(ch->dev, "SATA offline status=%08x\n",
2458 status);
2459 }
2460 return (0);
2461 }
2462 if (found == 0 && timeout >= 100)
2463 break;
2464 DELAY(100);
2465 }
2466 if (timeout >= 1000 || !found) {
2467 if (bootverbose) {
2468 device_printf(ch->dev,
2469 "SATA connect timeout time=%dus status=%08x\n",
2470 timeout * 100, status);
2471 }
2472 return (0);
2473 }
2474 if (bootverbose) {
2475 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n",
2476 timeout * 100, status);
2477 }
2478 /* Clear SATA error register */
2479 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff);
2480 return (1);
2481 }
2482
2483 static int
2484 ahci_sata_phy_reset(struct ahci_channel *ch)
2485 {
2486 int sata_rev;
2487 uint32_t val;
2488
2489 if (ch->listening) {
2490 val = ATA_INL(ch->r_mem, AHCI_P_CMD);
2491 val |= AHCI_P_CMD_SUD;
2492 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val);
2493 ch->listening = 0;
2494 }
2495 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision;
2496 if (sata_rev == 1)
2497 val = ATA_SC_SPD_SPEED_GEN1;
2498 else if (sata_rev == 2)
2499 val = ATA_SC_SPD_SPEED_GEN2;
2500 else if (sata_rev == 3)
2501 val = ATA_SC_SPD_SPEED_GEN3;
2502 else
2503 val = 0;
2504 ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
2505 ATA_SC_DET_RESET | val |
2506 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER);
2507 DELAY(1000);
2508 ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
2509 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 :
2510 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)));
2511 if (!ahci_sata_connect(ch)) {
2512 if (ch->caps & AHCI_CAP_SSS) {
2513 val = ATA_INL(ch->r_mem, AHCI_P_CMD);
2514 val &= ~AHCI_P_CMD_SUD;
2515 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val);
2516 ch->listening = 1;
2517 } else if (ch->pm_level > 0)
2518 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
2519 return (0);
2520 }
2521 return (1);
2522 }
2523
2524 static int
2525 ahci_check_ids(struct ahci_channel *ch, union ccb *ccb)
2526 {
2527
2528 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) {
2529 ccb->ccb_h.status = CAM_TID_INVALID;
2530 ahci_done(ch, ccb);
2531 return (-1);
2532 }
2533 if (ccb->ccb_h.target_lun != 0) {
2534 ccb->ccb_h.status = CAM_LUN_INVALID;
2535 ahci_done(ch, ccb);
2536 return (-1);
2537 }
2538 return (0);
2539 }
2540
2541 static void
2542 ahciaction(struct cam_sim *sim, union ccb *ccb)
2543 {
2544 struct ahci_channel *ch;
2545
2546 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n",
2547 ccb->ccb_h.func_code));
2548
2549 ch = (struct ahci_channel *)cam_sim_softc(sim);
2550 switch (ccb->ccb_h.func_code) {
2551 /* Common cases first */
2552 case XPT_ATA_IO: /* Execute the requested I/O operation */
2553 case XPT_SCSI_IO:
2554 if (ahci_check_ids(ch, ccb))
2555 return;
2556 if (ch->devices == 0 ||
2557 (ch->pm_present == 0 &&
2558 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) {
2559 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2560 break;
2561 }
2562 ccb->ccb_h.recovery_type = RECOVERY_NONE;
2563 /* Check for command collision. */
2564 if (ahci_check_collision(ch, ccb)) {
2565 /* Freeze command. */
2566 ch->frozen = ccb;
2567 /* We have only one frozen slot, so freeze simq also. */
2568 xpt_freeze_simq(ch->sim, 1);
2569 return;
2570 }
2571 ahci_begin_transaction(ch, ccb);
2572 return;
2573 case XPT_ABORT: /* Abort the specified CCB */
2574 /* XXX Implement */
2575 ccb->ccb_h.status = CAM_REQ_INVALID;
2576 break;
2577 case XPT_SET_TRAN_SETTINGS:
2578 {
2579 struct ccb_trans_settings *cts = &ccb->cts;
2580 struct ahci_device *d;
2581
2582 if (ahci_check_ids(ch, ccb))
2583 return;
2584 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2585 d = &ch->curr[ccb->ccb_h.target_id];
2586 else
2587 d = &ch->user[ccb->ccb_h.target_id];
2588 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION)
2589 d->revision = cts->xport_specific.sata.revision;
2590 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE)
2591 d->mode = cts->xport_specific.sata.mode;
2592 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT)
2593 d->bytecount = min(8192, cts->xport_specific.sata.bytecount);
2594 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS)
2595 d->tags = min(ch->numslots, cts->xport_specific.sata.tags);
2596 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM)
2597 ch->pm_present = cts->xport_specific.sata.pm_present;
2598 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI)
2599 d->atapi = cts->xport_specific.sata.atapi;
2600 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS)
2601 d->caps = cts->xport_specific.sata.caps;
2602 ccb->ccb_h.status = CAM_REQ_CMP;
2603 break;
2604 }
2605 case XPT_GET_TRAN_SETTINGS:
2606 /* Get default/user set transfer settings for the target */
2607 {
2608 struct ccb_trans_settings *cts = &ccb->cts;
2609 struct ahci_device *d;
2610 uint32_t status;
2611
2612 if (ahci_check_ids(ch, ccb))
2613 return;
2614 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2615 d = &ch->curr[ccb->ccb_h.target_id];
2616 else
2617 d = &ch->user[ccb->ccb_h.target_id];
2618 cts->protocol = PROTO_UNSPECIFIED;
2619 cts->protocol_version = PROTO_VERSION_UNSPECIFIED;
2620 cts->transport = XPORT_SATA;
2621 cts->transport_version = XPORT_VERSION_UNSPECIFIED;
2622 cts->proto_specific.valid = 0;
2623 cts->xport_specific.sata.valid = 0;
2624 if (cts->type == CTS_TYPE_CURRENT_SETTINGS &&
2625 (ccb->ccb_h.target_id == 15 ||
2626 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) {
2627 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK;
2628 if (status & 0x0f0) {
2629 cts->xport_specific.sata.revision =
2630 (status & 0x0f0) >> 4;
2631 cts->xport_specific.sata.valid |=
2632 CTS_SATA_VALID_REVISION;
2633 }
2634 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D;
2635 if (ch->pm_level) {
2636 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC))
2637 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ;
2638 if (ch->caps2 & AHCI_CAP2_APST)
2639 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST;
2640 }
2641 if ((ch->caps & AHCI_CAP_SNCQ) &&
2642 (ch->quirks & AHCI_Q_NOAA) == 0)
2643 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA;
2644 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN;
2645 cts->xport_specific.sata.caps &=
2646 ch->user[ccb->ccb_h.target_id].caps;
2647 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2648 } else {
2649 cts->xport_specific.sata.revision = d->revision;
2650 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION;
2651 cts->xport_specific.sata.caps = d->caps;
2652 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2653 }
2654 cts->xport_specific.sata.mode = d->mode;
2655 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE;
2656 cts->xport_specific.sata.bytecount = d->bytecount;
2657 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT;
2658 cts->xport_specific.sata.pm_present = ch->pm_present;
2659 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM;
2660 cts->xport_specific.sata.tags = d->tags;
2661 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS;
2662 cts->xport_specific.sata.atapi = d->atapi;
2663 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI;
2664 ccb->ccb_h.status = CAM_REQ_CMP;
2665 break;
2666 }
2667 case XPT_RESET_BUS: /* Reset the specified SCSI bus */
2668 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
2669 ahci_reset(ch);
2670 ccb->ccb_h.status = CAM_REQ_CMP;
2671 break;
2672 case XPT_TERM_IO: /* Terminate the I/O process */
2673 /* XXX Implement */
2674 ccb->ccb_h.status = CAM_REQ_INVALID;
2675 break;
2676 case XPT_PATH_INQ: /* Path routing inquiry */
2677 {
2678 struct ccb_pathinq *cpi = &ccb->cpi;
2679
2680 cpi->version_num = 1; /* XXX??? */
2681 cpi->hba_inquiry = PI_SDTR_ABLE;
2682 if (ch->caps & AHCI_CAP_SNCQ)
2683 cpi->hba_inquiry |= PI_TAG_ABLE;
2684 if (ch->caps & AHCI_CAP_SPM)
2685 cpi->hba_inquiry |= PI_SATAPM;
2686 cpi->target_sprt = 0;
2687 cpi->hba_misc = PIM_SEQSCAN | PIM_UNMAPPED;
2688 if ((ch->quirks & AHCI_Q_NOAUX) == 0)
2689 cpi->hba_misc |= PIM_ATA_EXT;
2690 cpi->hba_eng_cnt = 0;
2691 if (ch->caps & AHCI_CAP_SPM)
2692 cpi->max_target = 15;
2693 else
2694 cpi->max_target = 0;
2695 cpi->max_lun = 0;
2696 cpi->initiator_id = 0;
2697 cpi->bus_id = cam_sim_bus(sim);
2698 cpi->base_transfer_speed = 150000;
2699 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2700 strlcpy(cpi->hba_vid, "AHCI", HBA_IDLEN);
2701 strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
2702 cpi->unit_number = cam_sim_unit(sim);
2703 cpi->transport = XPORT_SATA;
2704 cpi->transport_version = XPORT_VERSION_UNSPECIFIED;
2705 cpi->protocol = PROTO_ATA;
2706 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED;
2707 cpi->maxio = MAXPHYS;
2708 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */
2709 if (ch->quirks & AHCI_Q_MAXIO_64K)
2710 cpi->maxio = min(cpi->maxio, 128 * 512);
2711 cpi->hba_vendor = ch->vendorid;
2712 cpi->hba_device = ch->deviceid;
2713 cpi->hba_subvendor = ch->subvendorid;
2714 cpi->hba_subdevice = ch->subdeviceid;
2715 cpi->ccb_h.status = CAM_REQ_CMP;
2716 break;
2717 }
2718 default:
2719 ccb->ccb_h.status = CAM_REQ_INVALID;
2720 break;
2721 }
2722 ahci_done(ch, ccb);
2723 }
2724
2725 static void
2726 ahcipoll(struct cam_sim *sim)
2727 {
2728 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim);
2729 uint32_t istatus;
2730
2731 /* Read interrupt statuses and process if any. */
2732 istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
2733 if (istatus != 0)
2734 ahci_ch_intr_main(ch, istatus);
2735 if (ch->resetting != 0 &&
2736 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) {
2737 ch->resetpolldiv = 1000;
2738 ahci_reset_to(ch);
2739 }
2740 }
2741
2742 devclass_t ahci_devclass;
2743
2744 MODULE_VERSION(ahci, 1);
2745 MODULE_DEPEND(ahci, cam, 1, 1, 1);
Cache object: 3d2608df79b49a405c5a1b7193eb773e
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