FreeBSD/Linux Kernel Cross Reference
sys/dev/ahci/ahci.c
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer,
12 * without modification, immediately at the beginning of the file.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD: releng/12.0/sys/dev/ahci/ahci.c 336760 2018-07-27 13:11:05Z luporl $");
31
32 #include <sys/param.h>
33 #include <sys/module.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/bus.h>
37 #include <sys/conf.h>
38 #include <sys/endian.h>
39 #include <sys/malloc.h>
40 #include <sys/lock.h>
41 #include <sys/mutex.h>
42 #include <machine/stdarg.h>
43 #include <machine/resource.h>
44 #include <machine/bus.h>
45 #include <sys/rman.h>
46 #include "ahci.h"
47
48 #include <cam/cam.h>
49 #include <cam/cam_ccb.h>
50 #include <cam/cam_sim.h>
51 #include <cam/cam_xpt_sim.h>
52 #include <cam/cam_debug.h>
53
54 /* local prototypes */
55 static void ahci_intr(void *data);
56 static void ahci_intr_one(void *data);
57 static void ahci_intr_one_edge(void *data);
58 static int ahci_ch_init(device_t dev);
59 static int ahci_ch_deinit(device_t dev);
60 static int ahci_ch_suspend(device_t dev);
61 static int ahci_ch_resume(device_t dev);
62 static void ahci_ch_pm(void *arg);
63 static void ahci_ch_intr(void *arg);
64 static void ahci_ch_intr_direct(void *arg);
65 static void ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus);
66 static void ahci_begin_transaction(struct ahci_channel *ch, union ccb *ccb);
67 static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error);
68 static void ahci_execute_transaction(struct ahci_slot *slot);
69 static void ahci_timeout(struct ahci_slot *slot);
70 static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et);
71 static int ahci_setup_fis(struct ahci_channel *ch, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag);
72 static void ahci_dmainit(device_t dev);
73 static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
74 static void ahci_dmafini(device_t dev);
75 static void ahci_slotsalloc(device_t dev);
76 static void ahci_slotsfree(device_t dev);
77 static void ahci_reset(struct ahci_channel *ch);
78 static void ahci_start(struct ahci_channel *ch, int fbs);
79 static void ahci_stop(struct ahci_channel *ch);
80 static void ahci_clo(struct ahci_channel *ch);
81 static void ahci_start_fr(struct ahci_channel *ch);
82 static void ahci_stop_fr(struct ahci_channel *ch);
83
84 static int ahci_sata_connect(struct ahci_channel *ch);
85 static int ahci_sata_phy_reset(struct ahci_channel *ch);
86 static int ahci_wait_ready(struct ahci_channel *ch, int t, int t0);
87
88 static void ahci_issue_recovery(struct ahci_channel *ch);
89 static void ahci_process_read_log(struct ahci_channel *ch, union ccb *ccb);
90 static void ahci_process_request_sense(struct ahci_channel *ch, union ccb *ccb);
91
92 static void ahciaction(struct cam_sim *sim, union ccb *ccb);
93 static void ahcipoll(struct cam_sim *sim);
94
95 static MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers");
96
97 #define recovery_type spriv_field0
98 #define RECOVERY_NONE 0
99 #define RECOVERY_READ_LOG 1
100 #define RECOVERY_REQUEST_SENSE 2
101 #define recovery_slot spriv_field1
102
103 int
104 ahci_ctlr_setup(device_t dev)
105 {
106 struct ahci_controller *ctlr = device_get_softc(dev);
107 /* Clear interrupts */
108 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS));
109 /* Configure CCC */
110 if (ctlr->ccc) {
111 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI));
112 ATA_OUTL(ctlr->r_mem, AHCI_CCCC,
113 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) |
114 (4 << AHCI_CCCC_CC_SHIFT) |
115 AHCI_CCCC_EN);
116 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) &
117 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT;
118 if (bootverbose) {
119 device_printf(dev,
120 "CCC with %dms/4cmd enabled on vector %d\n",
121 ctlr->ccc, ctlr->cccv);
122 }
123 }
124 /* Enable AHCI interrupts */
125 ATA_OUTL(ctlr->r_mem, AHCI_GHC,
126 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE);
127 return (0);
128 }
129
130 int
131 ahci_ctlr_reset(device_t dev)
132 {
133 struct ahci_controller *ctlr = device_get_softc(dev);
134 int timeout;
135
136 /* Enable AHCI mode */
137 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
138 /* Reset AHCI controller */
139 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR);
140 for (timeout = 1000; timeout > 0; timeout--) {
141 DELAY(1000);
142 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0)
143 break;
144 }
145 if (timeout == 0) {
146 device_printf(dev, "AHCI controller reset failure\n");
147 return (ENXIO);
148 }
149 /* Reenable AHCI mode */
150 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
151
152 if (ctlr->quirks & AHCI_Q_RESTORE_CAP) {
153 /*
154 * Restore capability field.
155 * This is write to a read-only register to restore its state.
156 * On fully standard-compliant hardware this is not needed and
157 * this operation shall not take place. See ahci_pci.c for
158 * platforms using this quirk.
159 */
160 ATA_OUTL(ctlr->r_mem, AHCI_CAP, ctlr->caps);
161 }
162
163 return (0);
164 }
165
166
167 int
168 ahci_attach(device_t dev)
169 {
170 struct ahci_controller *ctlr = device_get_softc(dev);
171 int error, i, speed, unit;
172 uint32_t u, version;
173 device_t child;
174
175 ctlr->dev = dev;
176 ctlr->ccc = 0;
177 resource_int_value(device_get_name(dev),
178 device_get_unit(dev), "ccc", &ctlr->ccc);
179
180 /* Setup our own memory management for channels. */
181 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem);
182 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem);
183 ctlr->sc_iomem.rm_type = RMAN_ARRAY;
184 ctlr->sc_iomem.rm_descr = "I/O memory addresses";
185 if ((error = rman_init(&ctlr->sc_iomem)) != 0) {
186 ahci_free_mem(dev);
187 return (error);
188 }
189 if ((error = rman_manage_region(&ctlr->sc_iomem,
190 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) {
191 ahci_free_mem(dev);
192 rman_fini(&ctlr->sc_iomem);
193 return (error);
194 }
195 /* Get the HW capabilities */
196 version = ATA_INL(ctlr->r_mem, AHCI_VS);
197 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP);
198 if (version >= 0x00010200)
199 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2);
200 if (ctlr->caps & AHCI_CAP_EMS)
201 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL);
202
203 if (ctlr->quirks & AHCI_Q_FORCE_PI) {
204 /*
205 * Enable ports.
206 * The spec says that BIOS sets up bits corresponding to
207 * available ports. On platforms where this information
208 * is missing, the driver can define available ports on its own.
209 */
210 int nports = (ctlr->caps & AHCI_CAP_NPMASK) + 1;
211 int nmask = (1 << nports) - 1;
212
213 ATA_OUTL(ctlr->r_mem, AHCI_PI, nmask);
214 device_printf(dev, "Forcing PI to %d ports (mask = %x)\n",
215 nports, nmask);
216 }
217
218 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI);
219
220 /* Identify and set separate quirks for HBA and RAID f/w Marvells. */
221 if ((ctlr->quirks & AHCI_Q_ALTSIG) &&
222 (ctlr->caps & AHCI_CAP_SPM) == 0)
223 ctlr->quirks |= AHCI_Q_NOBSYRES;
224
225 if (ctlr->quirks & AHCI_Q_1CH) {
226 ctlr->caps &= ~AHCI_CAP_NPMASK;
227 ctlr->ichannels &= 0x01;
228 }
229 if (ctlr->quirks & AHCI_Q_2CH) {
230 ctlr->caps &= ~AHCI_CAP_NPMASK;
231 ctlr->caps |= 1;
232 ctlr->ichannels &= 0x03;
233 }
234 if (ctlr->quirks & AHCI_Q_4CH) {
235 ctlr->caps &= ~AHCI_CAP_NPMASK;
236 ctlr->caps |= 3;
237 ctlr->ichannels &= 0x0f;
238 }
239 ctlr->channels = MAX(flsl(ctlr->ichannels),
240 (ctlr->caps & AHCI_CAP_NPMASK) + 1);
241 if (ctlr->quirks & AHCI_Q_NOPMP)
242 ctlr->caps &= ~AHCI_CAP_SPM;
243 if (ctlr->quirks & AHCI_Q_NONCQ)
244 ctlr->caps &= ~AHCI_CAP_SNCQ;
245 if ((ctlr->caps & AHCI_CAP_CCCS) == 0)
246 ctlr->ccc = 0;
247 ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC);
248
249 /* Create controller-wide DMA tag. */
250 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
251 (ctlr->caps & AHCI_CAP_64BIT) ? BUS_SPACE_MAXADDR :
252 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
253 BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE,
254 ctlr->dma_coherent ? BUS_DMA_COHERENT : 0, NULL, NULL,
255 &ctlr->dma_tag)) {
256 ahci_free_mem(dev);
257 rman_fini(&ctlr->sc_iomem);
258 return (ENXIO);
259 }
260
261 ahci_ctlr_setup(dev);
262
263 /* Setup interrupts. */
264 if ((error = ahci_setup_interrupt(dev)) != 0) {
265 bus_dma_tag_destroy(ctlr->dma_tag);
266 ahci_free_mem(dev);
267 rman_fini(&ctlr->sc_iomem);
268 return (error);
269 }
270
271 i = 0;
272 for (u = ctlr->ichannels; u != 0; u >>= 1)
273 i += (u & 1);
274 ctlr->direct = (ctlr->msi && (ctlr->numirqs > 1 || i <= 3));
275 resource_int_value(device_get_name(dev), device_get_unit(dev),
276 "direct", &ctlr->direct);
277 /* Announce HW capabilities. */
278 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT;
279 device_printf(dev,
280 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n",
281 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f),
282 ((version >> 4) & 0xf0) + (version & 0x0f),
283 (ctlr->caps & AHCI_CAP_NPMASK) + 1,
284 ((speed == 1) ? "1.5":((speed == 2) ? "3":
285 ((speed == 3) ? "6":"?"))),
286 (ctlr->caps & AHCI_CAP_SPM) ?
287 "supported" : "not supported",
288 (ctlr->caps & AHCI_CAP_FBSS) ?
289 " with FBS" : "");
290 if (ctlr->quirks != 0) {
291 device_printf(dev, "quirks=0x%b\n", ctlr->quirks,
292 AHCI_Q_BIT_STRING);
293 }
294 if (bootverbose) {
295 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps",
296 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"",
297 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"",
298 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"",
299 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"",
300 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"",
301 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"",
302 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"",
303 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"",
304 ((speed == 1) ? "1.5":((speed == 2) ? "3":
305 ((speed == 3) ? "6":"?"))));
306 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n",
307 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"",
308 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"",
309 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"",
310 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"",
311 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"",
312 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"",
313 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1,
314 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"",
315 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"",
316 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"",
317 (ctlr->caps & AHCI_CAP_NPMASK) + 1);
318 }
319 if (bootverbose && version >= 0x00010200) {
320 device_printf(dev, "Caps2:%s%s%s%s%s%s\n",
321 (ctlr->caps2 & AHCI_CAP2_DESO) ? " DESO":"",
322 (ctlr->caps2 & AHCI_CAP2_SADM) ? " SADM":"",
323 (ctlr->caps2 & AHCI_CAP2_SDS) ? " SDS":"",
324 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"",
325 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"",
326 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":"");
327 }
328 /* Attach all channels on this controller */
329 for (unit = 0; unit < ctlr->channels; unit++) {
330 child = device_add_child(dev, "ahcich", -1);
331 if (child == NULL) {
332 device_printf(dev, "failed to add channel device\n");
333 continue;
334 }
335 device_set_ivars(child, (void *)(intptr_t)unit);
336 if ((ctlr->ichannels & (1 << unit)) == 0)
337 device_disable(child);
338 }
339 if (ctlr->caps & AHCI_CAP_EMS) {
340 child = device_add_child(dev, "ahciem", -1);
341 if (child == NULL)
342 device_printf(dev, "failed to add enclosure device\n");
343 else
344 device_set_ivars(child, (void *)(intptr_t)-1);
345 }
346 bus_generic_attach(dev);
347 return (0);
348 }
349
350 int
351 ahci_detach(device_t dev)
352 {
353 struct ahci_controller *ctlr = device_get_softc(dev);
354 int i;
355
356 /* Detach & delete all children */
357 device_delete_children(dev);
358
359 /* Free interrupts. */
360 for (i = 0; i < ctlr->numirqs; i++) {
361 if (ctlr->irqs[i].r_irq) {
362 bus_teardown_intr(dev, ctlr->irqs[i].r_irq,
363 ctlr->irqs[i].handle);
364 bus_release_resource(dev, SYS_RES_IRQ,
365 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq);
366 }
367 }
368 bus_dma_tag_destroy(ctlr->dma_tag);
369 /* Free memory. */
370 rman_fini(&ctlr->sc_iomem);
371 ahci_free_mem(dev);
372 return (0);
373 }
374
375 void
376 ahci_free_mem(device_t dev)
377 {
378 struct ahci_controller *ctlr = device_get_softc(dev);
379
380 /* Release memory resources */
381 if (ctlr->r_mem)
382 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
383 if (ctlr->r_msix_table)
384 bus_release_resource(dev, SYS_RES_MEMORY,
385 ctlr->r_msix_tab_rid, ctlr->r_msix_table);
386 if (ctlr->r_msix_pba)
387 bus_release_resource(dev, SYS_RES_MEMORY,
388 ctlr->r_msix_pba_rid, ctlr->r_msix_pba);
389
390 ctlr->r_msix_pba = ctlr->r_mem = ctlr->r_msix_table = NULL;
391 }
392
393 int
394 ahci_setup_interrupt(device_t dev)
395 {
396 struct ahci_controller *ctlr = device_get_softc(dev);
397 int i;
398
399 /* Check for single MSI vector fallback. */
400 if (ctlr->numirqs > 1 &&
401 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) {
402 device_printf(dev, "Falling back to one MSI\n");
403 ctlr->numirqs = 1;
404 }
405
406 /* Ensure we don't overrun irqs. */
407 if (ctlr->numirqs > AHCI_MAX_IRQS) {
408 device_printf(dev, "Too many irqs %d > %d (clamping)\n",
409 ctlr->numirqs, AHCI_MAX_IRQS);
410 ctlr->numirqs = AHCI_MAX_IRQS;
411 }
412
413 /* Allocate all IRQs. */
414 for (i = 0; i < ctlr->numirqs; i++) {
415 ctlr->irqs[i].ctlr = ctlr;
416 ctlr->irqs[i].r_irq_rid = i + (ctlr->msi ? 1 : 0);
417 if (ctlr->channels == 1 && !ctlr->ccc && ctlr->msi)
418 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE;
419 else if (ctlr->numirqs == 1 || i >= ctlr->channels ||
420 (ctlr->ccc && i == ctlr->cccv))
421 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL;
422 else if (ctlr->channels > ctlr->numirqs &&
423 i == ctlr->numirqs - 1)
424 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER;
425 else
426 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE;
427 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
428 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) {
429 device_printf(dev, "unable to map interrupt\n");
430 return (ENXIO);
431 }
432 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL,
433 (ctlr->irqs[i].mode != AHCI_IRQ_MODE_ONE) ? ahci_intr :
434 ((ctlr->quirks & AHCI_Q_EDGEIS) ? ahci_intr_one_edge :
435 ahci_intr_one),
436 &ctlr->irqs[i], &ctlr->irqs[i].handle))) {
437 /* SOS XXX release r_irq */
438 device_printf(dev, "unable to setup interrupt\n");
439 return (ENXIO);
440 }
441 if (ctlr->numirqs > 1) {
442 bus_describe_intr(dev, ctlr->irqs[i].r_irq,
443 ctlr->irqs[i].handle,
444 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ?
445 "ch%d" : "%d", i);
446 }
447 }
448 return (0);
449 }
450
451 /*
452 * Common case interrupt handler.
453 */
454 static void
455 ahci_intr(void *data)
456 {
457 struct ahci_controller_irq *irq = data;
458 struct ahci_controller *ctlr = irq->ctlr;
459 u_int32_t is, ise = 0;
460 void *arg;
461 int unit;
462
463 if (irq->mode == AHCI_IRQ_MODE_ALL) {
464 unit = 0;
465 if (ctlr->ccc)
466 is = ctlr->ichannels;
467 else
468 is = ATA_INL(ctlr->r_mem, AHCI_IS);
469 } else { /* AHCI_IRQ_MODE_AFTER */
470 unit = irq->r_irq_rid - 1;
471 is = ATA_INL(ctlr->r_mem, AHCI_IS);
472 is &= (0xffffffff << unit);
473 }
474 /* CCC interrupt is edge triggered. */
475 if (ctlr->ccc)
476 ise = 1 << ctlr->cccv;
477 /* Some controllers have edge triggered IS. */
478 if (ctlr->quirks & AHCI_Q_EDGEIS)
479 ise |= is;
480 if (ise != 0)
481 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise);
482 for (; unit < ctlr->channels; unit++) {
483 if ((is & (1 << unit)) != 0 &&
484 (arg = ctlr->interrupt[unit].argument)) {
485 ctlr->interrupt[unit].function(arg);
486 }
487 }
488 /* AHCI declares level triggered IS. */
489 if (!(ctlr->quirks & AHCI_Q_EDGEIS))
490 ATA_OUTL(ctlr->r_mem, AHCI_IS, is);
491 ATA_RBL(ctlr->r_mem, AHCI_IS);
492 }
493
494 /*
495 * Simplified interrupt handler for multivector MSI mode.
496 */
497 static void
498 ahci_intr_one(void *data)
499 {
500 struct ahci_controller_irq *irq = data;
501 struct ahci_controller *ctlr = irq->ctlr;
502 void *arg;
503 int unit;
504
505 unit = irq->r_irq_rid - 1;
506 if ((arg = ctlr->interrupt[unit].argument))
507 ctlr->interrupt[unit].function(arg);
508 /* AHCI declares level triggered IS. */
509 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
510 ATA_RBL(ctlr->r_mem, AHCI_IS);
511 }
512
513 static void
514 ahci_intr_one_edge(void *data)
515 {
516 struct ahci_controller_irq *irq = data;
517 struct ahci_controller *ctlr = irq->ctlr;
518 void *arg;
519 int unit;
520
521 unit = irq->r_irq_rid - 1;
522 /* Some controllers have edge triggered IS. */
523 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
524 if ((arg = ctlr->interrupt[unit].argument))
525 ctlr->interrupt[unit].function(arg);
526 ATA_RBL(ctlr->r_mem, AHCI_IS);
527 }
528
529 struct resource *
530 ahci_alloc_resource(device_t dev, device_t child, int type, int *rid,
531 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
532 {
533 struct ahci_controller *ctlr = device_get_softc(dev);
534 struct resource *res;
535 rman_res_t st;
536 int offset, size, unit;
537
538 unit = (intptr_t)device_get_ivars(child);
539 res = NULL;
540 switch (type) {
541 case SYS_RES_MEMORY:
542 if (unit >= 0) {
543 offset = AHCI_OFFSET + (unit << 7);
544 size = 128;
545 } else if (*rid == 0) {
546 offset = AHCI_EM_CTL;
547 size = 4;
548 } else {
549 offset = (ctlr->emloc & 0xffff0000) >> 14;
550 size = (ctlr->emloc & 0x0000ffff) << 2;
551 if (*rid != 1) {
552 if (*rid == 2 && (ctlr->capsem &
553 (AHCI_EM_XMT | AHCI_EM_SMB)) == 0)
554 offset += size;
555 else
556 break;
557 }
558 }
559 st = rman_get_start(ctlr->r_mem);
560 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset,
561 st + offset + size - 1, size, RF_ACTIVE, child);
562 if (res) {
563 bus_space_handle_t bsh;
564 bus_space_tag_t bst;
565 bsh = rman_get_bushandle(ctlr->r_mem);
566 bst = rman_get_bustag(ctlr->r_mem);
567 bus_space_subregion(bst, bsh, offset, 128, &bsh);
568 rman_set_bushandle(res, bsh);
569 rman_set_bustag(res, bst);
570 }
571 break;
572 case SYS_RES_IRQ:
573 if (*rid == ATA_IRQ_RID)
574 res = ctlr->irqs[0].r_irq;
575 break;
576 }
577 return (res);
578 }
579
580 int
581 ahci_release_resource(device_t dev, device_t child, int type, int rid,
582 struct resource *r)
583 {
584
585 switch (type) {
586 case SYS_RES_MEMORY:
587 rman_release_resource(r);
588 return (0);
589 case SYS_RES_IRQ:
590 if (rid != ATA_IRQ_RID)
591 return (ENOENT);
592 return (0);
593 }
594 return (EINVAL);
595 }
596
597 int
598 ahci_setup_intr(device_t dev, device_t child, struct resource *irq,
599 int flags, driver_filter_t *filter, driver_intr_t *function,
600 void *argument, void **cookiep)
601 {
602 struct ahci_controller *ctlr = device_get_softc(dev);
603 int unit = (intptr_t)device_get_ivars(child);
604
605 if (filter != NULL) {
606 printf("ahci.c: we cannot use a filter here\n");
607 return (EINVAL);
608 }
609 ctlr->interrupt[unit].function = function;
610 ctlr->interrupt[unit].argument = argument;
611 return (0);
612 }
613
614 int
615 ahci_teardown_intr(device_t dev, device_t child, struct resource *irq,
616 void *cookie)
617 {
618 struct ahci_controller *ctlr = device_get_softc(dev);
619 int unit = (intptr_t)device_get_ivars(child);
620
621 ctlr->interrupt[unit].function = NULL;
622 ctlr->interrupt[unit].argument = NULL;
623 return (0);
624 }
625
626 int
627 ahci_print_child(device_t dev, device_t child)
628 {
629 int retval, channel;
630
631 retval = bus_print_child_header(dev, child);
632 channel = (int)(intptr_t)device_get_ivars(child);
633 if (channel >= 0)
634 retval += printf(" at channel %d", channel);
635 retval += bus_print_child_footer(dev, child);
636 return (retval);
637 }
638
639 int
640 ahci_child_location_str(device_t dev, device_t child, char *buf,
641 size_t buflen)
642 {
643 int channel;
644
645 channel = (int)(intptr_t)device_get_ivars(child);
646 if (channel >= 0)
647 snprintf(buf, buflen, "channel=%d", channel);
648 return (0);
649 }
650
651 bus_dma_tag_t
652 ahci_get_dma_tag(device_t dev, device_t child)
653 {
654 struct ahci_controller *ctlr = device_get_softc(dev);
655
656 return (ctlr->dma_tag);
657 }
658
659 static int
660 ahci_ch_probe(device_t dev)
661 {
662
663 device_set_desc_copy(dev, "AHCI channel");
664 return (BUS_PROBE_DEFAULT);
665 }
666
667 static int
668 ahci_ch_attach(device_t dev)
669 {
670 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev));
671 struct ahci_channel *ch = device_get_softc(dev);
672 struct cam_devq *devq;
673 int rid, error, i, sata_rev = 0;
674 u_int32_t version;
675
676 ch->dev = dev;
677 ch->unit = (intptr_t)device_get_ivars(dev);
678 ch->caps = ctlr->caps;
679 ch->caps2 = ctlr->caps2;
680 ch->start = ctlr->ch_start;
681 ch->quirks = ctlr->quirks;
682 ch->vendorid = ctlr->vendorid;
683 ch->deviceid = ctlr->deviceid;
684 ch->subvendorid = ctlr->subvendorid;
685 ch->subdeviceid = ctlr->subdeviceid;
686 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1;
687 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF);
688 ch->pm_level = 0;
689 resource_int_value(device_get_name(dev),
690 device_get_unit(dev), "pm_level", &ch->pm_level);
691 STAILQ_INIT(&ch->doneq);
692 if (ch->pm_level > 3)
693 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0);
694 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0);
695 /* JMicron external ports (0) sometimes limited */
696 if ((ctlr->quirks & AHCI_Q_SATA1_UNIT0) && ch->unit == 0)
697 sata_rev = 1;
698 if (ch->quirks & AHCI_Q_SATA2)
699 sata_rev = 2;
700 resource_int_value(device_get_name(dev),
701 device_get_unit(dev), "sata_rev", &sata_rev);
702 for (i = 0; i < 16; i++) {
703 ch->user[i].revision = sata_rev;
704 ch->user[i].mode = 0;
705 ch->user[i].bytecount = 8192;
706 ch->user[i].tags = ch->numslots;
707 ch->user[i].caps = 0;
708 ch->curr[i] = ch->user[i];
709 if (ch->pm_level) {
710 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ |
711 CTS_SATA_CAPS_H_APST |
712 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST;
713 }
714 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA |
715 CTS_SATA_CAPS_H_AN;
716 }
717 rid = 0;
718 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
719 &rid, RF_ACTIVE)))
720 return (ENXIO);
721 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD);
722 version = ATA_INL(ctlr->r_mem, AHCI_VS);
723 if (version < 0x00010200 && (ctlr->caps & AHCI_CAP_FBSS))
724 ch->chcaps |= AHCI_P_CMD_FBSCP;
725 if (ch->caps2 & AHCI_CAP2_SDS)
726 ch->chscaps = ATA_INL(ch->r_mem, AHCI_P_DEVSLP);
727 if (bootverbose) {
728 device_printf(dev, "Caps:%s%s%s%s%s%s\n",
729 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"",
730 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"",
731 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"",
732 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"",
733 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":"",
734 (ch->chscaps & AHCI_P_DEVSLP_DSP) ? " DSP":"");
735 }
736 ahci_dmainit(dev);
737 ahci_slotsalloc(dev);
738 mtx_lock(&ch->mtx);
739 ahci_ch_init(dev);
740 rid = ATA_IRQ_RID;
741 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
742 &rid, RF_SHAREABLE | RF_ACTIVE))) {
743 device_printf(dev, "Unable to map interrupt\n");
744 error = ENXIO;
745 goto err0;
746 }
747 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL,
748 ctlr->direct ? ahci_ch_intr_direct : ahci_ch_intr,
749 ch, &ch->ih))) {
750 device_printf(dev, "Unable to setup interrupt\n");
751 error = ENXIO;
752 goto err1;
753 }
754 /* Create the device queue for our SIM. */
755 devq = cam_simq_alloc(ch->numslots);
756 if (devq == NULL) {
757 device_printf(dev, "Unable to allocate simq\n");
758 error = ENOMEM;
759 goto err1;
760 }
761 /* Construct SIM entry */
762 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch,
763 device_get_unit(dev), (struct mtx *)&ch->mtx,
764 (ch->quirks & AHCI_Q_NOCCS) ? 1 : min(2, ch->numslots),
765 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0,
766 devq);
767 if (ch->sim == NULL) {
768 cam_simq_free(devq);
769 device_printf(dev, "unable to allocate sim\n");
770 error = ENOMEM;
771 goto err1;
772 }
773 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) {
774 device_printf(dev, "unable to register xpt bus\n");
775 error = ENXIO;
776 goto err2;
777 }
778 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim),
779 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
780 device_printf(dev, "unable to create path\n");
781 error = ENXIO;
782 goto err3;
783 }
784 if (ch->pm_level > 3) {
785 callout_reset(&ch->pm_timer,
786 (ch->pm_level == 4) ? hz / 1000 : hz / 8,
787 ahci_ch_pm, ch);
788 }
789 mtx_unlock(&ch->mtx);
790 return (0);
791
792 err3:
793 xpt_bus_deregister(cam_sim_path(ch->sim));
794 err2:
795 cam_sim_free(ch->sim, /*free_devq*/TRUE);
796 err1:
797 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
798 err0:
799 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
800 mtx_unlock(&ch->mtx);
801 mtx_destroy(&ch->mtx);
802 return (error);
803 }
804
805 static int
806 ahci_ch_detach(device_t dev)
807 {
808 struct ahci_channel *ch = device_get_softc(dev);
809
810 mtx_lock(&ch->mtx);
811 xpt_async(AC_LOST_DEVICE, ch->path, NULL);
812 /* Forget about reset. */
813 if (ch->resetting) {
814 ch->resetting = 0;
815 xpt_release_simq(ch->sim, TRUE);
816 }
817 xpt_free_path(ch->path);
818 xpt_bus_deregister(cam_sim_path(ch->sim));
819 cam_sim_free(ch->sim, /*free_devq*/TRUE);
820 mtx_unlock(&ch->mtx);
821
822 if (ch->pm_level > 3)
823 callout_drain(&ch->pm_timer);
824 callout_drain(&ch->reset_timer);
825 bus_teardown_intr(dev, ch->r_irq, ch->ih);
826 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
827
828 ahci_ch_deinit(dev);
829 ahci_slotsfree(dev);
830 ahci_dmafini(dev);
831
832 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
833 mtx_destroy(&ch->mtx);
834 return (0);
835 }
836
837 static int
838 ahci_ch_init(device_t dev)
839 {
840 struct ahci_channel *ch = device_get_softc(dev);
841 uint64_t work;
842
843 /* Disable port interrupts */
844 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
845 /* Setup work areas */
846 work = ch->dma.work_bus + AHCI_CL_OFFSET;
847 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff);
848 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32);
849 work = ch->dma.rfis_bus;
850 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff);
851 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32);
852 /* Activate the channel and power/spin up device */
853 ATA_OUTL(ch->r_mem, AHCI_P_CMD,
854 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD |
855 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) |
856 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 )));
857 ahci_start_fr(ch);
858 ahci_start(ch, 1);
859 return (0);
860 }
861
862 static int
863 ahci_ch_deinit(device_t dev)
864 {
865 struct ahci_channel *ch = device_get_softc(dev);
866
867 /* Disable port interrupts. */
868 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
869 /* Reset command register. */
870 ahci_stop(ch);
871 ahci_stop_fr(ch);
872 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0);
873 /* Allow everything, including partial and slumber modes. */
874 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0);
875 /* Request slumber mode transition and give some time to get there. */
876 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER);
877 DELAY(100);
878 /* Disable PHY. */
879 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
880 return (0);
881 }
882
883 static int
884 ahci_ch_suspend(device_t dev)
885 {
886 struct ahci_channel *ch = device_get_softc(dev);
887
888 mtx_lock(&ch->mtx);
889 xpt_freeze_simq(ch->sim, 1);
890 /* Forget about reset. */
891 if (ch->resetting) {
892 ch->resetting = 0;
893 callout_stop(&ch->reset_timer);
894 xpt_release_simq(ch->sim, TRUE);
895 }
896 while (ch->oslots)
897 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100);
898 ahci_ch_deinit(dev);
899 mtx_unlock(&ch->mtx);
900 return (0);
901 }
902
903 static int
904 ahci_ch_resume(device_t dev)
905 {
906 struct ahci_channel *ch = device_get_softc(dev);
907
908 mtx_lock(&ch->mtx);
909 ahci_ch_init(dev);
910 ahci_reset(ch);
911 xpt_release_simq(ch->sim, TRUE);
912 mtx_unlock(&ch->mtx);
913 return (0);
914 }
915
916 devclass_t ahcich_devclass;
917 static device_method_t ahcich_methods[] = {
918 DEVMETHOD(device_probe, ahci_ch_probe),
919 DEVMETHOD(device_attach, ahci_ch_attach),
920 DEVMETHOD(device_detach, ahci_ch_detach),
921 DEVMETHOD(device_suspend, ahci_ch_suspend),
922 DEVMETHOD(device_resume, ahci_ch_resume),
923 DEVMETHOD_END
924 };
925 static driver_t ahcich_driver = {
926 "ahcich",
927 ahcich_methods,
928 sizeof(struct ahci_channel)
929 };
930 DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, NULL, NULL);
931
932 struct ahci_dc_cb_args {
933 bus_addr_t maddr;
934 int error;
935 };
936
937 static void
938 ahci_dmainit(device_t dev)
939 {
940 struct ahci_channel *ch = device_get_softc(dev);
941 struct ahci_dc_cb_args dcba;
942 size_t rfsize;
943
944 /* Command area. */
945 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0,
946 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
947 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE,
948 0, NULL, NULL, &ch->dma.work_tag))
949 goto error;
950 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work,
951 BUS_DMA_ZERO, &ch->dma.work_map))
952 goto error;
953 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work,
954 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) {
955 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
956 goto error;
957 }
958 ch->dma.work_bus = dcba.maddr;
959 /* FIS receive area. */
960 if (ch->chcaps & AHCI_P_CMD_FBSCP)
961 rfsize = 4096;
962 else
963 rfsize = 256;
964 if (bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0,
965 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
966 NULL, NULL, rfsize, 1, rfsize,
967 0, NULL, NULL, &ch->dma.rfis_tag))
968 goto error;
969 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0,
970 &ch->dma.rfis_map))
971 goto error;
972 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis,
973 rfsize, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) {
974 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
975 goto error;
976 }
977 ch->dma.rfis_bus = dcba.maddr;
978 /* Data area. */
979 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
980 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
981 NULL, NULL,
982 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots,
983 AHCI_SG_ENTRIES, AHCI_PRD_MAX,
984 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) {
985 goto error;
986 }
987 return;
988
989 error:
990 device_printf(dev, "WARNING - DMA initialization failed\n");
991 ahci_dmafini(dev);
992 }
993
994 static void
995 ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
996 {
997 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc;
998
999 if (!(dcba->error = error))
1000 dcba->maddr = segs[0].ds_addr;
1001 }
1002
1003 static void
1004 ahci_dmafini(device_t dev)
1005 {
1006 struct ahci_channel *ch = device_get_softc(dev);
1007
1008 if (ch->dma.data_tag) {
1009 bus_dma_tag_destroy(ch->dma.data_tag);
1010 ch->dma.data_tag = NULL;
1011 }
1012 if (ch->dma.rfis_bus) {
1013 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map);
1014 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
1015 ch->dma.rfis_bus = 0;
1016 ch->dma.rfis = NULL;
1017 }
1018 if (ch->dma.work_bus) {
1019 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map);
1020 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
1021 ch->dma.work_bus = 0;
1022 ch->dma.work = NULL;
1023 }
1024 if (ch->dma.work_tag) {
1025 bus_dma_tag_destroy(ch->dma.work_tag);
1026 ch->dma.work_tag = NULL;
1027 }
1028 }
1029
1030 static void
1031 ahci_slotsalloc(device_t dev)
1032 {
1033 struct ahci_channel *ch = device_get_softc(dev);
1034 int i;
1035
1036 /* Alloc and setup command/dma slots */
1037 bzero(ch->slot, sizeof(ch->slot));
1038 for (i = 0; i < ch->numslots; i++) {
1039 struct ahci_slot *slot = &ch->slot[i];
1040
1041 slot->ch = ch;
1042 slot->slot = i;
1043 slot->state = AHCI_SLOT_EMPTY;
1044 slot->ccb = NULL;
1045 callout_init_mtx(&slot->timeout, &ch->mtx, 0);
1046
1047 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map))
1048 device_printf(ch->dev, "FAILURE - create data_map\n");
1049 }
1050 }
1051
1052 static void
1053 ahci_slotsfree(device_t dev)
1054 {
1055 struct ahci_channel *ch = device_get_softc(dev);
1056 int i;
1057
1058 /* Free all dma slots */
1059 for (i = 0; i < ch->numslots; i++) {
1060 struct ahci_slot *slot = &ch->slot[i];
1061
1062 callout_drain(&slot->timeout);
1063 if (slot->dma.data_map) {
1064 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map);
1065 slot->dma.data_map = NULL;
1066 }
1067 }
1068 }
1069
1070 static int
1071 ahci_phy_check_events(struct ahci_channel *ch, u_int32_t serr)
1072 {
1073
1074 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) ||
1075 ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) {
1076 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
1077 union ccb *ccb;
1078
1079 if (bootverbose) {
1080 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE)
1081 device_printf(ch->dev, "CONNECT requested\n");
1082 else
1083 device_printf(ch->dev, "DISCONNECT requested\n");
1084 }
1085 ahci_reset(ch);
1086 if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
1087 return (0);
1088 if (xpt_create_path(&ccb->ccb_h.path, NULL,
1089 cam_sim_path(ch->sim),
1090 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
1091 xpt_free_ccb(ccb);
1092 return (0);
1093 }
1094 xpt_rescan(ccb);
1095 return (1);
1096 }
1097 return (0);
1098 }
1099
1100 static void
1101 ahci_cpd_check_events(struct ahci_channel *ch)
1102 {
1103 u_int32_t status;
1104 union ccb *ccb;
1105 device_t dev;
1106
1107 if (ch->pm_level == 0)
1108 return;
1109
1110 status = ATA_INL(ch->r_mem, AHCI_P_CMD);
1111 if ((status & AHCI_P_CMD_CPD) == 0)
1112 return;
1113
1114 if (bootverbose) {
1115 dev = ch->dev;
1116 if (status & AHCI_P_CMD_CPS) {
1117 device_printf(dev, "COLD CONNECT requested\n");
1118 } else
1119 device_printf(dev, "COLD DISCONNECT requested\n");
1120 }
1121 ahci_reset(ch);
1122 if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
1123 return;
1124 if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim),
1125 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
1126 xpt_free_ccb(ccb);
1127 return;
1128 }
1129 xpt_rescan(ccb);
1130 }
1131
1132 static void
1133 ahci_notify_events(struct ahci_channel *ch, u_int32_t status)
1134 {
1135 struct cam_path *dpath;
1136 int i;
1137
1138 if (ch->caps & AHCI_CAP_SSNTF)
1139 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status);
1140 if (bootverbose)
1141 device_printf(ch->dev, "SNTF 0x%04x\n", status);
1142 for (i = 0; i < 16; i++) {
1143 if ((status & (1 << i)) == 0)
1144 continue;
1145 if (xpt_create_path(&dpath, NULL,
1146 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) {
1147 xpt_async(AC_SCSI_AEN, dpath, NULL);
1148 xpt_free_path(dpath);
1149 }
1150 }
1151 }
1152
1153 static void
1154 ahci_done(struct ahci_channel *ch, union ccb *ccb)
1155 {
1156
1157 mtx_assert(&ch->mtx, MA_OWNED);
1158 if ((ccb->ccb_h.func_code & XPT_FC_QUEUED) == 0 ||
1159 ch->batch == 0) {
1160 xpt_done(ccb);
1161 return;
1162 }
1163
1164 STAILQ_INSERT_TAIL(&ch->doneq, &ccb->ccb_h, sim_links.stqe);
1165 }
1166
1167 static void
1168 ahci_ch_intr(void *arg)
1169 {
1170 struct ahci_channel *ch = (struct ahci_channel *)arg;
1171 uint32_t istatus;
1172
1173 /* Read interrupt statuses. */
1174 istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
1175
1176 mtx_lock(&ch->mtx);
1177 ahci_ch_intr_main(ch, istatus);
1178 mtx_unlock(&ch->mtx);
1179 }
1180
1181 static void
1182 ahci_ch_intr_direct(void *arg)
1183 {
1184 struct ahci_channel *ch = (struct ahci_channel *)arg;
1185 struct ccb_hdr *ccb_h;
1186 uint32_t istatus;
1187 STAILQ_HEAD(, ccb_hdr) tmp_doneq = STAILQ_HEAD_INITIALIZER(tmp_doneq);
1188
1189 /* Read interrupt statuses. */
1190 istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
1191
1192 mtx_lock(&ch->mtx);
1193 ch->batch = 1;
1194 ahci_ch_intr_main(ch, istatus);
1195 ch->batch = 0;
1196 /*
1197 * Prevent the possibility of issues caused by processing the queue
1198 * while unlocked below by moving the contents to a local queue.
1199 */
1200 STAILQ_CONCAT(&tmp_doneq, &ch->doneq);
1201 mtx_unlock(&ch->mtx);
1202 while ((ccb_h = STAILQ_FIRST(&tmp_doneq)) != NULL) {
1203 STAILQ_REMOVE_HEAD(&tmp_doneq, sim_links.stqe);
1204 xpt_done_direct((union ccb *)ccb_h);
1205 }
1206 }
1207
1208 static void
1209 ahci_ch_pm(void *arg)
1210 {
1211 struct ahci_channel *ch = (struct ahci_channel *)arg;
1212 uint32_t work;
1213
1214 if (ch->numrslots != 0)
1215 return;
1216 work = ATA_INL(ch->r_mem, AHCI_P_CMD);
1217 if (ch->pm_level == 4)
1218 work |= AHCI_P_CMD_PARTIAL;
1219 else
1220 work |= AHCI_P_CMD_SLUMBER;
1221 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work);
1222 }
1223
1224 static void
1225 ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus)
1226 {
1227 uint32_t cstatus, serr = 0, sntf = 0, ok, err;
1228 enum ahci_err_type et;
1229 int i, ccs, port, reset = 0;
1230
1231 /* Clear interrupt statuses. */
1232 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus);
1233 /* Read command statuses. */
1234 if (ch->numtslots != 0)
1235 cstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
1236 else
1237 cstatus = 0;
1238 if (ch->numrslots != ch->numtslots)
1239 cstatus |= ATA_INL(ch->r_mem, AHCI_P_CI);
1240 /* Read SNTF in one of possible ways. */
1241 if ((istatus & AHCI_P_IX_SDB) &&
1242 (ch->pm_present || ch->curr[0].atapi != 0)) {
1243 if (ch->caps & AHCI_CAP_SSNTF)
1244 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF);
1245 else if (ch->fbs_enabled) {
1246 u_int8_t *fis = ch->dma.rfis + 0x58;
1247
1248 for (i = 0; i < 16; i++) {
1249 if (fis[1] & 0x80) {
1250 fis[1] &= 0x7f;
1251 sntf |= 1 << i;
1252 }
1253 fis += 256;
1254 }
1255 } else {
1256 u_int8_t *fis = ch->dma.rfis + 0x58;
1257
1258 if (fis[1] & 0x80)
1259 sntf = (1 << (fis[1] & 0x0f));
1260 }
1261 }
1262 /* Process PHY events */
1263 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF |
1264 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) {
1265 serr = ATA_INL(ch->r_mem, AHCI_P_SERR);
1266 if (serr) {
1267 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr);
1268 reset = ahci_phy_check_events(ch, serr);
1269 }
1270 }
1271 /* Process cold presence detection events */
1272 if ((istatus & AHCI_P_IX_CPD) && !reset)
1273 ahci_cpd_check_events(ch);
1274 /* Process command errors */
1275 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF |
1276 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) {
1277 if (ch->quirks & AHCI_Q_NOCCS) {
1278 /*
1279 * ASMedia chips sometimes report failed commands as
1280 * completed. Count all running commands as failed.
1281 */
1282 cstatus |= ch->rslots;
1283
1284 /* They also report wrong CCS, so try to guess one. */
1285 ccs = powerof2(cstatus) ? ffs(cstatus) - 1 : -1;
1286 } else {
1287 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) &
1288 AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT;
1289 }
1290 //device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n",
1291 // __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD),
1292 // serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs);
1293 port = -1;
1294 if (ch->fbs_enabled) {
1295 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS);
1296 if (fbs & AHCI_P_FBS_SDE) {
1297 port = (fbs & AHCI_P_FBS_DWE)
1298 >> AHCI_P_FBS_DWE_SHIFT;
1299 } else {
1300 for (i = 0; i < 16; i++) {
1301 if (ch->numrslotspd[i] == 0)
1302 continue;
1303 if (port == -1)
1304 port = i;
1305 else if (port != i) {
1306 port = -2;
1307 break;
1308 }
1309 }
1310 }
1311 }
1312 err = ch->rslots & cstatus;
1313 } else {
1314 ccs = 0;
1315 err = 0;
1316 port = -1;
1317 }
1318 /* Complete all successful commands. */
1319 ok = ch->rslots & ~cstatus;
1320 for (i = 0; i < ch->numslots; i++) {
1321 if ((ok >> i) & 1)
1322 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE);
1323 }
1324 /* On error, complete the rest of commands with error statuses. */
1325 if (err) {
1326 if (ch->frozen) {
1327 union ccb *fccb = ch->frozen;
1328 ch->frozen = NULL;
1329 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1330 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1331 xpt_freeze_devq(fccb->ccb_h.path, 1);
1332 fccb->ccb_h.status |= CAM_DEV_QFRZN;
1333 }
1334 ahci_done(ch, fccb);
1335 }
1336 for (i = 0; i < ch->numslots; i++) {
1337 /* XXX: reqests in loading state. */
1338 if (((err >> i) & 1) == 0)
1339 continue;
1340 if (port >= 0 &&
1341 ch->slot[i].ccb->ccb_h.target_id != port)
1342 continue;
1343 if (istatus & AHCI_P_IX_TFE) {
1344 if (port != -2) {
1345 /* Task File Error */
1346 if (ch->numtslotspd[
1347 ch->slot[i].ccb->ccb_h.target_id] == 0) {
1348 /* Untagged operation. */
1349 if (i == ccs)
1350 et = AHCI_ERR_TFE;
1351 else
1352 et = AHCI_ERR_INNOCENT;
1353 } else {
1354 /* Tagged operation. */
1355 et = AHCI_ERR_NCQ;
1356 }
1357 } else {
1358 et = AHCI_ERR_TFE;
1359 ch->fatalerr = 1;
1360 }
1361 } else if (istatus & AHCI_P_IX_IF) {
1362 if (ch->numtslots == 0 && i != ccs && port != -2)
1363 et = AHCI_ERR_INNOCENT;
1364 else
1365 et = AHCI_ERR_SATA;
1366 } else
1367 et = AHCI_ERR_INVALID;
1368 ahci_end_transaction(&ch->slot[i], et);
1369 }
1370 /*
1371 * We can't reinit port if there are some other
1372 * commands active, use resume to complete them.
1373 */
1374 if (ch->rslots != 0 && !ch->recoverycmd)
1375 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC);
1376 }
1377 /* Process NOTIFY events */
1378 if (sntf)
1379 ahci_notify_events(ch, sntf);
1380 }
1381
1382 /* Must be called with channel locked. */
1383 static int
1384 ahci_check_collision(struct ahci_channel *ch, union ccb *ccb)
1385 {
1386 int t = ccb->ccb_h.target_id;
1387
1388 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1389 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1390 /* Tagged command while we have no supported tag free. */
1391 if (((~ch->oslots) & (0xffffffff >> (32 -
1392 ch->curr[t].tags))) == 0)
1393 return (1);
1394 /* If we have FBS */
1395 if (ch->fbs_enabled) {
1396 /* Tagged command while untagged are active. */
1397 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0)
1398 return (1);
1399 } else {
1400 /* Tagged command while untagged are active. */
1401 if (ch->numrslots != 0 && ch->numtslots == 0)
1402 return (1);
1403 /* Tagged command while tagged to other target is active. */
1404 if (ch->numtslots != 0 &&
1405 ch->taggedtarget != ccb->ccb_h.target_id)
1406 return (1);
1407 }
1408 } else {
1409 /* If we have FBS */
1410 if (ch->fbs_enabled) {
1411 /* Untagged command while tagged are active. */
1412 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0)
1413 return (1);
1414 } else {
1415 /* Untagged command while tagged are active. */
1416 if (ch->numrslots != 0 && ch->numtslots != 0)
1417 return (1);
1418 }
1419 }
1420 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1421 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) {
1422 /* Atomic command while anything active. */
1423 if (ch->numrslots != 0)
1424 return (1);
1425 }
1426 /* We have some atomic command running. */
1427 if (ch->aslots != 0)
1428 return (1);
1429 return (0);
1430 }
1431
1432 /* Must be called with channel locked. */
1433 static void
1434 ahci_begin_transaction(struct ahci_channel *ch, union ccb *ccb)
1435 {
1436 struct ahci_slot *slot;
1437 int tag, tags;
1438
1439 /* Choose empty slot. */
1440 tags = ch->numslots;
1441 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1442 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA))
1443 tags = ch->curr[ccb->ccb_h.target_id].tags;
1444 if (ch->lastslot + 1 < tags)
1445 tag = ffs(~(ch->oslots >> (ch->lastslot + 1)));
1446 else
1447 tag = 0;
1448 if (tag == 0 || tag + ch->lastslot >= tags)
1449 tag = ffs(~ch->oslots) - 1;
1450 else
1451 tag += ch->lastslot;
1452 ch->lastslot = tag;
1453 /* Occupy chosen slot. */
1454 slot = &ch->slot[tag];
1455 slot->ccb = ccb;
1456 /* Stop PM timer. */
1457 if (ch->numrslots == 0 && ch->pm_level > 3)
1458 callout_stop(&ch->pm_timer);
1459 /* Update channel stats. */
1460 ch->oslots |= (1 << tag);
1461 ch->numrslots++;
1462 ch->numrslotspd[ccb->ccb_h.target_id]++;
1463 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1464 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1465 ch->numtslots++;
1466 ch->numtslotspd[ccb->ccb_h.target_id]++;
1467 ch->taggedtarget = ccb->ccb_h.target_id;
1468 }
1469 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1470 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)))
1471 ch->aslots |= (1 << tag);
1472 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1473 slot->state = AHCI_SLOT_LOADING;
1474 bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map, ccb,
1475 ahci_dmasetprd, slot, 0);
1476 } else {
1477 slot->dma.nsegs = 0;
1478 ahci_execute_transaction(slot);
1479 }
1480 }
1481
1482 /* Locked by busdma engine. */
1483 static void
1484 ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1485 {
1486 struct ahci_slot *slot = arg;
1487 struct ahci_channel *ch = slot->ch;
1488 struct ahci_cmd_tab *ctp;
1489 struct ahci_dma_prd *prd;
1490 int i;
1491
1492 if (error) {
1493 device_printf(ch->dev, "DMA load error\n");
1494 ahci_end_transaction(slot, AHCI_ERR_INVALID);
1495 return;
1496 }
1497 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n"));
1498 /* Get a piece of the workspace for this request */
1499 ctp = (struct ahci_cmd_tab *)
1500 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot));
1501 /* Fill S/G table */
1502 prd = &ctp->prd_tab[0];
1503 for (i = 0; i < nsegs; i++) {
1504 prd[i].dba = htole64(segs[i].ds_addr);
1505 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK);
1506 }
1507 slot->dma.nsegs = nsegs;
1508 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1509 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ?
1510 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE));
1511 ahci_execute_transaction(slot);
1512 }
1513
1514 /* Must be called with channel locked. */
1515 static void
1516 ahci_execute_transaction(struct ahci_slot *slot)
1517 {
1518 struct ahci_channel *ch = slot->ch;
1519 struct ahci_cmd_tab *ctp;
1520 struct ahci_cmd_list *clp;
1521 union ccb *ccb = slot->ccb;
1522 int port = ccb->ccb_h.target_id & 0x0f;
1523 int fis_size, i, softreset;
1524 uint8_t *fis = ch->dma.rfis + 0x40;
1525 uint8_t val;
1526 uint16_t cmd_flags;
1527
1528 /* Get a piece of the workspace for this request */
1529 ctp = (struct ahci_cmd_tab *)
1530 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot));
1531 /* Setup the FIS for this request */
1532 if (!(fis_size = ahci_setup_fis(ch, ctp, ccb, slot->slot))) {
1533 device_printf(ch->dev, "Setting up SATA FIS failed\n");
1534 ahci_end_transaction(slot, AHCI_ERR_INVALID);
1535 return;
1536 }
1537 /* Setup the command list entry */
1538 clp = (struct ahci_cmd_list *)
1539 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot));
1540 cmd_flags =
1541 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) |
1542 (ccb->ccb_h.func_code == XPT_SCSI_IO ?
1543 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) |
1544 (fis_size / sizeof(u_int32_t)) |
1545 (port << 12);
1546 clp->prd_length = htole16(slot->dma.nsegs);
1547 /* Special handling for Soft Reset command. */
1548 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1549 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) {
1550 if (ccb->ataio.cmd.control & ATA_A_RESET) {
1551 softreset = 1;
1552 /* Kick controller into sane state */
1553 ahci_stop(ch);
1554 ahci_clo(ch);
1555 ahci_start(ch, 0);
1556 cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY;
1557 } else {
1558 softreset = 2;
1559 /* Prepare FIS receive area for check. */
1560 for (i = 0; i < 20; i++)
1561 fis[i] = 0xff;
1562 }
1563 } else
1564 softreset = 0;
1565 clp->bytecount = 0;
1566 clp->cmd_flags = htole16(cmd_flags);
1567 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET +
1568 (AHCI_CT_SIZE * slot->slot));
1569 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
1570 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1571 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
1572 BUS_DMASYNC_PREREAD);
1573 /* Set ACTIVE bit for NCQ commands. */
1574 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1575 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1576 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot);
1577 }
1578 /* If FBS is enabled, set PMP port. */
1579 if (ch->fbs_enabled) {
1580 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN |
1581 (port << AHCI_P_FBS_DEV_SHIFT));
1582 }
1583 /* Issue command to the controller. */
1584 slot->state = AHCI_SLOT_RUNNING;
1585 ch->rslots |= (1 << slot->slot);
1586 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot));
1587 /* Device reset commands doesn't interrupt. Poll them. */
1588 if (ccb->ccb_h.func_code == XPT_ATA_IO &&
1589 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) {
1590 int count, timeout = ccb->ccb_h.timeout * 100;
1591 enum ahci_err_type et = AHCI_ERR_NONE;
1592
1593 for (count = 0; count < timeout; count++) {
1594 DELAY(10);
1595 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot)))
1596 break;
1597 if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) &&
1598 softreset != 1) {
1599 #if 0
1600 device_printf(ch->dev,
1601 "Poll error on slot %d, TFD: %04x\n",
1602 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD));
1603 #endif
1604 et = AHCI_ERR_TFE;
1605 break;
1606 }
1607 /* Workaround for ATI SB600/SB700 chipsets. */
1608 if (ccb->ccb_h.target_id == 15 &&
1609 (ch->quirks & AHCI_Q_ATI_PMP_BUG) &&
1610 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) {
1611 et = AHCI_ERR_TIMEOUT;
1612 break;
1613 }
1614 }
1615
1616 /*
1617 * Some Marvell controllers require additional time
1618 * after soft reset to work properly. Setup delay
1619 * to 50ms after soft reset.
1620 */
1621 if (ch->quirks & AHCI_Q_MRVL_SR_DEL)
1622 DELAY(50000);
1623
1624 /*
1625 * Marvell HBAs with non-RAID firmware do not wait for
1626 * readiness after soft reset, so we have to wait here.
1627 * Marvell RAIDs do not have this problem, but instead
1628 * sometimes forget to update FIS receive area, breaking
1629 * this wait.
1630 */
1631 if ((ch->quirks & AHCI_Q_NOBSYRES) == 0 &&
1632 (ch->quirks & AHCI_Q_ATI_PMP_BUG) == 0 &&
1633 softreset == 2 && et == AHCI_ERR_NONE) {
1634 for ( ; count < timeout; count++) {
1635 bus_dmamap_sync(ch->dma.rfis_tag,
1636 ch->dma.rfis_map, BUS_DMASYNC_POSTREAD);
1637 val = fis[2];
1638 bus_dmamap_sync(ch->dma.rfis_tag,
1639 ch->dma.rfis_map, BUS_DMASYNC_PREREAD);
1640 if ((val & ATA_S_BUSY) == 0)
1641 break;
1642 DELAY(10);
1643 }
1644 }
1645
1646 if (timeout && (count >= timeout)) {
1647 device_printf(ch->dev, "Poll timeout on slot %d port %d\n",
1648 slot->slot, port);
1649 device_printf(ch->dev, "is %08x cs %08x ss %08x "
1650 "rs %08x tfd %02x serr %08x cmd %08x\n",
1651 ATA_INL(ch->r_mem, AHCI_P_IS),
1652 ATA_INL(ch->r_mem, AHCI_P_CI),
1653 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
1654 ATA_INL(ch->r_mem, AHCI_P_TFD),
1655 ATA_INL(ch->r_mem, AHCI_P_SERR),
1656 ATA_INL(ch->r_mem, AHCI_P_CMD));
1657 et = AHCI_ERR_TIMEOUT;
1658 }
1659
1660 /* Kick controller into sane state and enable FBS. */
1661 if (softreset == 2)
1662 ch->eslots |= (1 << slot->slot);
1663 ahci_end_transaction(slot, et);
1664 return;
1665 }
1666 /* Start command execution timeout */
1667 callout_reset_sbt(&slot->timeout, SBT_1MS * ccb->ccb_h.timeout / 2,
1668 0, (timeout_t*)ahci_timeout, slot, 0);
1669 return;
1670 }
1671
1672 /* Must be called with channel locked. */
1673 static void
1674 ahci_process_timeout(struct ahci_channel *ch)
1675 {
1676 int i;
1677
1678 mtx_assert(&ch->mtx, MA_OWNED);
1679 /* Handle the rest of commands. */
1680 for (i = 0; i < ch->numslots; i++) {
1681 /* Do we have a running request on slot? */
1682 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
1683 continue;
1684 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT);
1685 }
1686 }
1687
1688 /* Must be called with channel locked. */
1689 static void
1690 ahci_rearm_timeout(struct ahci_channel *ch)
1691 {
1692 int i;
1693
1694 mtx_assert(&ch->mtx, MA_OWNED);
1695 for (i = 0; i < ch->numslots; i++) {
1696 struct ahci_slot *slot = &ch->slot[i];
1697
1698 /* Do we have a running request on slot? */
1699 if (slot->state < AHCI_SLOT_RUNNING)
1700 continue;
1701 if ((ch->toslots & (1 << i)) == 0)
1702 continue;
1703 callout_reset_sbt(&slot->timeout,
1704 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0,
1705 (timeout_t*)ahci_timeout, slot, 0);
1706 }
1707 }
1708
1709 /* Locked by callout mechanism. */
1710 static void
1711 ahci_timeout(struct ahci_slot *slot)
1712 {
1713 struct ahci_channel *ch = slot->ch;
1714 device_t dev = ch->dev;
1715 uint32_t sstatus;
1716 int ccs;
1717 int i;
1718
1719 /* Check for stale timeout. */
1720 if (slot->state < AHCI_SLOT_RUNNING)
1721 return;
1722
1723 /* Check if slot was not being executed last time we checked. */
1724 if (slot->state < AHCI_SLOT_EXECUTING) {
1725 /* Check if slot started executing. */
1726 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
1727 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK)
1728 >> AHCI_P_CMD_CCS_SHIFT;
1729 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot ||
1730 ch->fbs_enabled || ch->wrongccs)
1731 slot->state = AHCI_SLOT_EXECUTING;
1732 else if ((ch->rslots & (1 << ccs)) == 0) {
1733 ch->wrongccs = 1;
1734 slot->state = AHCI_SLOT_EXECUTING;
1735 }
1736
1737 callout_reset_sbt(&slot->timeout,
1738 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0,
1739 (timeout_t*)ahci_timeout, slot, 0);
1740 return;
1741 }
1742
1743 device_printf(dev, "Timeout on slot %d port %d\n",
1744 slot->slot, slot->ccb->ccb_h.target_id & 0x0f);
1745 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x "
1746 "serr %08x cmd %08x\n",
1747 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI),
1748 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
1749 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR),
1750 ATA_INL(ch->r_mem, AHCI_P_CMD));
1751
1752 /* Handle frozen command. */
1753 if (ch->frozen) {
1754 union ccb *fccb = ch->frozen;
1755 ch->frozen = NULL;
1756 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1757 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1758 xpt_freeze_devq(fccb->ccb_h.path, 1);
1759 fccb->ccb_h.status |= CAM_DEV_QFRZN;
1760 }
1761 ahci_done(ch, fccb);
1762 }
1763 if (!ch->fbs_enabled && !ch->wrongccs) {
1764 /* Without FBS we know real timeout source. */
1765 ch->fatalerr = 1;
1766 /* Handle command with timeout. */
1767 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT);
1768 /* Handle the rest of commands. */
1769 for (i = 0; i < ch->numslots; i++) {
1770 /* Do we have a running request on slot? */
1771 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
1772 continue;
1773 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
1774 }
1775 } else {
1776 /* With FBS we wait for other commands timeout and pray. */
1777 if (ch->toslots == 0)
1778 xpt_freeze_simq(ch->sim, 1);
1779 ch->toslots |= (1 << slot->slot);
1780 if ((ch->rslots & ~ch->toslots) == 0)
1781 ahci_process_timeout(ch);
1782 else
1783 device_printf(dev, " ... waiting for slots %08x\n",
1784 ch->rslots & ~ch->toslots);
1785 }
1786 }
1787
1788 /* Must be called with channel locked. */
1789 static void
1790 ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et)
1791 {
1792 struct ahci_channel *ch = slot->ch;
1793 union ccb *ccb = slot->ccb;
1794 struct ahci_cmd_list *clp;
1795 int lastto;
1796 uint32_t sig;
1797
1798 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
1799 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1800 clp = (struct ahci_cmd_list *)
1801 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot));
1802 /* Read result registers to the result struct
1803 * May be incorrect if several commands finished same time,
1804 * so read only when sure or have to.
1805 */
1806 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1807 struct ata_res *res = &ccb->ataio.res;
1808
1809 if ((et == AHCI_ERR_TFE) ||
1810 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) {
1811 u_int8_t *fis = ch->dma.rfis + 0x40;
1812
1813 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
1814 BUS_DMASYNC_POSTREAD);
1815 if (ch->fbs_enabled) {
1816 fis += ccb->ccb_h.target_id * 256;
1817 res->status = fis[2];
1818 res->error = fis[3];
1819 } else {
1820 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD);
1821
1822 res->status = tfd;
1823 res->error = tfd >> 8;
1824 }
1825 res->lba_low = fis[4];
1826 res->lba_mid = fis[5];
1827 res->lba_high = fis[6];
1828 res->device = fis[7];
1829 res->lba_low_exp = fis[8];
1830 res->lba_mid_exp = fis[9];
1831 res->lba_high_exp = fis[10];
1832 res->sector_count = fis[12];
1833 res->sector_count_exp = fis[13];
1834
1835 /*
1836 * Some weird controllers do not return signature in
1837 * FIS receive area. Read it from PxSIG register.
1838 */
1839 if ((ch->quirks & AHCI_Q_ALTSIG) &&
1840 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
1841 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) {
1842 sig = ATA_INL(ch->r_mem, AHCI_P_SIG);
1843 res->lba_high = sig >> 24;
1844 res->lba_mid = sig >> 16;
1845 res->lba_low = sig >> 8;
1846 res->sector_count = sig;
1847 }
1848 } else
1849 bzero(res, sizeof(*res));
1850 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 &&
1851 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
1852 (ch->quirks & AHCI_Q_NOCOUNT) == 0) {
1853 ccb->ataio.resid =
1854 ccb->ataio.dxfer_len - le32toh(clp->bytecount);
1855 }
1856 } else {
1857 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
1858 (ch->quirks & AHCI_Q_NOCOUNT) == 0) {
1859 ccb->csio.resid =
1860 ccb->csio.dxfer_len - le32toh(clp->bytecount);
1861 }
1862 }
1863 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1864 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1865 (ccb->ccb_h.flags & CAM_DIR_IN) ?
1866 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1867 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map);
1868 }
1869 if (et != AHCI_ERR_NONE)
1870 ch->eslots |= (1 << slot->slot);
1871 /* In case of error, freeze device for proper recovery. */
1872 if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) &&
1873 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) {
1874 xpt_freeze_devq(ccb->ccb_h.path, 1);
1875 ccb->ccb_h.status |= CAM_DEV_QFRZN;
1876 }
1877 /* Set proper result status. */
1878 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1879 switch (et) {
1880 case AHCI_ERR_NONE:
1881 ccb->ccb_h.status |= CAM_REQ_CMP;
1882 if (ccb->ccb_h.func_code == XPT_SCSI_IO)
1883 ccb->csio.scsi_status = SCSI_STATUS_OK;
1884 break;
1885 case AHCI_ERR_INVALID:
1886 ch->fatalerr = 1;
1887 ccb->ccb_h.status |= CAM_REQ_INVALID;
1888 break;
1889 case AHCI_ERR_INNOCENT:
1890 ccb->ccb_h.status |= CAM_REQUEUE_REQ;
1891 break;
1892 case AHCI_ERR_TFE:
1893 case AHCI_ERR_NCQ:
1894 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
1895 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
1896 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
1897 } else {
1898 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR;
1899 }
1900 break;
1901 case AHCI_ERR_SATA:
1902 ch->fatalerr = 1;
1903 if (!ch->recoverycmd) {
1904 xpt_freeze_simq(ch->sim, 1);
1905 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1906 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
1907 }
1908 ccb->ccb_h.status |= CAM_UNCOR_PARITY;
1909 break;
1910 case AHCI_ERR_TIMEOUT:
1911 if (!ch->recoverycmd) {
1912 xpt_freeze_simq(ch->sim, 1);
1913 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1914 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
1915 }
1916 ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
1917 break;
1918 default:
1919 ch->fatalerr = 1;
1920 ccb->ccb_h.status |= CAM_REQ_CMP_ERR;
1921 }
1922 /* Free slot. */
1923 ch->oslots &= ~(1 << slot->slot);
1924 ch->rslots &= ~(1 << slot->slot);
1925 ch->aslots &= ~(1 << slot->slot);
1926 slot->state = AHCI_SLOT_EMPTY;
1927 slot->ccb = NULL;
1928 /* Update channel stats. */
1929 ch->numrslots--;
1930 ch->numrslotspd[ccb->ccb_h.target_id]--;
1931 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1932 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1933 ch->numtslots--;
1934 ch->numtslotspd[ccb->ccb_h.target_id]--;
1935 }
1936 /* Cancel timeout state if request completed normally. */
1937 if (et != AHCI_ERR_TIMEOUT) {
1938 lastto = (ch->toslots == (1 << slot->slot));
1939 ch->toslots &= ~(1 << slot->slot);
1940 if (lastto)
1941 xpt_release_simq(ch->sim, TRUE);
1942 }
1943 /* If it was first request of reset sequence and there is no error,
1944 * proceed to second request. */
1945 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1946 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
1947 (ccb->ataio.cmd.control & ATA_A_RESET) &&
1948 et == AHCI_ERR_NONE) {
1949 ccb->ataio.cmd.control &= ~ATA_A_RESET;
1950 ahci_begin_transaction(ch, ccb);
1951 return;
1952 }
1953 /* If it was our READ LOG command - process it. */
1954 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) {
1955 ahci_process_read_log(ch, ccb);
1956 /* If it was our REQUEST SENSE command - process it. */
1957 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) {
1958 ahci_process_request_sense(ch, ccb);
1959 /* If it was NCQ or ATAPI command error, put result on hold. */
1960 } else if (et == AHCI_ERR_NCQ ||
1961 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR &&
1962 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) {
1963 ch->hold[slot->slot] = ccb;
1964 ch->numhslots++;
1965 } else
1966 ahci_done(ch, ccb);
1967 /* If we have no other active commands, ... */
1968 if (ch->rslots == 0) {
1969 /* if there was fatal error - reset port. */
1970 if (ch->toslots != 0 || ch->fatalerr) {
1971 ahci_reset(ch);
1972 } else {
1973 /* if we have slots in error, we can reinit port. */
1974 if (ch->eslots != 0) {
1975 ahci_stop(ch);
1976 ahci_clo(ch);
1977 ahci_start(ch, 1);
1978 }
1979 /* if there commands on hold, we can do READ LOG. */
1980 if (!ch->recoverycmd && ch->numhslots)
1981 ahci_issue_recovery(ch);
1982 }
1983 /* If all the rest of commands are in timeout - give them chance. */
1984 } else if ((ch->rslots & ~ch->toslots) == 0 &&
1985 et != AHCI_ERR_TIMEOUT)
1986 ahci_rearm_timeout(ch);
1987 /* Unfreeze frozen command. */
1988 if (ch->frozen && !ahci_check_collision(ch, ch->frozen)) {
1989 union ccb *fccb = ch->frozen;
1990 ch->frozen = NULL;
1991 ahci_begin_transaction(ch, fccb);
1992 xpt_release_simq(ch->sim, TRUE);
1993 }
1994 /* Start PM timer. */
1995 if (ch->numrslots == 0 && ch->pm_level > 3 &&
1996 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) {
1997 callout_schedule(&ch->pm_timer,
1998 (ch->pm_level == 4) ? hz / 1000 : hz / 8);
1999 }
2000 }
2001
2002 static void
2003 ahci_issue_recovery(struct ahci_channel *ch)
2004 {
2005 union ccb *ccb;
2006 struct ccb_ataio *ataio;
2007 struct ccb_scsiio *csio;
2008 int i;
2009
2010 /* Find some held command. */
2011 for (i = 0; i < ch->numslots; i++) {
2012 if (ch->hold[i])
2013 break;
2014 }
2015 ccb = xpt_alloc_ccb_nowait();
2016 if (ccb == NULL) {
2017 device_printf(ch->dev, "Unable to allocate recovery command\n");
2018 completeall:
2019 /* We can't do anything -- complete held commands. */
2020 for (i = 0; i < ch->numslots; i++) {
2021 if (ch->hold[i] == NULL)
2022 continue;
2023 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2024 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL;
2025 ahci_done(ch, ch->hold[i]);
2026 ch->hold[i] = NULL;
2027 ch->numhslots--;
2028 }
2029 ahci_reset(ch);
2030 return;
2031 }
2032 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */
2033 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
2034 /* READ LOG */
2035 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG;
2036 ccb->ccb_h.func_code = XPT_ATA_IO;
2037 ccb->ccb_h.flags = CAM_DIR_IN;
2038 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
2039 ataio = &ccb->ataio;
2040 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT);
2041 if (ataio->data_ptr == NULL) {
2042 xpt_free_ccb(ccb);
2043 device_printf(ch->dev,
2044 "Unable to allocate memory for READ LOG command\n");
2045 goto completeall;
2046 }
2047 ataio->dxfer_len = 512;
2048 bzero(&ataio->cmd, sizeof(ataio->cmd));
2049 ataio->cmd.flags = CAM_ATAIO_48BIT;
2050 ataio->cmd.command = 0x2F; /* READ LOG EXT */
2051 ataio->cmd.sector_count = 1;
2052 ataio->cmd.sector_count_exp = 0;
2053 ataio->cmd.lba_low = 0x10;
2054 ataio->cmd.lba_mid = 0;
2055 ataio->cmd.lba_mid_exp = 0;
2056 } else {
2057 /* REQUEST SENSE */
2058 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE;
2059 ccb->ccb_h.recovery_slot = i;
2060 ccb->ccb_h.func_code = XPT_SCSI_IO;
2061 ccb->ccb_h.flags = CAM_DIR_IN;
2062 ccb->ccb_h.status = 0;
2063 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
2064 csio = &ccb->csio;
2065 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data;
2066 csio->dxfer_len = ch->hold[i]->csio.sense_len;
2067 csio->cdb_len = 6;
2068 bzero(&csio->cdb_io, sizeof(csio->cdb_io));
2069 csio->cdb_io.cdb_bytes[0] = 0x03;
2070 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len;
2071 }
2072 /* Freeze SIM while doing recovery. */
2073 ch->recoverycmd = 1;
2074 xpt_freeze_simq(ch->sim, 1);
2075 ahci_begin_transaction(ch, ccb);
2076 }
2077
2078 static void
2079 ahci_process_read_log(struct ahci_channel *ch, union ccb *ccb)
2080 {
2081 uint8_t *data;
2082 struct ata_res *res;
2083 int i;
2084
2085 ch->recoverycmd = 0;
2086
2087 data = ccb->ataio.data_ptr;
2088 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP &&
2089 (data[0] & 0x80) == 0) {
2090 for (i = 0; i < ch->numslots; i++) {
2091 if (!ch->hold[i])
2092 continue;
2093 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO)
2094 continue;
2095 if ((data[0] & 0x1F) == i) {
2096 res = &ch->hold[i]->ataio.res;
2097 res->status = data[2];
2098 res->error = data[3];
2099 res->lba_low = data[4];
2100 res->lba_mid = data[5];
2101 res->lba_high = data[6];
2102 res->device = data[7];
2103 res->lba_low_exp = data[8];
2104 res->lba_mid_exp = data[9];
2105 res->lba_high_exp = data[10];
2106 res->sector_count = data[12];
2107 res->sector_count_exp = data[13];
2108 } else {
2109 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2110 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ;
2111 }
2112 ahci_done(ch, ch->hold[i]);
2113 ch->hold[i] = NULL;
2114 ch->numhslots--;
2115 }
2116 } else {
2117 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP)
2118 device_printf(ch->dev, "Error while READ LOG EXT\n");
2119 else if ((data[0] & 0x80) == 0) {
2120 device_printf(ch->dev, "Non-queued command error in READ LOG EXT\n");
2121 }
2122 for (i = 0; i < ch->numslots; i++) {
2123 if (!ch->hold[i])
2124 continue;
2125 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO)
2126 continue;
2127 ahci_done(ch, ch->hold[i]);
2128 ch->hold[i] = NULL;
2129 ch->numhslots--;
2130 }
2131 }
2132 free(ccb->ataio.data_ptr, M_AHCI);
2133 xpt_free_ccb(ccb);
2134 xpt_release_simq(ch->sim, TRUE);
2135 }
2136
2137 static void
2138 ahci_process_request_sense(struct ahci_channel *ch, union ccb *ccb)
2139 {
2140 int i;
2141
2142 ch->recoverycmd = 0;
2143
2144 i = ccb->ccb_h.recovery_slot;
2145 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) {
2146 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID;
2147 } else {
2148 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2149 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL;
2150 }
2151 ahci_done(ch, ch->hold[i]);
2152 ch->hold[i] = NULL;
2153 ch->numhslots--;
2154 xpt_free_ccb(ccb);
2155 xpt_release_simq(ch->sim, TRUE);
2156 }
2157
2158 static void
2159 ahci_start(struct ahci_channel *ch, int fbs)
2160 {
2161 u_int32_t cmd;
2162
2163 /* Run the channel start callback, if any. */
2164 if (ch->start)
2165 ch->start(ch);
2166
2167 /* Clear SATA error register */
2168 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF);
2169 /* Clear any interrupts pending on this channel */
2170 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF);
2171 /* Configure FIS-based switching if supported. */
2172 if (ch->chcaps & AHCI_P_CMD_FBSCP) {
2173 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0;
2174 ATA_OUTL(ch->r_mem, AHCI_P_FBS,
2175 ch->fbs_enabled ? AHCI_P_FBS_EN : 0);
2176 }
2177 /* Start operations on this channel */
2178 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2179 cmd &= ~AHCI_P_CMD_PMA;
2180 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST |
2181 (ch->pm_present ? AHCI_P_CMD_PMA : 0));
2182 }
2183
2184 static void
2185 ahci_stop(struct ahci_channel *ch)
2186 {
2187 u_int32_t cmd;
2188 int timeout;
2189
2190 /* Kill all activity on this channel */
2191 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2192 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST);
2193 /* Wait for activity stop. */
2194 timeout = 0;
2195 do {
2196 DELAY(10);
2197 if (timeout++ > 50000) {
2198 device_printf(ch->dev, "stopping AHCI engine failed\n");
2199 break;
2200 }
2201 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR);
2202 ch->eslots = 0;
2203 }
2204
2205 static void
2206 ahci_clo(struct ahci_channel *ch)
2207 {
2208 u_int32_t cmd;
2209 int timeout;
2210
2211 /* Issue Command List Override if supported */
2212 if (ch->caps & AHCI_CAP_SCLO) {
2213 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2214 cmd |= AHCI_P_CMD_CLO;
2215 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd);
2216 timeout = 0;
2217 do {
2218 DELAY(10);
2219 if (timeout++ > 50000) {
2220 device_printf(ch->dev, "executing CLO failed\n");
2221 break;
2222 }
2223 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO);
2224 }
2225 }
2226
2227 static void
2228 ahci_stop_fr(struct ahci_channel *ch)
2229 {
2230 u_int32_t cmd;
2231 int timeout;
2232
2233 /* Kill all FIS reception on this channel */
2234 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2235 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE);
2236 /* Wait for FIS reception stop. */
2237 timeout = 0;
2238 do {
2239 DELAY(10);
2240 if (timeout++ > 50000) {
2241 device_printf(ch->dev, "stopping AHCI FR engine failed\n");
2242 break;
2243 }
2244 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR);
2245 }
2246
2247 static void
2248 ahci_start_fr(struct ahci_channel *ch)
2249 {
2250 u_int32_t cmd;
2251
2252 /* Start FIS reception on this channel */
2253 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2254 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE);
2255 }
2256
2257 static int
2258 ahci_wait_ready(struct ahci_channel *ch, int t, int t0)
2259 {
2260 int timeout = 0;
2261 uint32_t val;
2262
2263 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) &
2264 (ATA_S_BUSY | ATA_S_DRQ)) {
2265 if (timeout > t) {
2266 if (t != 0) {
2267 device_printf(ch->dev,
2268 "AHCI reset: device not ready after %dms "
2269 "(tfd = %08x)\n",
2270 MAX(t, 0) + t0, val);
2271 }
2272 return (EBUSY);
2273 }
2274 DELAY(1000);
2275 timeout++;
2276 }
2277 if (bootverbose)
2278 device_printf(ch->dev, "AHCI reset: device ready after %dms\n",
2279 timeout + t0);
2280 return (0);
2281 }
2282
2283 static void
2284 ahci_reset_to(void *arg)
2285 {
2286 struct ahci_channel *ch = arg;
2287
2288 if (ch->resetting == 0)
2289 return;
2290 ch->resetting--;
2291 if (ahci_wait_ready(ch, ch->resetting == 0 ? -1 : 0,
2292 (310 - ch->resetting) * 100) == 0) {
2293 ch->resetting = 0;
2294 ahci_start(ch, 1);
2295 xpt_release_simq(ch->sim, TRUE);
2296 return;
2297 }
2298 if (ch->resetting == 0) {
2299 ahci_clo(ch);
2300 ahci_start(ch, 1);
2301 xpt_release_simq(ch->sim, TRUE);
2302 return;
2303 }
2304 callout_schedule(&ch->reset_timer, hz / 10);
2305 }
2306
2307 static void
2308 ahci_reset(struct ahci_channel *ch)
2309 {
2310 struct ahci_controller *ctlr = device_get_softc(device_get_parent(ch->dev));
2311 int i;
2312
2313 xpt_freeze_simq(ch->sim, 1);
2314 if (bootverbose)
2315 device_printf(ch->dev, "AHCI reset...\n");
2316 /* Forget about previous reset. */
2317 if (ch->resetting) {
2318 ch->resetting = 0;
2319 callout_stop(&ch->reset_timer);
2320 xpt_release_simq(ch->sim, TRUE);
2321 }
2322 /* Requeue freezed command. */
2323 if (ch->frozen) {
2324 union ccb *fccb = ch->frozen;
2325 ch->frozen = NULL;
2326 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
2327 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
2328 xpt_freeze_devq(fccb->ccb_h.path, 1);
2329 fccb->ccb_h.status |= CAM_DEV_QFRZN;
2330 }
2331 ahci_done(ch, fccb);
2332 }
2333 /* Kill the engine and requeue all running commands. */
2334 ahci_stop(ch);
2335 for (i = 0; i < ch->numslots; i++) {
2336 /* Do we have a running request on slot? */
2337 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
2338 continue;
2339 /* XXX; Commands in loading state. */
2340 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
2341 }
2342 for (i = 0; i < ch->numslots; i++) {
2343 if (!ch->hold[i])
2344 continue;
2345 ahci_done(ch, ch->hold[i]);
2346 ch->hold[i] = NULL;
2347 ch->numhslots--;
2348 }
2349 if (ch->toslots != 0)
2350 xpt_release_simq(ch->sim, TRUE);
2351 ch->eslots = 0;
2352 ch->toslots = 0;
2353 ch->wrongccs = 0;
2354 ch->fatalerr = 0;
2355 /* Tell the XPT about the event */
2356 xpt_async(AC_BUS_RESET, ch->path, NULL);
2357 /* Disable port interrupts */
2358 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
2359 /* Reset and reconnect PHY, */
2360 if (!ahci_sata_phy_reset(ch)) {
2361 if (bootverbose)
2362 device_printf(ch->dev,
2363 "AHCI reset: device not found\n");
2364 ch->devices = 0;
2365 /* Enable wanted port interrupts */
2366 ATA_OUTL(ch->r_mem, AHCI_P_IE,
2367 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) |
2368 AHCI_P_IX_PRC | AHCI_P_IX_PC));
2369 xpt_release_simq(ch->sim, TRUE);
2370 return;
2371 }
2372 if (bootverbose)
2373 device_printf(ch->dev, "AHCI reset: device found\n");
2374 /* Wait for clearing busy status. */
2375 if (ahci_wait_ready(ch, dumping ? 31000 : 0, 0)) {
2376 if (dumping)
2377 ahci_clo(ch);
2378 else
2379 ch->resetting = 310;
2380 }
2381 ch->devices = 1;
2382 /* Enable wanted port interrupts */
2383 ATA_OUTL(ch->r_mem, AHCI_P_IE,
2384 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) |
2385 AHCI_P_IX_TFE | AHCI_P_IX_HBF |
2386 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF |
2387 ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC |
2388 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) |
2389 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR)));
2390 if (ch->resetting)
2391 callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, ch);
2392 else {
2393 ahci_start(ch, 1);
2394 xpt_release_simq(ch->sim, TRUE);
2395 }
2396 }
2397
2398 static int
2399 ahci_setup_fis(struct ahci_channel *ch, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag)
2400 {
2401 u_int8_t *fis = &ctp->cfis[0];
2402
2403 bzero(fis, 20);
2404 fis[0] = 0x27; /* host to device */
2405 fis[1] = (ccb->ccb_h.target_id & 0x0f);
2406 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
2407 fis[1] |= 0x80;
2408 fis[2] = ATA_PACKET_CMD;
2409 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2410 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA)
2411 fis[3] = ATA_F_DMA;
2412 else {
2413 fis[5] = ccb->csio.dxfer_len;
2414 fis[6] = ccb->csio.dxfer_len >> 8;
2415 }
2416 fis[7] = ATA_D_LBA;
2417 fis[15] = ATA_A_4BIT;
2418 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ?
2419 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes,
2420 ctp->acmd, ccb->csio.cdb_len);
2421 bzero(ctp->acmd + ccb->csio.cdb_len, 32 - ccb->csio.cdb_len);
2422 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) {
2423 fis[1] |= 0x80;
2424 fis[2] = ccb->ataio.cmd.command;
2425 fis[3] = ccb->ataio.cmd.features;
2426 fis[4] = ccb->ataio.cmd.lba_low;
2427 fis[5] = ccb->ataio.cmd.lba_mid;
2428 fis[6] = ccb->ataio.cmd.lba_high;
2429 fis[7] = ccb->ataio.cmd.device;
2430 fis[8] = ccb->ataio.cmd.lba_low_exp;
2431 fis[9] = ccb->ataio.cmd.lba_mid_exp;
2432 fis[10] = ccb->ataio.cmd.lba_high_exp;
2433 fis[11] = ccb->ataio.cmd.features_exp;
2434 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
2435 fis[12] = tag << 3;
2436 } else {
2437 fis[12] = ccb->ataio.cmd.sector_count;
2438 }
2439 fis[13] = ccb->ataio.cmd.sector_count_exp;
2440 fis[15] = ATA_A_4BIT;
2441 } else {
2442 fis[15] = ccb->ataio.cmd.control;
2443 }
2444 if (ccb->ataio.ata_flags & ATA_FLAG_AUX) {
2445 fis[16] = ccb->ataio.aux & 0xff;
2446 fis[17] = (ccb->ataio.aux >> 8) & 0xff;
2447 fis[18] = (ccb->ataio.aux >> 16) & 0xff;
2448 fis[19] = (ccb->ataio.aux >> 24) & 0xff;
2449 }
2450 return (20);
2451 }
2452
2453 static int
2454 ahci_sata_connect(struct ahci_channel *ch)
2455 {
2456 u_int32_t status;
2457 int timeout, found = 0;
2458
2459 /* Wait up to 100ms for "connect well" */
2460 for (timeout = 0; timeout < 1000 ; timeout++) {
2461 status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
2462 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE)
2463 found = 1;
2464 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) &&
2465 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) &&
2466 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE))
2467 break;
2468 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) {
2469 if (bootverbose) {
2470 device_printf(ch->dev, "SATA offline status=%08x\n",
2471 status);
2472 }
2473 return (0);
2474 }
2475 if (found == 0 && timeout >= 100)
2476 break;
2477 DELAY(100);
2478 }
2479 if (timeout >= 1000 || !found) {
2480 if (bootverbose) {
2481 device_printf(ch->dev,
2482 "SATA connect timeout time=%dus status=%08x\n",
2483 timeout * 100, status);
2484 }
2485 return (0);
2486 }
2487 if (bootverbose) {
2488 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n",
2489 timeout * 100, status);
2490 }
2491 /* Clear SATA error register */
2492 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff);
2493 return (1);
2494 }
2495
2496 static int
2497 ahci_sata_phy_reset(struct ahci_channel *ch)
2498 {
2499 int sata_rev;
2500 uint32_t val;
2501
2502 if (ch->listening) {
2503 val = ATA_INL(ch->r_mem, AHCI_P_CMD);
2504 val |= AHCI_P_CMD_SUD;
2505 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val);
2506 ch->listening = 0;
2507 }
2508 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision;
2509 if (sata_rev == 1)
2510 val = ATA_SC_SPD_SPEED_GEN1;
2511 else if (sata_rev == 2)
2512 val = ATA_SC_SPD_SPEED_GEN2;
2513 else if (sata_rev == 3)
2514 val = ATA_SC_SPD_SPEED_GEN3;
2515 else
2516 val = 0;
2517 ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
2518 ATA_SC_DET_RESET | val |
2519 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER);
2520 DELAY(1000);
2521 ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
2522 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 :
2523 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)));
2524 if (!ahci_sata_connect(ch)) {
2525 if (ch->caps & AHCI_CAP_SSS) {
2526 val = ATA_INL(ch->r_mem, AHCI_P_CMD);
2527 val &= ~AHCI_P_CMD_SUD;
2528 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val);
2529 ch->listening = 1;
2530 } else if (ch->pm_level > 0)
2531 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
2532 return (0);
2533 }
2534 return (1);
2535 }
2536
2537 static int
2538 ahci_check_ids(struct ahci_channel *ch, union ccb *ccb)
2539 {
2540
2541 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) {
2542 ccb->ccb_h.status = CAM_TID_INVALID;
2543 ahci_done(ch, ccb);
2544 return (-1);
2545 }
2546 if (ccb->ccb_h.target_lun != 0) {
2547 ccb->ccb_h.status = CAM_LUN_INVALID;
2548 ahci_done(ch, ccb);
2549 return (-1);
2550 }
2551 return (0);
2552 }
2553
2554 static void
2555 ahciaction(struct cam_sim *sim, union ccb *ccb)
2556 {
2557 struct ahci_channel *ch;
2558
2559 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n",
2560 ccb->ccb_h.func_code));
2561
2562 ch = (struct ahci_channel *)cam_sim_softc(sim);
2563 switch (ccb->ccb_h.func_code) {
2564 /* Common cases first */
2565 case XPT_ATA_IO: /* Execute the requested I/O operation */
2566 case XPT_SCSI_IO:
2567 if (ahci_check_ids(ch, ccb))
2568 return;
2569 if (ch->devices == 0 ||
2570 (ch->pm_present == 0 &&
2571 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) {
2572 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2573 break;
2574 }
2575 ccb->ccb_h.recovery_type = RECOVERY_NONE;
2576 /* Check for command collision. */
2577 if (ahci_check_collision(ch, ccb)) {
2578 /* Freeze command. */
2579 ch->frozen = ccb;
2580 /* We have only one frozen slot, so freeze simq also. */
2581 xpt_freeze_simq(ch->sim, 1);
2582 return;
2583 }
2584 ahci_begin_transaction(ch, ccb);
2585 return;
2586 case XPT_ABORT: /* Abort the specified CCB */
2587 /* XXX Implement */
2588 ccb->ccb_h.status = CAM_REQ_INVALID;
2589 break;
2590 case XPT_SET_TRAN_SETTINGS:
2591 {
2592 struct ccb_trans_settings *cts = &ccb->cts;
2593 struct ahci_device *d;
2594
2595 if (ahci_check_ids(ch, ccb))
2596 return;
2597 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2598 d = &ch->curr[ccb->ccb_h.target_id];
2599 else
2600 d = &ch->user[ccb->ccb_h.target_id];
2601 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION)
2602 d->revision = cts->xport_specific.sata.revision;
2603 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE)
2604 d->mode = cts->xport_specific.sata.mode;
2605 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT)
2606 d->bytecount = min(8192, cts->xport_specific.sata.bytecount);
2607 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS)
2608 d->tags = min(ch->numslots, cts->xport_specific.sata.tags);
2609 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM)
2610 ch->pm_present = cts->xport_specific.sata.pm_present;
2611 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI)
2612 d->atapi = cts->xport_specific.sata.atapi;
2613 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS)
2614 d->caps = cts->xport_specific.sata.caps;
2615 ccb->ccb_h.status = CAM_REQ_CMP;
2616 break;
2617 }
2618 case XPT_GET_TRAN_SETTINGS:
2619 /* Get default/user set transfer settings for the target */
2620 {
2621 struct ccb_trans_settings *cts = &ccb->cts;
2622 struct ahci_device *d;
2623 uint32_t status;
2624
2625 if (ahci_check_ids(ch, ccb))
2626 return;
2627 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2628 d = &ch->curr[ccb->ccb_h.target_id];
2629 else
2630 d = &ch->user[ccb->ccb_h.target_id];
2631 cts->protocol = PROTO_UNSPECIFIED;
2632 cts->protocol_version = PROTO_VERSION_UNSPECIFIED;
2633 cts->transport = XPORT_SATA;
2634 cts->transport_version = XPORT_VERSION_UNSPECIFIED;
2635 cts->proto_specific.valid = 0;
2636 cts->xport_specific.sata.valid = 0;
2637 if (cts->type == CTS_TYPE_CURRENT_SETTINGS &&
2638 (ccb->ccb_h.target_id == 15 ||
2639 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) {
2640 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK;
2641 if (status & 0x0f0) {
2642 cts->xport_specific.sata.revision =
2643 (status & 0x0f0) >> 4;
2644 cts->xport_specific.sata.valid |=
2645 CTS_SATA_VALID_REVISION;
2646 }
2647 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D;
2648 if (ch->pm_level) {
2649 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC))
2650 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ;
2651 if (ch->caps2 & AHCI_CAP2_APST)
2652 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST;
2653 }
2654 if ((ch->caps & AHCI_CAP_SNCQ) &&
2655 (ch->quirks & AHCI_Q_NOAA) == 0)
2656 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA;
2657 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN;
2658 cts->xport_specific.sata.caps &=
2659 ch->user[ccb->ccb_h.target_id].caps;
2660 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2661 } else {
2662 cts->xport_specific.sata.revision = d->revision;
2663 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION;
2664 cts->xport_specific.sata.caps = d->caps;
2665 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2666 }
2667 cts->xport_specific.sata.mode = d->mode;
2668 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE;
2669 cts->xport_specific.sata.bytecount = d->bytecount;
2670 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT;
2671 cts->xport_specific.sata.pm_present = ch->pm_present;
2672 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM;
2673 cts->xport_specific.sata.tags = d->tags;
2674 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS;
2675 cts->xport_specific.sata.atapi = d->atapi;
2676 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI;
2677 ccb->ccb_h.status = CAM_REQ_CMP;
2678 break;
2679 }
2680 case XPT_RESET_BUS: /* Reset the specified SCSI bus */
2681 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
2682 ahci_reset(ch);
2683 ccb->ccb_h.status = CAM_REQ_CMP;
2684 break;
2685 case XPT_TERM_IO: /* Terminate the I/O process */
2686 /* XXX Implement */
2687 ccb->ccb_h.status = CAM_REQ_INVALID;
2688 break;
2689 case XPT_PATH_INQ: /* Path routing inquiry */
2690 {
2691 struct ccb_pathinq *cpi = &ccb->cpi;
2692
2693 cpi->version_num = 1; /* XXX??? */
2694 cpi->hba_inquiry = PI_SDTR_ABLE;
2695 if (ch->caps & AHCI_CAP_SNCQ)
2696 cpi->hba_inquiry |= PI_TAG_ABLE;
2697 if (ch->caps & AHCI_CAP_SPM)
2698 cpi->hba_inquiry |= PI_SATAPM;
2699 cpi->target_sprt = 0;
2700 cpi->hba_misc = PIM_SEQSCAN | PIM_UNMAPPED;
2701 if ((ch->quirks & AHCI_Q_NOAUX) == 0)
2702 cpi->hba_misc |= PIM_ATA_EXT;
2703 cpi->hba_eng_cnt = 0;
2704 if (ch->caps & AHCI_CAP_SPM)
2705 cpi->max_target = 15;
2706 else
2707 cpi->max_target = 0;
2708 cpi->max_lun = 0;
2709 cpi->initiator_id = 0;
2710 cpi->bus_id = cam_sim_bus(sim);
2711 cpi->base_transfer_speed = 150000;
2712 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2713 strlcpy(cpi->hba_vid, "AHCI", HBA_IDLEN);
2714 strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
2715 cpi->unit_number = cam_sim_unit(sim);
2716 cpi->transport = XPORT_SATA;
2717 cpi->transport_version = XPORT_VERSION_UNSPECIFIED;
2718 cpi->protocol = PROTO_ATA;
2719 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED;
2720 cpi->maxio = MAXPHYS;
2721 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */
2722 if (ch->quirks & AHCI_Q_MAXIO_64K)
2723 cpi->maxio = min(cpi->maxio, 128 * 512);
2724 cpi->hba_vendor = ch->vendorid;
2725 cpi->hba_device = ch->deviceid;
2726 cpi->hba_subvendor = ch->subvendorid;
2727 cpi->hba_subdevice = ch->subdeviceid;
2728 cpi->ccb_h.status = CAM_REQ_CMP;
2729 break;
2730 }
2731 default:
2732 ccb->ccb_h.status = CAM_REQ_INVALID;
2733 break;
2734 }
2735 ahci_done(ch, ccb);
2736 }
2737
2738 static void
2739 ahcipoll(struct cam_sim *sim)
2740 {
2741 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim);
2742 uint32_t istatus;
2743
2744 /* Read interrupt statuses and process if any. */
2745 istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
2746 if (istatus != 0)
2747 ahci_ch_intr_main(ch, istatus);
2748 if (ch->resetting != 0 &&
2749 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) {
2750 ch->resetpolldiv = 1000;
2751 ahci_reset_to(ch);
2752 }
2753 }
2754
2755 devclass_t ahci_devclass;
2756
2757 MODULE_VERSION(ahci, 1);
2758 MODULE_DEPEND(ahci, cam, 1, 1, 1);
Cache object: 97d5a926dd01f4fe054a365096b4529f
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